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Sander de Smalen [Mon, 18 Dec 2017 16:48:53 +0000 (16:48 +0000)]
[AArch64][SVE] Asm: Improve diagnostics further when +sve is not specified
Summary: Patch [4/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch further improves diagnostic messages for when the SVE feature is not specified.
Reviewers: rengolin, fhahn, olista01, echristo, efriedma
Reviewed By: fhahn
Subscribers: sdardis, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D40363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320992
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Simon Dardis [Mon, 18 Dec 2017 15:56:40 +0000 (15:56 +0000)]
Reland "[mips] Fix the target specific instruction verifier"
Fix an off by one error in the bounds checking for 'dinsu' and update
the ranges in the test comments so that they are accurate.
This version has the correct commit message.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D41183
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320991
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Sean Fertile [Mon, 18 Dec 2017 15:31:14 +0000 (15:31 +0000)]
[Memcpy Loop Lowering] Remove the fixed int8 lowering.
Switch over to the lowering that uses target supplied operand types.
Differential Revision: https://reviews.llvm.org/D41201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320989
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Sander de Smalen [Mon, 18 Dec 2017 14:34:24 +0000 (14:34 +0000)]
[TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction
Summary:
When emitting a diagnostic for an invalid operand, a specific diagnostic
should only be reported when the instruction being matched is actually
enabled by the feature flags.
Patch [3/4] in a series to add parsing of predicates and properly parse SVE
ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when
the SVE feature is not specified.
Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund
Reviewed By: olista01, sdardis
Subscribers: fhahn, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D40362
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320986
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Max Kazantsev [Mon, 18 Dec 2017 14:23:30 +0000 (14:23 +0000)]
[LVI] Support for ashr in LVI
Enhance LVI to analyze the ‘ashr’ binary operation. This leverages the infrastructure in ConstantRange for the ashr operation.
Patch by Surya Kumari Jangala!
Differential Revision: https://reviews.llvm.org/D40886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320983
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Diana Picus [Mon, 18 Dec 2017 13:22:28 +0000 (13:22 +0000)]
[ARM GlobalISel] Fix G_(UN)MERGE_VALUES handling after r319524
r319524 has made more G_MERGE_VALUES/G_UNMERGE_VALUES pairs legal than
are supported by the rest of the pipeline. Restrict that to only the
cases that we can currently handle: packing 32-bit values into 64-bit
ones, when we have hardware FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320980
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Benjamin Kramer [Mon, 18 Dec 2017 13:20:26 +0000 (13:20 +0000)]
Constexprify LaneBitmask factory methods.
This avoids global constructors when they're used in a global constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320979
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Max Kazantsev [Mon, 18 Dec 2017 13:01:32 +0000 (13:01 +0000)]
[ConstantRange] Support for ashr in ConstantRange computation
Extend the ConstantRange implementation to compute the range of possible values resulting from an arithmetic right shift operation.
There will be a follow up patch to leverage this constant range infrastructure in LazyValueInfo.
Patch by Surya Kumari Jangala!
Differential Revision: https://reviews.llvm.org/D40881
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320976
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Simon Dardis [Mon, 18 Dec 2017 12:30:34 +0000 (12:30 +0000)]
Revert "[mips] Fix the target specific instruction verifier"
This reverts commit r320974. The commit message lacked the Differential Revison: line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320975
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Simon Dardis [Mon, 18 Dec 2017 12:24:17 +0000 (12:24 +0000)]
[mips] Fix the target specific instruction verifier
Fix an off by one error in the bounds checking for 'dinsu' and update
the ranges in the test comments so that they are accurate.
Reviewers: atanasyan
https://reviews.llvm.org/D41183
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320974
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Sander de Smalen [Mon, 18 Dec 2017 11:29:59 +0000 (11:29 +0000)]
[AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors)
Summary: Patch [2/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.
Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, llvm-commits, tschuett
Differential Revision: https://reviews.llvm.org/D40361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320973
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Sander de Smalen [Mon, 18 Dec 2017 11:26:34 +0000 (11:26 +0000)]
[AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support
Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.
Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, llvm-commits, tschuett
Differential Revision: https://reviews.llvm.org/D40360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320970
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Eugene Leviant [Mon, 18 Dec 2017 10:53:45 +0000 (10:53 +0000)]
[ThinLTO] Remove unused code
This is a re-commit of r320464, after patch for gold plugin
was landed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320968
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Tim Northover [Mon, 18 Dec 2017 10:36:00 +0000 (10:36 +0000)]
AArch64: work around how Cyclone handles "movi.2d vD, #0".
For Cylone, the instruction "movi.2d vD, #0" is executed incorrectly in some rare
circumstances. Work around the issue conservatively by avoiding the instruction entirely.
This patch changes CodeGen so that problematic instructions are never
generated, and the AsmParser so that an equivalent instruction is used (with a
warning).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320965
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Igor Laevsky [Mon, 18 Dec 2017 10:31:58 +0000 (10:31 +0000)]
[TargetLibraryInfo] Discard library functions with incorrectly sized integers
Differential Revision: https://reviews.llvm.org/D41184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320964
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Sam Parker [Mon, 18 Dec 2017 10:08:03 +0000 (10:08 +0000)]
[ARM] Adjust test checks
Correct the CHECK-LABELS of a couple of dag combine tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320963
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Sam Parker [Mon, 18 Dec 2017 10:04:27 +0000 (10:04 +0000)]
[DAGCombine] Move AND nodes to multiple load leaves
Search from AND nodes to find whether they can be propagated back to
loads, so that the AND and load can be combined into a narrow load.
We search through OR, XOR and other AND nodes and all bar one of the
leaves are required to be loads or constants. The exception node then
needs to be masked off meaning that the 'and' isn't removed, but the
loads(s) are narrowed still.
Differential Revision: https://reviews.llvm.org/D41177
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320962
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Clement Courbet [Mon, 18 Dec 2017 07:32:48 +0000 (07:32 +0000)]
[NFC][CodeGen][ExpandMemCmp] Fix documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320960
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Craig Topper [Mon, 18 Dec 2017 07:21:58 +0000 (07:21 +0000)]
[X86] Use mattr instead of mcpu in some of the cost model tests.
Based on the names of the check lines, features seems more appropriate that cpu.
Spotted while prototyping my patch to make 512-bit vectors illegal on SKX sometimes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320959
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Hiroshi Inoue [Mon, 18 Dec 2017 06:47:37 +0000 (06:47 +0000)]
[SROA] Disable non-whole-alloca splits by default
This patch introduce a switch to control splitting of non-whole-alloca slices with default off.
The switch will be default on again after fixing an issue reported in PR35657.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320958
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Craig Topper [Mon, 18 Dec 2017 04:50:05 +0000 (04:50 +0000)]
[X86] Fix mistake that I made when splitting up the setOperationAction calls recently.
The block I moved things that need BWI and 512-bit or VLX is incorrectly qualified with just hasBWI || hasVLX. Here I've qualified it with hasBWI && (hasAVX512 || hasVLX) where the hasAVX512 will be replaced with allowing 512-bit vectors in an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320957
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Serguei Katkov [Mon, 18 Dec 2017 04:25:07 +0000 (04:25 +0000)]
[CGP] Fix the handling select inst in complex addressing mode
When we put the value in select placeholder we must pass
the value through simplification tracker due to the value might
be already simplified and erased.
This is a fix for PR35658.
Reviewers: john.brawn, uabelho
Reviewed By: john.brawn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41251
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320956
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Sanjay Patel [Mon, 18 Dec 2017 00:38:45 +0000 (00:38 +0000)]
[x86] add tests for finite libcall lowering (PR35672); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320955
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Bjorn Steinbrink [Sun, 17 Dec 2017 21:20:16 +0000 (21:20 +0000)]
Re-commit "Properly handle multi-element and dynamically sized allocas in getPointerDereferenceableBytes()""
llvm-clang-x86_64-expensive-checks-win is still broken, so the failure
seems unrelated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320953
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Craig Topper [Sun, 17 Dec 2017 18:31:36 +0000 (18:31 +0000)]
[X86] Add test cases that show cases where buildvector of extract and inserts should be turned into fmsubadd.
This is a follow up to the fmaddsub support added in r320950. Hopefully in the future we can fix lowering to handle this fmsubadd too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320951
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Craig Topper [Sun, 17 Dec 2017 18:23:45 +0000 (18:23 +0000)]
[X86] Make the code that creates fmaddsub from build_vector of extracts and inserts functional and add tests.
Summary:
We had no tests for this and we couldn't do the optimization because of a bad use count check. We need to know how many non-undef pieces of the build vector were filled in and ensure our use count is equal to that. But on the shuffle combine version we need the use count to be 2.
The missing coverage was noticed during the review of D40335.
Reviewers: RKSimon, zvi, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41133
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320950
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Simon Pilgrim [Sun, 17 Dec 2017 18:20:42 +0000 (18:20 +0000)]
[X86] Regenerate truncated rotation tests + add missing 32-bit checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320949
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Sam Clegg [Sun, 17 Dec 2017 17:50:07 +0000 (17:50 +0000)]
use uint32_t
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320947
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Sam Clegg [Sun, 17 Dec 2017 17:50:07 +0000 (17:50 +0000)]
[WebAssembly] Export some more info on wasm funtions
Summary:
These fields are useful for lld's gc-sections support
Also remove an unused field.
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish
Differential Revision: https://reviews.llvm.org/D41320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320946
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Bjorn Steinbrink [Sun, 17 Dec 2017 15:16:58 +0000 (15:16 +0000)]
Revert "Properly handle multi-element and dynamically sized allocas in getPointerDereferenceableBytes()"
This reverts commit
217067d5179882de9deb60d2e866befea4c126e7.
Fails on llvm-clang-x86_64-expensive-checks-win
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320945
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Bjorn Steinbrink [Sun, 17 Dec 2017 15:16:51 +0000 (15:16 +0000)]
Revert "Treat sret arguments as being dereferenceable in getPointerDereferenceableBytes()"
This reverts commit
8b7a7660a3904b2088bc594311bcea2c651def08.
I didn't mean to commit this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320944
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Bjorn Steinbrink [Sun, 17 Dec 2017 15:11:52 +0000 (15:11 +0000)]
Treat sret arguments as being dereferenceable in getPointerDereferenceableBytes()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320943
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Simon Pilgrim [Sun, 17 Dec 2017 11:01:33 +0000 (11:01 +0000)]
Remove superfluous break after a return. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320941
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Craig Topper [Sun, 17 Dec 2017 03:16:23 +0000 (03:16 +0000)]
[X86DomainReassignment] Store legal domains in a std::bitset instead of using a SmallVector that really only ever has one element as a set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320940
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Bjorn Steinbrink [Sun, 17 Dec 2017 02:37:42 +0000 (02:37 +0000)]
Properly handle byval arguments in getPointerDereferenceableBytes()
Summary:
For byval arguments, the number of dereferenceable bytes is equal to
the size of the pointee, not the pointer.
Reviewers: hfinkel, rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320939
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Bjorn Steinbrink [Sun, 17 Dec 2017 01:54:25 +0000 (01:54 +0000)]
Properly handle multi-element and dynamically sized allocas in getPointerDereferenceableBytes()
Reviewers: hfinkel, rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320938
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Craig Topper [Sun, 17 Dec 2017 01:35:48 +0000 (01:35 +0000)]
[X86] Use extract_vector_elt instead of X86ISD::VEXTRACT for isel of vXi1 extractions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320937
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Craig Topper [Sun, 17 Dec 2017 01:35:47 +0000 (01:35 +0000)]
[X86] Canonicalize extract_vector_elt from vXi1 to always return MVT::i32.
This allows us to remove some isel patterns that allowed MVT::i8 result type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320936
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Craig Topper [Sun, 17 Dec 2017 01:35:44 +0000 (01:35 +0000)]
[X86] Don't create X86ISD::VEXTRACT nodes directly. Use EXTRACT_VECTOR_ELT and allow that to be legaized to VEXTRACT.
I think we can remove the VEXTRACT node completely and use a canonicalized EXTRACT_VECTOR_ELT instead. This is a first step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320935
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Simon Pilgrim [Sat, 16 Dec 2017 23:37:51 +0000 (23:37 +0000)]
Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320934
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Simon Pilgrim [Sat, 16 Dec 2017 23:32:18 +0000 (23:32 +0000)]
[X86][AVX] lowerVectorShuffleAsBroadcast - aggressively peek through BITCASTs
Assuming we can safely adjust the broadcast index for the new type to keep it suitably aligned, then peek through BITCASTs when looking for the broadcast source.
Fixes PR32007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320933
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Simon Pilgrim [Sat, 16 Dec 2017 23:09:57 +0000 (23:09 +0000)]
[X86][AVX] Use extract128BitVector helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320932
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Simon Pilgrim [Sat, 16 Dec 2017 22:57:17 +0000 (22:57 +0000)]
[X86][AVX] Fix failed broadcast fold
Strip excess BITCASTs from EXTRACT_SUBVECTOR input
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320930
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Sean Fertile [Sat, 16 Dec 2017 22:41:39 +0000 (22:41 +0000)]
[Memcpy Loop Lowering] Only calculate residual size/bytes copied when needed.
If the loop operand type is int8 then there will be no residual loop for the
unknown size expansion. Dont create the residual-size and bytes-copied values
when they are not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320929
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Craig Topper [Sat, 16 Dec 2017 21:12:24 +0000 (21:12 +0000)]
[X86] Don't pass a zero input to the passthru operand of getVectorMaskingNode/getScalarMaskingNode when its going to emit an ISD::OR/ISD::AND. NFCI
In those cases, the pass thru operand of the methods isn't used. The calls to the scalar version were passing a MVT::i1 zero, which is an illegal type at the stage this code runs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320928
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Craig Topper [Sat, 16 Dec 2017 21:12:23 +0000 (21:12 +0000)]
[X86] Have getVectorMaskingNode return an ISD::AND for X86ISD::VPSHUFBITQMB instead of creating a select with one input being 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320927
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Craig Topper [Sat, 16 Dec 2017 19:31:36 +0000 (19:31 +0000)]
[X86] When using vpopcntdq for ctpop of v8i16 vectors, only promote to v8i32.
Previously we promoted to v8i64, but we don't need to go all the way to 512-bits. If we have VLX we can use the 256-bit instruction. And even if we don't have VLX we can widen v8i32 to v16i32 and drop the upper half.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320926
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Craig Topper [Sat, 16 Dec 2017 18:35:31 +0000 (18:35 +0000)]
[X86] Combine some more scheduler model entries using regular expressions.
We had a lot of separate 32 and 64 instructions that had the same scheduling data. This merges them into the same regular expression. This is pretty consistent with a lot of other instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320924
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Craig Topper [Sat, 16 Dec 2017 18:35:29 +0000 (18:35 +0000)]
[X86] Use instrs instead of instregex for gather/scatter instructions in the scheduler models. Combine into single InstrRW entries.
The reduces the number of scheduler groups in subtarget info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320923
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Simon Pilgrim [Sat, 16 Dec 2017 17:18:15 +0000 (17:18 +0000)]
[InstCombine] Regenerate FMUL/FMA combine tests with update_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320922
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Sanjay Patel [Sat, 16 Dec 2017 16:41:17 +0000 (16:41 +0000)]
[InstCombine] canonicalize shifty abs(): ashr+add+xor --> cmp+neg+sel
We want to do this for 2 reasons:
1. Value tracking does not recognize the ashr variant, so it would fail to match for cases like D39766.
2. DAGCombiner does better at producing optimal codegen when we have the cmp+sel pattern.
More detail about what happens in the backend:
1. DAGCombiner has a generic transform for all targets to convert the scalar cmp+sel variant of abs
into the shift variant. That is the opposite of this IR canonicalization.
2. DAGCombiner has a generic transform for all targets to convert the vector cmp+sel variant of abs
into either an ABS node or the shift variant. That is again the opposite of this IR canonicalization.
3. DAGCombiner has a generic transform for all targets to convert the exact shift variants produced by #1 or #2
into an ISD::ABS node. Note: It would be an efficiency improvement if we had #1 go directly to an ABS node
when that's legal/custom.
4. The pattern matching above is incomplete, so it is possible to escape the intended/optimal codegen in a
variety of ways.
a. For #2, the vector path is missing the case for setlt with a '1' constant.
b. For #3, we are missing a match for commuted versions of the shift variants.
5. Therefore, this IR canonicalization can only help get us to the optimal codegen. The version of cmp+sel
produced by this patch will be recognized in the DAG and converted to an ABS node when possible or the
shift sequence when not.
6. In the following examples with this patch applied, we may get conditional moves rather than the shift
produced by the generic DAGCombiner transforms. The conditional move is created using a target-specific
decision for any given target. Whether it is optimal or not for a particular subtarget may be up for debate.
define i32 @abs_shifty(i32 %x) {
%signbit = ashr i32 %x, 31
%add = add i32 %signbit, %x
%abs = xor i32 %signbit, %add
ret i32 %abs
}
define i32 @abs_cmpsubsel(i32 %x) {
%cmp = icmp slt i32 %x, zeroinitializer
%sub = sub i32 zeroinitializer, %x
%abs = select i1 %cmp, i32 %sub, i32 %x
ret i32 %abs
}
define <4 x i32> @abs_shifty_vec(<4 x i32> %x) {
%signbit = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
%add = add <4 x i32> %signbit, %x
%abs = xor <4 x i32> %signbit, %add
ret <4 x i32> %abs
}
define <4 x i32> @abs_cmpsubsel_vec(<4 x i32> %x) {
%cmp = icmp slt <4 x i32> %x, zeroinitializer
%sub = sub <4 x i32> zeroinitializer, %x
%abs = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> %x
ret <4 x i32> %abs
}
> $ ./opt -instcombine shiftyabs.ll -S | ./llc -o - -mtriple=x86_64 -mattr=avx
> abs_shifty:
> movl %edi, %eax
> negl %eax
> cmovll %edi, %eax
> retq
>
> abs_cmpsubsel:
> movl %edi, %eax
> negl %eax
> cmovll %edi, %eax
> retq
>
> abs_shifty_vec:
> vpabsd %xmm0, %xmm0
> retq
>
> abs_cmpsubsel_vec:
> vpabsd %xmm0, %xmm0
> retq
>
> $ ./opt -instcombine shiftyabs.ll -S | ./llc -o - -mtriple=aarch64
> abs_shifty:
> cmp w0, #0 // =0
> cneg w0, w0, mi
> ret
>
> abs_cmpsubsel:
> cmp w0, #0 // =0
> cneg w0, w0, mi
> ret
>
> abs_shifty_vec:
> abs v0.4s, v0.4s
> ret
>
> abs_cmpsubsel_vec:
> abs v0.4s, v0.4s
> ret
>
> $ ./opt -instcombine shiftyabs.ll -S | ./llc -o - -mtriple=powerpc64le
> abs_shifty:
> srawi 4, 3, 31
> add 3, 3, 4
> xor 3, 3, 4
> blr
>
> abs_cmpsubsel:
> srawi 4, 3, 31
> add 3, 3, 4
> xor 3, 3, 4
> blr
>
> abs_shifty_vec:
> vspltisw 3, -16
> vspltisw 4, 15
> vsubuwm 3, 4, 3
> vsraw 3, 2, 3
> vadduwm 2, 2, 3
> xxlxor 34, 34, 35
> blr
>
> abs_cmpsubsel_vec:
> vspltisw 3, -16
> vspltisw 4, 15
> vsubuwm 3, 4, 3
> vsraw 3, 2, 3
> vadduwm 2, 2, 3
> xxlxor 34, 34, 35
> blr
>
Differential Revision: https://reviews.llvm.org/D40984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320921
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 16 Dec 2017 08:25:30 +0000 (08:25 +0000)]
[X86] Remove GCCBuiltin from kand/kandn/kor/kxor/kxnor/knot intrinsics so clang can implement with native IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320918
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 16 Dec 2017 06:58:30 +0000 (06:58 +0000)]
[X86] Remove unneeded code for handling the old kunpck intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320917
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Sat, 16 Dec 2017 05:10:20 +0000 (05:10 +0000)]
Move Transforms/LoopVectorize/consecutive-ptr-cg-bug.ll into the X86 subdirectory
This test depends on X86's TTI; move into the X86 subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320914
91177308-0d34-0410-b5e6-
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Hal Finkel [Sat, 16 Dec 2017 02:55:24 +0000 (02:55 +0000)]
[LV] Extend InstWidening with CM_Widen_Recursive
Changes to the original scalar loop during LV code gen cause the return value
of Legal->isConsecutivePtr() to be inconsistent with the return value during
legal/cost phases (further analysis and information of the bug is in D39346).
This patch is an alternative fix to PR34965 following the CM_Widen approach
proposed by Ayal and Gil in D39346. It extends InstWidening enum with
CM_Widen_Reverse to properly record the widening decision for consecutive
reverse memory accesses and, consequently, get rid of the
Legal->isConsetuviePtr() call in LV code gen. I think this is a simpler/cleaner
solution to PR34965 than the one in D39346.
Fixes PR34965.
Patch by Diego Caballero, thanks!
Differential Revision: https://reviews.llvm.org/D40742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320913
91177308-0d34-0410-b5e6-
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Galina Kistanova [Sat, 16 Dec 2017 02:54:17 +0000 (02:54 +0000)]
Fixed warning 'function declaration isn’t a prototype [-Werror=strict-prototypes]'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320912
91177308-0d34-0410-b5e6-
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Hal Finkel [Sat, 16 Dec 2017 02:42:18 +0000 (02:42 +0000)]
[PowerPC, AsmParser] Enable the mnemonic spell corrector
r307148 added an assembly mnemonic spelling correction support and enabled it
on ARM. This enables that support on PowerPC as well.
Patch by Dmitry Venikov, thanks!
Differential Revision: https://reviews.llvm.org/D40552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320911
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 16 Dec 2017 02:40:28 +0000 (02:40 +0000)]
[X86] Add 128 and 256-bit VPOPCNTDQ instructions. Adjust some tablegen classes LZCNT/POPCNT.
I think when this instruction was first published it was only for a Knights CPU and thus VLX version was missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320910
91177308-0d34-0410-b5e6-
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Vitaly Buka [Sat, 16 Dec 2017 02:40:20 +0000 (02:40 +0000)]
[LTO] Update tests for r320905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320909
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Sat, 16 Dec 2017 02:12:35 +0000 (02:12 +0000)]
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320907
91177308-0d34-0410-b5e6-
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Sam Clegg [Sat, 16 Dec 2017 02:10:16 +0000 (02:10 +0000)]
[WebAssembly] Return ArrayRef's rather than const std::vector&
From working on lld I've learned this is generally the
preferred way for several reasons (e.g. more concise, improves
encapsulation).
Differential Revision: https://reviews.llvm.org/D41265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320906
91177308-0d34-0410-b5e6-
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Vitaly Buka [Sat, 16 Dec 2017 02:10:00 +0000 (02:10 +0000)]
[LTO] Make processing of combined module more consistent
Summary:
1. Use stream 0 only for combined module. Previously if combined module was not
processes ThinLTO used the stream for own output. However small changes in input,
could trigger combined module and shuffle outputs making life of llvm::LTO harder.
2. Always process combined module and write output to stream 0. Processing empty
combined module is cheap and allows llvm::LTO users to avoid implementing processing
which is already done in llvm::LTO.
Subscribers: mehdi_amini, inglorion, eraman, hiraditya
Differential Revision: https://reviews.llvm.org/D41267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320905
91177308-0d34-0410-b5e6-
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Teresa Johnson [Sat, 16 Dec 2017 01:35:36 +0000 (01:35 +0000)]
Add another missing -enable-import-metadata to test
r320895 modified a test so that it needs -enable-import-metadata which
is false by default for NDEBUG, found another place that needs this
added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320903
91177308-0d34-0410-b5e6-
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Hal Finkel [Sat, 16 Dec 2017 01:26:25 +0000 (01:26 +0000)]
[SimplifyLibCalls] Inline calls to cabs when it's safe to do so
When unsafe algerbra is allowed calls to cabs(r) can be replaced by:
sqrt(creal(r)*creal(r) + cimag(r)*cimag(r))
Patch by Paul Walker, thanks!
Differential Revision: https://reviews.llvm.org/D40069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320901
91177308-0d34-0410-b5e6-
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Hal Finkel [Sat, 16 Dec 2017 01:12:50 +0000 (01:12 +0000)]
[LV] NFC patch for moving VP*Recipe class definitions from LoopVectorize.cpp to VPlan.h
This is a small step forward to move VPlan stuff to where it should belong (i.e., VPlan.*):
1. VP*Recipe classes in LoopVectorize.cpp are moved to VPlan.h.
2. Many of VP*Recipe::print() and execute() definitions are still left in
LoopVectorize.cpp since they refer to things declared in LoopVectorize.cpp. To
be moved to VPlan.cpp at a later time.
3. InterleaveGroup class is moved from anonymous namespace to llvm namespace.
Referencing it in anonymous namespace from VPlan.h ended up in warning.
Patch by Hideki Saito, thanks!
Differential Revision: https://reviews.llvm.org/D41045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320900
91177308-0d34-0410-b5e6-
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Teresa Johnson [Sat, 16 Dec 2017 01:00:48 +0000 (01:00 +0000)]
Add -enable-import-metadata to test
r320895 modified a test so that it needs -enable-import-metadata which
is false by default for NDEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320899
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 16 Dec 2017 00:33:16 +0000 (00:33 +0000)]
[X86] Add back the assert from r320830 that was reverted in r320850
Hopefully r320864 has fixed the offending case that failed the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320898
91177308-0d34-0410-b5e6-
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Teresa Johnson [Sat, 16 Dec 2017 00:29:31 +0000 (00:29 +0000)]
Fix NDEBUG build problem in r320895
Fix incorrect placement of #endif causing NDEBUG build failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320897
91177308-0d34-0410-b5e6-
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Teresa Johnson [Sat, 16 Dec 2017 00:18:12 +0000 (00:18 +0000)]
[ThinLTO] Enable importing of aliases as copy of aliasee
Summary:
This implements a missing feature to allow importing of aliases, which
was previously disabled because alias cannot be available_externally.
We instead import an alias as a copy of its aliasee.
Some additional work was required in the IndexBitcodeWriter for the
distributed build case, to ensure that the aliasee has a value id
in the distributed index file (i.e. even when it is not being
imported directly).
This is a performance win in codes that have many aliases, e.g. C++
applications that have many constructor and destructor aliases.
Reviewers: pcc
Subscribers: mehdi_amini, inglorion, eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D40747
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320895
91177308-0d34-0410-b5e6-
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David Blaikie [Fri, 15 Dec 2017 23:52:06 +0000 (23:52 +0000)]
Fix WebAssembly backend for some LLVM API changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320893
91177308-0d34-0410-b5e6-
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Quentin Colombet [Fri, 15 Dec 2017 23:24:39 +0000 (23:24 +0000)]
[TableGen][GlobalISel] Make the different Matcher comparable
This opens refactoring opportunities in the match table now that we can
check that two predicates are the same.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320890
91177308-0d34-0410-b5e6-
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Quentin Colombet [Fri, 15 Dec 2017 23:24:36 +0000 (23:24 +0000)]
[TableGen][GlobalISel] Fix unused variable warning in release mode
Introduced in r320887.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320889
91177308-0d34-0410-b5e6-
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Paul Robinson [Fri, 15 Dec 2017 23:21:52 +0000 (23:21 +0000)]
Revert "Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header.""
This reverts commit
0afef672f63f0e4e91938656bc73424a8c058bfc.
Still failing at runtime on bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320888
91177308-0d34-0410-b5e6-
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Quentin Colombet [Fri, 15 Dec 2017 23:07:42 +0000 (23:07 +0000)]
[TableGen][GlobalISel] Have the predicate directly know which data they are dealing with
Prior to this patch, a predicate wouldn't make sense outside of its
rule. Indeed, it was only during emitting a rule that a predicate would
be made aware of the IDs of the data it is checking. Because of that,
predicates could not be moved around or compared between each other.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320887
91177308-0d34-0410-b5e6-
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Paul Robinson [Fri, 15 Dec 2017 22:57:17 +0000 (22:57 +0000)]
Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header."
Adds missing support for DW_FORM_data16.
Update of r320852, fixing the unittest to use a hand-coded struct
instead of std::array to guarantee data layout.
Differential Revision: https://reviews.llvm.org/D41090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320886
91177308-0d34-0410-b5e6-
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Matthias Braun [Fri, 15 Dec 2017 22:53:33 +0000 (22:53 +0000)]
Fix unused variable in non-assert builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320885
91177308-0d34-0410-b5e6-
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Matthias Braun [Fri, 15 Dec 2017 22:22:58 +0000 (22:22 +0000)]
MachineFunction: Return reference from getFunction(); NFC
The Function can never be nullptr so we can return a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320884
91177308-0d34-0410-b5e6-
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Matthias Braun [Fri, 15 Dec 2017 22:22:46 +0000 (22:22 +0000)]
MachineFunction: Slight refactoring; NFC
Slight cleanup/refactor in preparation for upcoming commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320882
91177308-0d34-0410-b5e6-
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Matthias Braun [Fri, 15 Dec 2017 22:22:42 +0000 (22:22 +0000)]
MachineModuleInfo: Remove unused function; NFC
Remove the unused setModule() function; it would be dangerous if someone
actually used it as it wouldn't reset/recompute various other module
related data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320881
91177308-0d34-0410-b5e6-
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Galina Kistanova [Fri, 15 Dec 2017 22:15:29 +0000 (22:15 +0000)]
Fixed the gcc 'enumeral and non-enumeral type in conditional expression [-Werror=extra]' warning introduced by r320750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320868
91177308-0d34-0410-b5e6-
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Krzysztof Parzyszek [Fri, 15 Dec 2017 21:34:05 +0000 (21:34 +0000)]
[Hexagon] Remove recursion in visitUsesOf, replace with use queue
This is primarily to reduce stack usage, but ordering the use queue
according to the position in the code (earlier instructions visited
before later ones) reduces the number of unnecessary bottoms due to
visiting instructions out of order, e.g.
%reg1 = copy %reg0
%reg2 = copy %reg0
%reg3 = and %reg1, %reg2
Here, reg3 should be known to be same as reg0-2, but if reg3 is
evaluated after reg1 is updated, but before reg2 is updated, the two
inputs to the and will appear different, causing reg3 to become
bottom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320866
91177308-0d34-0410-b5e6-
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Krzysztof Parzyszek [Fri, 15 Dec 2017 21:23:12 +0000 (21:23 +0000)]
[Hexagon] Handle concat_vectors of all allowed HVX types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320865
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 15 Dec 2017 21:18:06 +0000 (21:18 +0000)]
[X86] Use AND32ri8 instead of AND64ri8 in Asan code in EmitCallAsanReport for 32-bit mode.
This seemed to work due to a quirk in the X86 MC encoder that didn't emit a REX byte that the AND64ri8 implies when in 32-bit mode. This made the encoding the same as AND32ri8. I tried to add an assert to catch the dropped REX prefix that caught this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320864
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 15 Dec 2017 21:18:05 +0000 (21:18 +0000)]
[X86] In LowerVectorCTPOP use ISD::ZERO_EXTEND/ISD::TRUNCATE instead of the target specific nodes.
The target independent nodes will get legalized to the target specific nodes by their own legalization process. Someday I'd like to stop using a target specific for zero extends and truncates of legal types so the less places we reference the target specific opcode the better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320863
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 15 Dec 2017 20:57:18 +0000 (20:57 +0000)]
[X86] Remove unnecessary TODO.
When I wrote it I thought we were missing a potential optimization for KNL. But investigating further shows that for KNL we still do the optimal thing by widening to v4f32 and then using special isel patterns to widen again to zmm a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320862
91177308-0d34-0410-b5e6-
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Vitaly Buka [Fri, 15 Dec 2017 20:50:25 +0000 (20:50 +0000)]
[LTO] Remove unused RegularLTOState::HasModule
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320859
91177308-0d34-0410-b5e6-
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Jun Bum Lim [Fri, 15 Dec 2017 20:33:24 +0000 (20:33 +0000)]
Re-commit : [LICM] Allow sinking when foldable in loop
This recommits r320823 reverted due to the test failure in sink-foldable.ll and
an unused variable. Added "REQUIRES: aarch64-registered-target" in the test
and removed unused variable.
Original commit message:
Continue trying to sink an instruction if its users in the loop is foldable.
This will allow the instruction to be folded in the loop by decoupling it from
the user outside of the loop.
Reviewers: hfinkel, majnemer, davidxl, efriedma, danielcdh, bmakam, mcrosier
Reviewed By: hfinkel
Subscribers: javed.absar, bmakam, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D37076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320858
91177308-0d34-0410-b5e6-
96231b3b80d8
Paul Robinson [Fri, 15 Dec 2017 20:29:25 +0000 (20:29 +0000)]
Revert "[DWARFv5] Dump an MD5 checksum in the line-table header."
Unit test fails on some bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320857
91177308-0d34-0410-b5e6-
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Jake Ehrlich [Fri, 15 Dec 2017 20:17:55 +0000 (20:17 +0000)]
[llvm-objcopy] Reformat everything using clang-format -i
Overtime some non-clang formatted code has creeped into llvm-objcopy. This
patch fixes all of that.
Differential Revision: https://reviews.llvm.org/D41262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320856
91177308-0d34-0410-b5e6-
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Krzysztof Parzyszek [Fri, 15 Dec 2017 20:13:57 +0000 (20:13 +0000)]
[Hexagon] Fix operand-swapping PatFrag for atomic stores
PatFrag now has the atomicity information stored as bit fields. They
need to be copied to the new PatFrag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320855
91177308-0d34-0410-b5e6-
96231b3b80d8
Paul Robinson [Fri, 15 Dec 2017 19:52:34 +0000 (19:52 +0000)]
[DWARFv5] Dump an MD5 checksum in the line-table header.
Adds missing support for DW_FORM_data16.
Differential Revision: https://reviews.llvm.org/D41090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320852
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 15 Dec 2017 19:38:14 +0000 (19:38 +0000)]
[X86] Remove assert in X86MCCodeEmitter.cpp that was added in r320830.
It seems to be failing real code which is concerning, but we were silently getting away with it. I'll investigate further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320850
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 15 Dec 2017 19:35:22 +0000 (19:35 +0000)]
[SelectionDAG][X86] Fix insert_vector_elt lowering for v32i1/v64i1 with non-constant index
Summary:
Currently we don't handle v32i1/v64i1 insert_vector_elt correctly as we fail to look at the number of elements closely and assume it can only be v16i1 or v8i1.
We also can't type legalize v64i1 insert_vector_elt correctly on KNL due to the type not being byte addressable as required by the legalizing through memory accesses path requires.
For the first issue, the patch now tries to pick a 512-bit register with the correct number of elements and promotes to that.
For the second issue, we now extend the vector to a byte addressable type, do the stores to memory, load the two halves, and then truncate the halves back to the original type. Technically since we changed the type, we may not need two loads, but actually checking that is more work and for the v64i1 case we do need them.
Reviewers: RKSimon, delena, spatel, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320849
91177308-0d34-0410-b5e6-
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Sean Fertile [Fri, 15 Dec 2017 19:29:12 +0000 (19:29 +0000)]
[Memcpy Loop Lowering] Insert loop BB inbetween the split BB.
The original memcpy expansion inserted the loop basic block inbetween
the 2 new basic blocks created by splitting the original block the memcpy
call was in. This commit makes the new memcpy expansion do the same to keep the
layout of the IR matching between the old and new implementations.
Differential Review: https://reviews.llvm.org/D41197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320848
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 15 Dec 2017 19:01:51 +0000 (19:01 +0000)]
[X86] Add 'Requires<[In64BitMode]>' to a bunch of instructions that only have memory and immediate operands.
The asm parser wasn't preventing these from being accepted in 32-bit mode. Instructions that use a GR64 register are protected by the parser rejecting the register in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320846
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 15 Dec 2017 19:01:50 +0000 (19:01 +0000)]
[X86] Change BNDLDX to use anymem instead of i64mem for itsmemory operand.
This instruction doesn't access memory. It juse use a similar looking memory encoding. Don't require Intel syntax to put "qword ptr" in front of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320845
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Craig Topper [Fri, 15 Dec 2017 19:01:49 +0000 (19:01 +0000)]
[X86] Remove the 'Requires' In64BitMode/Not64BitMode from the LWP instructions.
These aren't doing anything due to a top level "let Predicates =". I think the GR32/GR64 register class protects these anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320844
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Craig Topper [Fri, 15 Dec 2017 19:01:48 +0000 (19:01 +0000)]
[X86] Remove the 'Requires<[In64BitMode]>' from SHSTK instructions.
This has no effect due to a top level "let Predicates =" around the instructions. But its also not required because the GR64 usage in the instruction guarantees it can never match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320843
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Sanjay Patel [Fri, 15 Dec 2017 18:54:29 +0000 (18:54 +0000)]
[TargetLibraryInfo] fix documentation comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320842
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Sanjay Patel [Fri, 15 Dec 2017 18:34:45 +0000 (18:34 +0000)]
[CodeGen] fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320840
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