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Amos Kong [Tue, 16 Jul 2013 11:52:14 +0000 (19:52 +0800)]
qmp: update send-key document
commit
9f328977 changes qmp_send_key() to accept key codes in hex,
but the document wasn't updated. The items of keys list is union
now, not enum.
Signed-off-by: Amos Kong <akong@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Luiz Capitulino [Thu, 11 Jul 2013 18:26:56 +0000 (14:26 -0400)]
qapi: qapi-commands: fix possible leaks on visitor dealloc
In qmp-marshal.c the dealloc visitor calls use the same errp
pointer of the input visitor calls. This means that if any of
the input visitor calls fails, then the dealloc visitor will
return early, before freeing the object's memory.
Here's an example, consider this code:
int qmp_marshal_input_block_passwd(Monitor *mon, const QDict *qdict, QObject **ret)
{
[...]
char * device = NULL;
char * password = NULL;
mi = qmp_input_visitor_new_strict(QOBJECT(args));
v = qmp_input_get_visitor(mi);
visit_type_str(v, &device, "device", errp);
visit_type_str(v, &password, "password", errp);
qmp_input_visitor_cleanup(mi);
if (error_is_set(errp)) {
goto out;
}
qmp_block_passwd(device, password, errp);
out:
md = qapi_dealloc_visitor_new();
v = qapi_dealloc_get_visitor(md);
visit_type_str(v, &device, "device", errp);
visit_type_str(v, &password, "password", errp);
qapi_dealloc_visitor_cleanup(md);
[...]
return 0;
}
Consider errp != NULL when the out label is reached, we're going
to leak device and password.
This patch fixes this by always passing errp=NULL for dealloc
visitors, meaning that we always try to free them regardless of
any previous failure. The above example would then be:
out:
md = qapi_dealloc_visitor_new();
v = qapi_dealloc_get_visitor(md);
visit_type_str(v, &device, "device", NULL);
visit_type_str(v, &password, "password", NULL);
qapi_dealloc_visitor_cleanup(md);
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Anthony Liguori [Mon, 15 Jul 2013 19:49:15 +0000 (14:49 -0500)]
Merge remote-tracking branch 'quintela/migration.next' into staging
# By Chegu Vinod
# Via Juan Quintela
* quintela/migration.next:
Force auto-convegence of live migration
Add 'auto-converge' migration capability
Introduce async_run_on_cpu()
Message-id:
1373664508-5404-1-git-send-email-quintela@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Anthony Liguori [Mon, 15 Jul 2013 19:02:41 +0000 (14:02 -0500)]
Merge remote-tracking branch 'cohuck/virtio-ccw-upstr' into staging
# By Dominik Dingel
# Via Cornelia Huck
* cohuck/virtio-ccw-upstr:
virtio-ccw: Enable x-data-plane for virtio-ccw-blk
Message-id:
1373903207-27085-1-git-send-email-cornelia.huck@de.ibm.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Anthony Liguori [Mon, 15 Jul 2013 19:02:32 +0000 (14:02 -0500)]
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-
20130715-1' into staging
target-arm queue
# gpg: Signature made Mon 15 Jul 2013 11:15:13 AM CDT using RSA key ID
14360CDE
# gpg: Can't check signature: public key not found
# By Mans Rullgard (3) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-
20130715-1:
target-arm: Avoid g_hash_table_get_keys()
target-arm: avoid undefined behaviour when writing TTBCR
target-arm/helper.c: Allow const opaques in arm CP
target-arm/helper.c: Implement MIDR aliases
target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup
target-arm: explicitly decode SEVL instruction
target-arm: implement LDA/STL instructions
target-arm: add feature flag for ARMv8
Message-id:
1373905022-27735-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Anthony Liguori [Mon, 15 Jul 2013 19:02:12 +0000 (14:02 -0500)]
Merge remote-tracking branch 'pmaydell/tags/pull-arm-devs-
20130715' into staging
arm-devs queue
# gpg: Signature made Mon 15 Jul 2013 10:53:44 AM CDT using RSA key ID
14360CDE
# gpg: Can't check signature: public key not found
# By Peter Maydell (4) and others
# Via Peter Maydell
* pmaydell/tags/pull-arm-devs-
20130715:
ARM/highbank: add support for Calxeda ECX-2000 / Midway
ARM/highbank: prepare for adding similar machines
hw/arm/vexpress: Add alias for flash at address 0 on A15 board
hw/dma/omap_dma: Fix bugs with DMA requests above 32
sd/pl181.c: Avoid undefined shift behaviour in RWORD macro
hw/cpu/a15mpcore: Correct default value for num-irq
char/cadence_uart: Fix reset for unattached instances
Message-id:
1373904095-27592-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Anthony Liguori [Mon, 15 Jul 2013 19:00:57 +0000 (14:00 -0500)]
Merge remote-tracking branch 'rth/axp-next' into staging
# By Richard Henderson
# Via Richard Henderson
* rth/axp-next:
hw/alpha: Use SRM epoch
hw/alpha: Drop latch_tmp hack
exec: Support 64-bit operations in address_space_rw
hw/alpha: Don't machine check on missing pci i/o
hw/alpha: Don't use get_system_io
Message-id:
1373840171-25556-1-git-send-email-rth@twiddle.net
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Anthony Liguori [Mon, 15 Jul 2013 19:00:32 +0000 (14:00 -0500)]
Merge remote-tracking branch 'kwolf/for-anthony' into staging
# By Kevin Wolf (6) and Stefan Hajnoczi (2)
# Via Kevin Wolf
* kwolf/for-anthony:
ahci: Fix FLUSH command
migration: Fail migration on bdrv_flush_all() error
cpus: Add return value for vm_stop()
block: Add return value for bdrv_flush_all()
qemu-iotests: Update 051 reference output
block: Don't parse protocol from file.filename
block: add drive_backup HMP command
blockdev: add sync mode to drive-backup QMP command
Message-id:
1373887000-4488-1-git-send-email-kwolf@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Peter Maydell [Mon, 1 Jul 2013 11:40:19 +0000 (12:40 +0100)]
target-arm: Avoid g_hash_table_get_keys()
g_hash_table_get_keys() was only introduced in glib 2.14, and we're
still targeting a minimum version of 2.12. Rewrite the offending
code (introduced in commit
721fae1) to use g_hash_table_foreach()
to build the list of keys.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
1372678819-8633-1-git-send-email-peter.maydell@linaro.org
Peter Maydell [Thu, 27 Jun 2013 15:38:47 +0000 (16:38 +0100)]
target-arm: avoid undefined behaviour when writing TTBCR
LPAE CPUs have more potentially valid bits in the TTBCR, and so the
simple masking out of invalid bits is no longer sufficient to obtain
the base address width field of the register, which is what we use to
precalculate c2_mask and c2_base_mask. Explicitly extract the
relevant register field rather than simply shifting by the register
value.
This bug would have had no ill effects in practice, since if the
EAE bit (TTBCR bit 31) is set then we don't use the precalculated
masks, and if EAE is zero then bits 30..3 are all UNK/SBZP, so
well-behaved guests won't set them. However the shift is undefined
behaviour, so we should avoid it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1372347527-4428-1-git-send-email-peter.maydell@linaro.org
Peter Crosthwaite [Wed, 10 Jul 2013 04:22:59 +0000 (14:22 +1000)]
target-arm/helper.c: Allow const opaques in arm CP
Allow for defining const opaque data in ARM CP register definitions by
setting .opaque = foo. If non null opaque is passed into
define_one_arm_cp_reg_with_opaque then that opaque will take
precedence, otherwise if null opaque is passed, the original opaque
data will be used.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
cf0a3ac3438d97464240db9f5f4ef1585cbc1d77.
1373429432.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 10 Jul 2013 04:22:21 +0000 (14:22 +1000)]
target-arm/helper.c: Implement MIDR aliases
Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space default
to aliasing the MIDR register. Set all registers in the space to access
MIDR by default.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
6127846712b7ad2727354a4f5e1d809451f1e859.
1373429432.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 10 Jul 2013 04:21:42 +0000 (14:21 +1000)]
target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup
The if block detecting OMAP/StrongARM modifies the id_cp_reginfo
.access fields in place. So there is no need to replicate the call
to define_arm_cp_reg(). Dropped, and let the OMAP case fall through
to the normal behaviour after the in-place modification.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
72aae9b8ebbc9a76d2b06faf8666ef8a4b34b92a.
1373429432.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Mans Rullgard [Mon, 15 Jul 2013 13:35:25 +0000 (14:35 +0100)]
target-arm: explicitly decode SEVL instruction
The ARMv8 SEVL instruction is in the architectural hint space already
emulated as nop. This makes the decoding of SEVL explicit for clarity.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Message-id:
1370606786-5650-3-git-send-email-mans@mansr.com
[PMM: added 'SEVL' to the TODO comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Mans Rullgard [Mon, 15 Jul 2013 13:35:25 +0000 (14:35 +0100)]
target-arm: implement LDA/STL instructions
This adds support for the ARMv8 load acquire/store release instructions.
Since qemu does nothing special for memory barriers, these can be
emulated like their non-acquire/release counterparts.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Dominik Dingel [Thu, 11 Jul 2013 11:22:19 +0000 (13:22 +0200)]
virtio-ccw: Enable x-data-plane for virtio-ccw-blk
Add property x-data-plane to virtio-ccw-blk devices.
Signed-off-by: Dominik Dingel <dingel@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Andre Przywara [Fri, 5 Jul 2013 12:21:37 +0000 (14:21 +0200)]
ARM/highbank: add support for Calxeda ECX-2000 / Midway
The Calxeda ECX-2000 chip (aka. Midway) is model-wise quite similar
to the Highbank. The most prominent difference is the Cortex-A15 CPU
core in it, together with the associated core peripherals.
Add a new ARM machine type called "midway".
Move the L2 cache controller device into the Highbank specific part,
since Midway does not have (and need) it.
Signed-off-by: Andre Przywara <andre.przywara@calxeda.com>
Message-id:
1373026897-12085-3-git-send-email-andre.przywara@calxeda.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Andre Przywara [Fri, 5 Jul 2013 12:21:36 +0000 (14:21 +0200)]
ARM/highbank: prepare for adding similar machines
To allow the modelling of machines similar to Calxeda Highbank,
introduce a parameter to the init function and call it from a
wrapper. This allows to tweak the definition for individual machines
later on.
Signed-off-by: Andre Przywara <andre.przywara@calxeda.com>
Message-id:
1373026897-12085-2-git-send-email-andre.przywara@calxeda.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 9 Jul 2013 12:49:40 +0000 (13:49 +0100)]
hw/arm/vexpress: Add alias for flash at address 0 on A15 board
The A15 Versatile Express board can remap a variety of things at address
0. We don't currently emulate the Serial Configuration Controller which
is how the guest can control this remapping, but we can provide the
initial default mapping of the first flash device into this space.
In particular this allows QEMU to boot flash images such as UEFI which
expect to include an exception vector table.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Grant Likely <grant.likely@linaro.org>
Message-id:
1373374180-19884-1-git-send-email-peter.maydell@linaro.org
Peter Maydell [Fri, 28 Jun 2013 12:51:59 +0000 (13:51 +0100)]
hw/dma/omap_dma: Fix bugs with DMA requests above 32
The drqbmp field of struct soc_dma_s is a uint64_t; however several
places in the code attempt to set bits in it using "(1 << drq)",
which will fail if drq is large enough that the 1 bit gets shifted
off the top of a 32 bit integer. Change these to "(1ULL << drq)" so
that the promotion to 64 bit happens before the shift rather than
afterwards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1372423919-5669-1-git-send-email-peter.maydell@linaro.org
Peter Maydell [Thu, 27 Jun 2013 14:03:51 +0000 (15:03 +0100)]
sd/pl181.c: Avoid undefined shift behaviour in RWORD macro
Add a cast to avoid potentially shifting into the sign bit of
a signed value, which is undefined behaviour in C.
(Detected with clang's -fsanitize=undefined.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1372341831-4264-1-git-send-email-peter.maydell@linaro.org
Peter Maydell [Fri, 5 Jul 2013 13:54:41 +0000 (14:54 +0100)]
hw/cpu/a15mpcore: Correct default value for num-irq
The a15mpcore device claims that its default value for num-irq
is the number of interrupts used by the A15MP in the vexpress-a15
board. However that chip has 128 external interrupts, not 64.
Since there is only one A15 based model in QEMU currently, we
can fix this by simply changing the default value.
This error was causing recent (3.10) Linux kernels to print
warnings/backtraces when the number of interrupts reported
by the GIC was smaller than an interrupt number they wanted
to use.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1373032481-15280-1-git-send-email-peter.maydell@linaro.org
Mans Rullgard [Mon, 15 Jul 2013 13:35:25 +0000 (14:35 +0100)]
target-arm: add feature flag for ARMv8
Signed-off-by: Mans Rullgard <mans@mansr.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Mon, 15 Jul 2013 11:28:07 +0000 (12:28 +0100)]
char/cadence_uart: Fix reset for unattached instances
commit
1db8b5efe0c2b5000e50691eea61264a615f43de introduced an issue
where QEMU would segfault if you have an unattached Cadence UART.
Fix by guarding the flush-on-reset logic on there being a qemu_chr
attachment.
Reported-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Message-id:
9009578ee10a50d994b2e10aa2840d73765f5968.
1370577272.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Kevin Wolf [Mon, 15 Jul 2013 09:25:55 +0000 (11:25 +0200)]
ahci: Fix FLUSH command
AHCI couldn't cope with asynchronous commands that aren't doing DMA, it
simply wouldn't complete them. Due to the bug fixed in commit
f68ec837,
FLUSH commands would seem to have completed immediately even if they
were still running on the host. After the commit, they would simply hang
and never unset the BSY bit, rendering AHCI unusable on any OS sending
flushes.
This patch adds another callback for the completion of asynchronous
commands. This is what AHCI really wants to use for its command
completion logic rather than an DMA completion callback.
Cc: qemu-stable@nongnu.org
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Kevin Wolf [Fri, 5 Jul 2013 11:54:55 +0000 (13:54 +0200)]
migration: Fail migration on bdrv_flush_all() error
If bdrv_flush_all() returns an error, there is an inconsistency in the
view of an image file between the source and the destination host.
Completing the migration would lead to corruption. Better abort
migration in this case.
To reproduce this case, try the following (ensures that there is
something to flush, and then fails that flush):
$ qemu-img create -f qcow2 test.qcow2 1G
$ cat blkdebug.cfg
[inject-error]
event = "flush_to_os"
errno = "5"
$ qemu-system-x86_64 -hda blkdebug:blkdebug.cfg:test.qcow2 -monitor stdio
(qemu) qemu-io ide0-hd0 "write 0 4k"
(qemu) migrate ...
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Kevin Wolf [Fri, 5 Jul 2013 11:49:54 +0000 (13:49 +0200)]
cpus: Add return value for vm_stop()
If flushing the block devices fails, return an error. The VM is stopped
anyway.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Kevin Wolf [Fri, 5 Jul 2013 11:48:01 +0000 (13:48 +0200)]
block: Add return value for bdrv_flush_all()
bdrv_flush() can fail, and bdrv_flush_all() should return an error as
well if this happens for a block device. It returns the first error
return now, but still at least tries to flush the remaining devices even
in error cases.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Kevin Wolf [Wed, 10 Jul 2013 15:30:26 +0000 (17:30 +0200)]
qemu-iotests: Update 051 reference output
This has been broken by commit
bd5c51ee.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Kevin Wolf [Wed, 10 Jul 2013 13:47:39 +0000 (15:47 +0200)]
block: Don't parse protocol from file.filename
One of the major reasons for doing something new for -blockdev and
blockdev-add was that the old block layer code parses filenames instead
of just taking them literally. So we should really leave it untouched
when it's passing using the new interfaces (like -drive
file.filename=...).
This allows opening relative file names that contain a colon.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Stefan Hajnoczi [Wed, 26 Jun 2013 12:11:58 +0000 (14:11 +0200)]
block: add drive_backup HMP command
Make "drive_backup" available on the HMP monitor:
drive_backup [-n] [-f] device target [format]
The -n flag requests QEMU to reuse the image found in new-image-file,
instead of recreating it from scratch.
The -f flag requests QEMU to copy the whole disk, so that the result
does not need a backing file. Note that this flag *must* currently be
passed since the other sync modes ('none' and 'top') have not been
implemented yet. Requiring it ensures that "drive_backup" behaves like
"drive_mirror".
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Stefan Hajnoczi [Wed, 26 Jun 2013 12:11:57 +0000 (14:11 +0200)]
blockdev: add sync mode to drive-backup QMP command
The drive-backup command is similar to the drive-mirror command, except
no guest data written after the command executes gets copied. Add a
sync mode argument which determines whether the entire disk is copied,
just allocated clusters, or only clusters being written to by the guest.
Currently only sync mode 'full' is supported - it copies the entire disk.
For read-only point-in-time snapshots we may only need sync mode 'none'
since the target can be a qcow2 file using the guest's disk as its
backing file (no need to copy the entire disk). Finally, sync mode
'top' is useful if we wish to preserve the backing chain.
Note that this patch just adds the sync mode argument to drive-backup.
It does not implement sync modes 'top' or 'none'. This patch is
necessary so we can add a drive-backup HMP command that behaves like the
existing drive-mirror HMP command and takes a sync mode.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Richard Henderson [Sun, 14 Jul 2013 00:23:37 +0000 (17:23 -0700)]
hw/alpha: Use SRM epoch
The 1980 epoch is used by the ARC PALcode for NT. But we're emulating
a system using the SRM PALcode. Using the proper epoch results in less
confusion in the guest userland.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 8 Jul 2013 21:57:39 +0000 (14:57 -0700)]
hw/alpha: Drop latch_tmp hack
The memory and i/o core now support passing 64-bit accesses along
from the guest, so we no longer need to emulate them.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 8 Jul 2013 21:55:59 +0000 (14:55 -0700)]
exec: Support 64-bit operations in address_space_rw
Honor the implementation maximum access size, and at least check
the minimum access size.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 8 Jul 2013 22:46:37 +0000 (15:46 -0700)]
hw/alpha: Don't machine check on missing pci i/o
Not really correct, but we don't implement all of the random devices
that the kernel looks for. This is good enough to keep us booting.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Richard Henderson [Mon, 8 Jul 2013 20:55:30 +0000 (13:55 -0700)]
hw/alpha: Don't use get_system_io
Advancements in the ioport subsystem mean that we need no longer
thunk memory-mapped i/o through the system-io address space.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Anthony Liguori [Fri, 12 Jul 2013 19:37:47 +0000 (14:37 -0500)]
ioport: remove LITTLE_ENDIAN mark for portio
Setting it to LE forces a byte swap when host != guest endian but
this makes no sense at all.
Herve made the suggestion upon observing that word writes/reads
were broken into byte writes/reads in such a way as to assume
devices are interpret registers as LE.
However, even if this were a problem, marking the region as LE is
not useful because what's essentially happening here is that LE is
open coded. So by marking it LE in MemoryRegionOps, we're doing a
superflous swap.
Now, the portio code is suspicious to begin with. The dispatch
layer really has no purpose in splitting I/O requests in the first
place...
Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Alex Graf <agraf@suse.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Chegu Vinod [Mon, 24 Jun 2013 09:47:39 +0000 (03:47 -0600)]
Force auto-convegence of live migration
If a user chooses to turn on the auto-converge migration capability
these changes detect the lack of convergence and throttle down the
guest. i.e. force the VCPUs out of the guest for some duration
and let the migration thread catchup and help converge.
Verified the convergence using the following :
- Java Warehouse workload running on a 20VCPU/256G guest(~80% busy)
- OLTP like workload running on a 80VCPU/512G guest (~80% busy)
Sample results with Java warehouse workload : (migrate speed set to 20Gb and
migrate downtime set to 4seconds).
(qemu) info migrate
capabilities: xbzrle: off auto-converge: off <----
Migration status: active
total time:
1487503 milliseconds
expected downtime: 519 milliseconds
transferred ram:
383749347 kbytes
remaining ram:
2753372 kbytes
total ram:
268444224 kbytes
duplicate:
65461532 pages
skipped:
64901568 pages
normal:
95750218 pages
normal bytes:
383000872 kbytes
dirty pages rate: 67551 pages
---
(qemu) info migrate
capabilities: xbzrle: off auto-converge: on <----
Migration status: completed
total time: 241161 milliseconds
downtime: 6373 milliseconds
transferred ram:
28235307 kbytes
remaining ram: 0 kbytes
total ram:
268444224 kbytes
duplicate:
64946416 pages
skipped:
64903523 pages
normal:
7044971 pages
normal bytes:
28179884 kbytes
Signed-off-by: Chegu Vinod <chegu_vinod@hp.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Chegu Vinod [Mon, 24 Jun 2013 09:49:42 +0000 (03:49 -0600)]
Add 'auto-converge' migration capability
The auto-converge migration capability allows the user to specify if they
choose live migration seqeunce to automatically detect and force convergence.
Signed-off-by: Chegu Vinod <chegu_vinod@hp.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Chegu Vinod [Mon, 24 Jun 2013 09:49:41 +0000 (03:49 -0600)]
Introduce async_run_on_cpu()
Introduce an asynchronous version of run_on_cpu() i.e. the caller
doesn't have to block till the call back routine finishes execution
on the target vcpu.
Signed-off-by: Chegu Vinod <chegu_vinod@hp.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Anthony Liguori [Fri, 12 Jul 2013 12:58:31 +0000 (07:58 -0500)]
Merge remote-tracking branch 'agraf/ppc-for-upstream' into staging
# By Alexander Graf (16) and others
# Via Alexander Graf
* agraf/ppc-for-upstream: (22 commits)
PPC: dbdma: Support more multi-issue DMA requests
PPC: Add timer handler for newworld mac-io
PPC: dbdma: Support unaligned DMA access
PPC: dbdma: Wait for DMA until we have data
PPC: dbdma: Move processing to io
PPC: dbdma: macio: Add DMA callback
PPC: dbdma: Move static bh variable to device struct
PPC: dbdma: Introduce kick function
PPC: dbdma: Move defines into header file
PPC: dbdma: Allow new commands in RUN state
PPC: dbdma: Fix debug print
PPC: Mac: Add debug prints in macio and dbdma code
PPC: dbdma: Replace tabs with spaces
PPC: Macio: Replace tabs with spaces
PPC: g3beige: Move secondary IDE bus to mac-io
PPC: Mac: Fix guest exported tbfreq values
target-ppc: Add POWER8 v1.0 CPU model
pseries: move interrupt controllers to hw/intc/
spapr: Respect -bios command line option for SLOF
spapr: Use named enum for function remove_hpte
...
Message-id:
1373562085-29728-1-git-send-email-agraf@suse.de
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Alexander Graf [Sun, 30 Jun 2013 13:29:13 +0000 (15:29 +0200)]
PPC: dbdma: Support more multi-issue DMA requests
A DMA request can happen for data that hasn't been completely been
provided by the IDE core yet. For example
- DBDMA request for 0x1000 bytes
- IDE request for 1 sector
- DBDMA wants to read 0x1000 bytes (8 sectors) from bdrv
- breakage
Instead, we should truncate our bdrv request to the maximum number
of sectors we're allowed to read at that given time. Once that transfer
is through, we will fall into our recently introduced waiting logic.
- DBDMA requests for 0x1000 bytes
- IDE request for 1 sector
- DBDMA wants to read MIN(0x1000, 1 * 512) bytes
- DBDMA finishes reading, indicates to IDE core that transfer is complete
- IDE request for 7 sectors
- DBDMA finishes the DMA
Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sun, 30 Jun 2013 03:15:14 +0000 (05:15 +0200)]
PPC: Add timer handler for newworld mac-io
Mac OS X accesses fancy timer registers inside of the mac-io on bootup.
These really should be ticking at the mac-io bus frequency, but I don't
see anyone upset when we just make them as fast as we want to.
With this patch on top of my previous patch queue and latest OpenBIOS
I am able to boot Mac OS X 10.4 with -M mac99.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Fri, 28 Jun 2013 11:30:01 +0000 (13:30 +0200)]
PPC: dbdma: Support unaligned DMA access
The DBDMA engine really just reads bytes from a producing device (IDE
in our case) and shoves these bytes into memory. It doesn't care whether
any alignment takes place or not.
Our code today however assumes that block accesses always happen on
sector (512 byte) boundaries. This is a fair assumption for most cases.
However, Mac OS X really likes to do unaligned, incomplete accesses
that it finishes with the next DMA request.
So we need to read / write the unaligned bits independent of the actual
asynchronous request, because that one can only handle 512-byte-aligned
data. We also need to cache these unaligned sectors until the next DMA
request, at which point the data might be successfully flushed from the
pipe.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sun, 30 Jun 2013 00:54:35 +0000 (02:54 +0200)]
PPC: dbdma: Wait for DMA until we have data
We should only start processing DMA requests when we have data to process.
Hold off working through the DMA shuffling until the IDE core told us that
it's ready.
This is required because the guest can program the DMA engine or the IDE
transfer first. Both are legal.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sun, 30 Jun 2013 00:47:20 +0000 (02:47 +0200)]
PPC: dbdma: Move processing to io
Soon we will introduce intermediate processing pauses which will
allow the bottom half to restart a DMA request that couldn't be
fulfilled yet.
For that to work, move the processing variable into the io struct
which is what DMA providers work with.
While touching it, also change it into a bool
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sun, 30 Jun 2013 00:36:14 +0000 (02:36 +0200)]
PPC: dbdma: macio: Add DMA callback
We need to know when the IDE core starts a DMA transfer. Add a notifier
function so we have the chance to start transmitting data.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sun, 30 Jun 2013 00:22:41 +0000 (02:22 +0200)]
PPC: dbdma: Move static bh variable to device struct
The DBDMA controller has a bottom half to asynchronously process DMA
request queues.
This bh was stored as a gross static variable. Move it into the device
struct instead.
While at it, move all users of it to the new generic kick function.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sun, 30 Jun 2013 00:18:54 +0000 (02:18 +0200)]
PPC: dbdma: Introduce kick function
The DBDMA engine really is running all the time, waiting for input. However
we don't want to waste cycles constantly polling.
So introduce a kick function that data providers can call to notify the
DBDMA controller of new input.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sun, 30 Jun 2013 00:06:35 +0000 (02:06 +0200)]
PPC: dbdma: Move defines into header file
We usually keep struct and constant definitions in header files. Move
them there to stay consistent and to make access to fields easier.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 29 Jun 2013 23:53:51 +0000 (01:53 +0200)]
PPC: dbdma: Allow new commands in RUN state
The DBDMA controller can not change its command stream while it's
actively streaming data, true. But the fact that it's in RUN state
doesn't actually indicate anything. It could just as well be in
WAIT while in RUN. And then it's legal to change commands.
This fixes a real world issue I've encountered with Mac OS X.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 29 Jun 2013 23:53:05 +0000 (01:53 +0200)]
PPC: dbdma: Fix debug print
There was a debug print that didn't compile for me because the format
and the arguments weren't in sync. Fix it up.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 29 Jun 2013 23:23:45 +0000 (01:23 +0200)]
PPC: Mac: Add debug prints in macio and dbdma code
The macio code is basically undebuggable as it stands today, with no
debug prints anywhere whatsoever. DBDMA was better, but I needed a
few more to create reasonable logs that tell me where breakage is.
Add a DPRINTF macro in the macio source file and add a bunch of debug
prints that are all disabled by default of course.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 29 Jun 2013 23:45:22 +0000 (01:45 +0200)]
PPC: dbdma: Replace tabs with spaces
s/^I/ /g on the file with a few manual tweaks to align things.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 29 Jun 2013 23:43:17 +0000 (01:43 +0200)]
PPC: Macio: Replace tabs with spaces
s/^I/ /g on the file.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Mon, 24 Jun 2013 19:40:50 +0000 (21:40 +0200)]
PPC: g3beige: Move secondary IDE bus to mac-io
On a real G3 Beige the secondary IDE bus lives on the mac-io chip, not
on some random PCI device. Move it there to become more compatible.
While at it, also clean up the IDE channel connection logic.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 29 Jun 2013 15:34:58 +0000 (17:34 +0200)]
PPC: Mac: Fix guest exported tbfreq values
We can tell the guest the frequency of its time base through fwcfg.
However, we tell it a different value from the speed tb actually runs
at. Let's fix it and make the tbfreq initialization and the fwcfg exposure
use the same values.
Signed-off-by: Alexander Graf <agraf@suse.de>
Prerna Saxena [Thu, 4 Jul 2013 06:42:32 +0000 (12:12 +0530)]
target-ppc: Add POWER8 v1.0 CPU model
This patch adds CPU PVR definition for POWER8,
and enables QEMU to launch guests on POWER8 hardware.
Signed-off-by: Prerna Saxena <prerna@linux.vnet.ibm.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Andreas Farber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexey Kardashevskiy [Sat, 6 Jul 2013 13:53:58 +0000 (23:53 +1000)]
pseries: move interrupt controllers to hw/intc/
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Andreas Färber [Wed, 3 Jul 2013 19:26:50 +0000 (21:26 +0200)]
spapr: Respect -bios command line option for SLOF
Allow the user to override the firmware file name rather than always
using "slof.bin".
Reported-by: Dinar Valeev <k0da@opensuse.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Stefan Weil [Mon, 24 Jun 2013 17:48:47 +0000 (19:48 +0200)]
spapr: Use named enum for function remove_hpte
The function returned a target_ulong which was made from unnamed enum
values. The target_ulong was then assigned to an int variable which
was used in a switch statement.
Using a named enum in both cases makes reviews easier.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Stefan Weil [Sat, 29 Jun 2013 13:47:26 +0000 (15:47 +0200)]
spapr: Fix compiler warnings for some versions of gcc
i686-w64-mingw32-gcc (GCC) 4.6.3 from Debian wheezy reports these warnings:
hw/ppc/spapr_hcall.c:188:1: warning:
control reaches end of non-void function [-Wreturn-type]
hw/ppc/spapr_pci.c:454:1: warning:
control reaches end of non-void function [-Wreturn-type]
Both warnings are fixed by using g_assert_not_reached instead of assert.
A second line with assert(0) in spapr_pci.c which did not raise a compiler
warning was modified, too, because g_assert_not_reached documents the
purpose of that statement and is not removed in release builds.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Julio Guerra [Mon, 24 Jun 2013 21:15:54 +0000 (23:15 +0200)]
e600 core for MPC86xx processors
MPC86xx processors are based on the e600 core, which is not the case
in qemu where it is based on the 7400 processor.
This patch creates the e600 core and instantiates the MPC86xx
processors based on it. Therefore, adding the high BATs, the SPRG
4..7 registers, which are e600-specific [1], and a HW MMU model (as 7400).
This allows to define the MPC8610 processor too.
Tested with a kernel using the HW TLB misses.
[1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf
Signed-off-by: Julio Guerra <guerr@julio.in>
Signed-off-by: Alexander Graf <agraf@suse.de>
Anthony Liguori [Wed, 10 Jul 2013 19:34:32 +0000 (14:34 -0500)]
Merge remote-tracking branch 'luiz/queue/qmp' into staging
# By Kevin Wolf (4) and others
# Via Luiz Capitulino
* luiz/queue/qmp:
add timestamp to error_report()
qapi-schema: Use existing type for drive-backup arguments
qapi-schema: Use BlockdevSnapshot type for blockdev-snapshot-sync
qapi.py: Allow top-level type reference for command definitions
qapi.py: Avoid code duplication
qemu-char: Fix ringbuf option size
Message-id:
1373478767-20965-1-git-send-email-lcapitulino@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Seiji Aguchi [Thu, 4 Jul 2013 03:02:46 +0000 (23:02 -0400)]
add timestamp to error_report()
[Issue]
When we offer a customer support service and a problem happens
in a customer's system, we try to understand the problem by
comparing what the customer reports with message logs of the
customer's system.
In this case, we often need to know when the problem happens.
But, currently, there is no timestamp in qemu's error messages.
Therefore, we may not be able to understand the problem based on
error messages.
[Solution]
Add a timestamp to qemu's error message logged by
error_report() with g_time_val_to_iso8601().
Signed-off-by: Seiji Aguchi <seiji.aguchi@hds.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Kevin Wolf [Tue, 9 Jul 2013 08:05:35 +0000 (10:05 +0200)]
qapi-schema: Use existing type for drive-backup arguments
This removes duplicated definitions and documentation by reusing the
existing data type.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Kevin Wolf [Mon, 1 Jul 2013 14:31:52 +0000 (16:31 +0200)]
qapi-schema: Use BlockdevSnapshot type for blockdev-snapshot-sync
We don't have to duplicate the definition any more now that we may refer
to a type instead.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Kevin Wolf [Mon, 1 Jul 2013 14:31:51 +0000 (16:31 +0200)]
qapi.py: Allow top-level type reference for command definitions
If 'data' for a command definition isn't a dict, but a string, it is
taken as a (struct) type name and the fields of this struct are directly
used as parameters.
This is useful for transactionable commands that can use the same type
definition for both the transaction action and the arguments of the
standalone command.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Kevin Wolf [Mon, 1 Jul 2013 14:31:50 +0000 (16:31 +0200)]
qapi.py: Avoid code duplication
The code that interprets the read JSON expression and appends types to
the respective global variables was duplicated. We can avoid that by
splitting off the part that reads from the file.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Markus Armbruster [Thu, 27 Jun 2013 14:22:07 +0000 (16:22 +0200)]
qemu-char: Fix ringbuf option size
Any attempt to use it trips an "opt->desc->type == QEMU_OPT_NUMBER"
assertion. Broken in commit
1da48c65.
Cc: qemu-stable@nongnu.org
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Anthony Liguori [Wed, 10 Jul 2013 15:54:16 +0000 (10:54 -0500)]
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings
* Fix for OpenRISCCPU subclasses
* Fix for gdbstub CPU selection
* Move linux-user CPU functions into new header
* CPUState part 10 refactoring: first_cpu, next_cpu, cpu_single_env et al.
* Fix some targets to consistently inline TCG code generation
* Centrally log CPU reset
# gpg: Signature made Wed 10 Jul 2013 07:52:39 AM CDT using RSA key ID
3E7E013F
# gpg: Can't check signature: public key not found
# By Andreas Färber (41) and others
# Via Andreas Färber
* afaerber/tags/qom-cpu-for-anthony: (43 commits)
cpu: Move reset logging to CPUState
target-ppc: Change LOG_MMU_STATE() argument to CPUState
target-i386: Change LOG_PCALL_STATE() argument to CPUState
log: Change log_cpu_state[_mask]() argument to CPUState
target-i386: Change do_smm_enter() argument to X86CPU
target-i386: Change do_interrupt_all() argument to X86CPU
target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU
target-unicore32: Change gen_intermediate_code_internal() signature
target-sparc: Change gen_intermediate_code_internal() argument to SPARCCPU
target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPU
target-s390x: Change gen_intermediate_code_internal() argument to S390CPU
target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU
target-mips: Change gen_intermediate_code_internal() argument to MIPSCPU
target-microblaze: Change gen_intermediate_code_internal() argument types
target-m68k: Change gen_intermediate_code_internal() argument to M68kCPU
target-lm32: Change gen_intermediate_code_internal() argument to LM32CPU
target-i386: Change gen_intermediate_code_internal() argument to X86CPU
target-cris: Change gen_intermediate_code_internal() argument to CRISCPU
target-arm: Change gen_intermediate_code_internal() argument to ARMCPU
target-alpha: Change gen_intermediate_code_internal() argument to AlphaCPU
...
Anthony Liguori [Wed, 10 Jul 2013 15:54:09 +0000 (10:54 -0500)]
Merge remote-tracking branch 'riku/linux-user-for-upstream' into staging
# By Andreas Schwab (2) and others
# Via Riku Voipio
* riku/linux-user-for-upstream:
linux-user: Do not ignore mmap failure from host
linux-user: improve target_to_host_sock_type conversion
user-exec.c: Set is_write correctly in the ARM cpu_signal_handler()
linux-user: Fix sys_utimensat (would not compile on old glibc)
linux-user: fix signal number range check
linux-user: add SIOCADDRT/SIOCDELRT support
linux-user: handle /proc/$$ like /proc/self
Message-id: cover.
1373051589.git.riku.voipio@linaro.org
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Anthony Liguori [Wed, 10 Jul 2013 15:53:55 +0000 (10:53 -0500)]
Merge remote-tracking branch 'rth/tcg-next' into staging
# By Richard Henderson
# Via Richard Henderson
* rth/tcg-next:
tcg-arm: Implement tcg_register_jit
tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame size
tcg: Move the CIE and FDE header definitions to common code
tcg: Fix high_pc fields in .debug_info
tcg-arm: Use AT_PLATFORM to detect the host ISA
tcg-arm: Simplify logic in detecting the ARM ISA in use
tcg-arm: Rename use_armv5_instructions to use_armvt5_instructions
tcg-arm: Make use of conditional availability of opcodes for divide
tcg: Simplify logic using TCG_OPF_NOT_PRESENT
tcg: Allow non-constant control macros
tcg-ppc64: Don't implement rem
tcg-ppc: Don't implement rem
tcg-arm: Don't implement rem
tcg: Split rem requirement from div requirement
tcg: Add myself to general TCG maintainership
Message-id:
1373379515-28596-1-git-send-email-rth@twiddle.net
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Peter Crosthwaite [Tue, 18 Jun 2013 09:18:59 +0000 (19:18 +1000)]
qom: Fix class cast of NULL classes
Its clear from the implementation that class casting is supposed to work
with a NULL class argument. Guard all dereferences of the class argument
against NULL accordingly.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
94cd5ba46b74eea289a7e582635820c1c54e66fa.
1371546907.git.peter.crosthwaite@xilinx.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Andreas Färber [Sun, 16 Jun 2013 05:49:48 +0000 (07:49 +0200)]
cpu: Move reset logging to CPUState
x86 was using additional CPU_DUMP_* flags, so make that configurable in
CPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Tue, 2 Jul 2013 22:52:23 +0000 (00:52 +0200)]
target-ppc: Change LOG_MMU_STATE() argument to CPUState
Choose CPUState rather than PowerPCCPU since doing a CPU() cast on the
macro argument would hide type mismatches.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Tue, 2 Jul 2013 23:07:10 +0000 (01:07 +0200)]
target-i386: Change LOG_PCALL_STATE() argument to CPUState
Since log_cpu_state_mask() argument was changed to CPUState,
CPUArchState is no longer needed.
Choose CPUState rather than X86CPU to not hide type mismatches with CPU().
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Sun, 16 Jun 2013 05:28:50 +0000 (07:28 +0200)]
log: Change log_cpu_state[_mask]() argument to CPUState
Since commit
878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turn
cpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is no
longer needed.
Add documentation and make the functions available through qemu/log.h
outside NEED_CPU_H to allow use in qom/cpu.c. Moving them to qom/cpu.h
was not yet possible due to convoluted include paths, so that some
devices grow an implicit and unneeded dependency on qom/cpu.h for now.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Reviewed-by: Richard Henderson <rth@twiddle.net>
[AF: Simplified mb_cpu_do_interrupt() and do_interrupt_all() changes]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Wed, 3 Jul 2013 00:45:17 +0000 (02:45 +0200)]
target-i386: Change do_smm_enter() argument to X86CPU
Prepares for log_cpu_state_mask() changing argument to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Wed, 3 Jul 2013 00:00:09 +0000 (02:00 +0200)]
target-i386: Change do_interrupt_all() argument to X86CPU
Prepares for log_cpu_state() changing argument to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:33:01 +0000 (22:33 +0200)]
target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:29:57 +0000 (22:29 +0200)]
target-unicore32: Change gen_intermediate_code_internal() signature
Use UniCore32CPU and bool.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:27:28 +0000 (22:27 +0200)]
target-sparc: Change gen_intermediate_code_internal() argument to SPARCCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:24:41 +0000 (22:24 +0200)]
target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:22:09 +0000 (22:22 +0200)]
target-s390x: Change gen_intermediate_code_internal() argument to S390CPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:19:32 +0000 (22:19 +0200)]
target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:17:17 +0000 (22:17 +0200)]
target-mips: Change gen_intermediate_code_internal() argument to MIPSCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:14:44 +0000 (22:14 +0200)]
target-microblaze: Change gen_intermediate_code_internal() argument types
Use MicroBlazeCPU and bool.
Prepares for changing log_cpu_state() argument to CPUState and for
moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:11:36 +0000 (22:11 +0200)]
target-m68k: Change gen_intermediate_code_internal() argument to M68kCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:09:30 +0000 (22:09 +0200)]
target-lm32: Change gen_intermediate_code_internal() argument to LM32CPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:09:01 +0000 (22:09 +0200)]
target-i386: Change gen_intermediate_code_internal() argument to X86CPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:04:49 +0000 (22:04 +0200)]
target-cris: Change gen_intermediate_code_internal() argument to CRISCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 19:57:04 +0000 (21:57 +0200)]
target-arm: Change gen_intermediate_code_internal() argument to ARMCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Fri, 21 Jun 2013 20:01:20 +0000 (22:01 +0200)]
target-alpha: Change gen_intermediate_code_internal() argument to AlphaCPU
Also use bool argument while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Tue, 2 Jul 2013 18:05:21 +0000 (20:05 +0200)]
target-xtensa: gen_intermediate_code_internal() should be inlined
Cc: qemu-stable@nongnu.org
Reported-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Tue, 2 Jul 2013 18:04:28 +0000 (20:04 +0200)]
target-moxie: gen_intermediate_code_internal() should be inlined
Cc: qemu-stable@nongnu.org
Reported-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Tue, 2 Jul 2013 18:03:00 +0000 (20:03 +0200)]
target-microblaze: gen_intermediate_code_internal() should be inlined
Cc: qemu-stable@nongnu.org
Reported-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Tue, 2 Jul 2013 17:35:02 +0000 (19:35 +0200)]
target-lm32: gen_intermediate_code_internal() should be inlined
Cc: qemu-stable@nongnu.org
Reported-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: Michael Walle <michael@walle.cc>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Andreas Färber [Tue, 2 Jul 2013 17:30:14 +0000 (19:30 +0200)]
target-cris: gen_intermediate_code_internal() should be inlined
Cc: qemu-stable@nongnu.org
Reported-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>