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Reid Kleckner [Tue, 31 Jan 2017 00:34:23 +0000 (00:34 +0000)]
Remove LLVM_CONFIG from config headers
It appears to be dead, and it needlessly caused me to rebuild all of
LLVM when I changed CMAKE_INSTALL_PREFIX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293574
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Vedant Kumar [Mon, 30 Jan 2017 23:58:51 +0000 (23:58 +0000)]
Fix llvm-readobj build error after r293569
Clang complains about an ambiguous call to printNumber() because it
can't work out what size_t should convert to. I picked uint64_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293573
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Keno Fischer [Mon, 30 Jan 2017 23:37:03 +0000 (23:37 +0000)]
[ExecutionDepsFix] Improve clearance calculation for loops
Summary:
In revision rL278321, ExecutionDepsFix learned how to pick a better
register for undef register reads, e.g. for instructions such as
`vcvtsi2sdq`. While this revision improved performance on a good number
of our benchmarks, it unfortunately also caused significant regressions
(up to 3x) on others. This regression turned out to be caused by loops
such as:
PH -> A -> B (xmm<Undef> -> xmm<Def>) -> C -> D -> EXIT
^ |
+----------------------------------+
In the previous version of the clearance calculation, we would visit
the blocks in order, remembering for each whether there were any
incoming backedges from blocks that we hadn't processed yet and if
so queuing up the block to be re-processed. However, for loop structures
such as the above, this is clearly insufficient, since the block B
does not have any unknown backedges, so we do not see the false
dependency from the previous interation's Def of xmm registers in B.
To fix this, we need to consider all blocks that are part of the loop
and reprocess them one the correct clearance values are known. As
an optimization, we also want to avoid reprocessing any later blocks
that are not part of the loop.
In summary, the iteration order is as follows:
Before: PH A B C D A'
Corrected (Naive): PH A B C D A' B' C' D'
Corrected (w/ optimization): PH A B C A' B' C' D
To facilitate this optimization we introduce two new counters for each
basic block. The first counts how many of it's predecssors have
completed primary processing. The second counts how many of its
predecessors have completed all processing (we will call such a block
*done*. Now, the criteria to reprocess a block is as follows:
- All Predecessors have completed primary processing
- For x the number of predecessors that have completed primary
processing *at the time of primary processing of this block*,
the number of predecessors that are done has reached x.
The intuition behind this criterion is as follows:
We need to perform primary processing on all predecessors in order to
find out any direct defs in those predecessors. When predecessors are
done, we also know that we have information about indirect defs (e.g.
in block B though that were inherited through B->C->A->B). However,
we can't wait for all predecessors to be done, since that would
cause cyclic dependencies. However, it is guaranteed that all those
predecessors that are prior to us in reverse postorder will be done
before us. Since we iterate of the basic blocks in reverse postorder,
the number x above, is precisely the count of the number of predecessors
prior to us in reverse postorder.
Reviewers: myatsina
Differential Revision: https://reviews.llvm.org/D28759
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293571
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Sanjay Patel [Mon, 30 Jan 2017 23:35:52 +0000 (23:35 +0000)]
[InstCombine] enable (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2) for vectors with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293570
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Derek Schuff [Mon, 30 Jan 2017 23:30:52 +0000 (23:30 +0000)]
[WebAssembly] Add wasm support for llvm-readobj
Create a WasmDumper subclass of ObjDumper to support Webassembly binary
files.
Patch by Sam Clegg
Differential Revision: https://reviews.llvm.org/D27355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293569
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Matt Arsenault [Mon, 30 Jan 2017 23:27:11 +0000 (23:27 +0000)]
NVPTX: Trivial cleanups of NVPTXInferAddressSpaces
- Move DEBUG_TYPE below includes
- Change unknown address space constant to be consistent with other
passes
- Grammar fixes in debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293567
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Sanjay Patel [Mon, 30 Jan 2017 23:26:17 +0000 (23:26 +0000)]
[InstCombine] add vector test for (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293566
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Eugene Zelenko [Mon, 30 Jan 2017 23:21:32 +0000 (23:21 +0000)]
[Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293565
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Benjamin Kramer [Mon, 30 Jan 2017 23:11:29 +0000 (23:11 +0000)]
[ICP] Fix bool conversion warning and actually write out the reason instead of dropping it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293564
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Matt Arsenault [Mon, 30 Jan 2017 23:02:12 +0000 (23:02 +0000)]
NVPTX: Refactor NVPTXInferAddressSpaces to check TTI
Add a new TTI hook for getting the generic address space value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293563
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Sanjay Patel [Mon, 30 Jan 2017 23:01:05 +0000 (23:01 +0000)]
[InstCombine] enable more lshr(shl X, C1), C2 folds for vectors with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293562
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Simon Pilgrim [Mon, 30 Jan 2017 22:58:44 +0000 (22:58 +0000)]
[X86][SSE] Fix unsigned <= 0 warning in assert. NFCI.
Thanks to @mkuper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293561
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Simon Pilgrim [Mon, 30 Jan 2017 22:48:49 +0000 (22:48 +0000)]
[X86][SSE] Generalize the number of decoded shuffle inputs. NFCI.
combineX86ShufflesRecursively can still only handle a maximum of 2 shuffle inputs but everything before it now supports any number of shuffle inputs.
This will be necessary for combining OR(SHUFFLE, SHUFFLE) patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293560
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Dehao Chen [Mon, 30 Jan 2017 22:46:37 +0000 (22:46 +0000)]
Expose isLegalToPromot as a global helper function so that SamplePGO pass can call it for legality check.
Summary: SamplePGO needs to check if it is legal to promote a target before it actually promotes it.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D29306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293559
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Dehao Chen [Mon, 30 Jan 2017 22:26:05 +0000 (22:26 +0000)]
Revert r292979 which causes compile time failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293557
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Sanjay Patel [Mon, 30 Jan 2017 22:24:36 +0000 (22:24 +0000)]
[InstCombine] add tests for more shift-shift patterns; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293555
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Eli Friedman [Mon, 30 Jan 2017 22:04:23 +0000 (22:04 +0000)]
Fix line endings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293554
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Tom Stellard [Mon, 30 Jan 2017 22:02:58 +0000 (22:02 +0000)]
AMDGPU: Fix release build broken by r293551
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293553
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Artem Tamazov [Mon, 30 Jan 2017 21:59:21 +0000 (21:59 +0000)]
Reapply [AMDGPU][mc][tests][NFC] Add coverage/smoke tests for Gfx7 and Gfx8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293552
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Tom Stellard [Mon, 30 Jan 2017 21:56:46 +0000 (21:56 +0000)]
Re-commit AMDGPU/GlobalISel: Add support for simple shaders
Fix build when global-isel is disabled and fix a warning.
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293551
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Tim Northover [Mon, 30 Jan 2017 21:45:21 +0000 (21:45 +0000)]
GlobalISel: correctly translate invoke when callee is a register.
This should fix the GlobalISel verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293550
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Stanislav Mekhanoshin [Mon, 30 Jan 2017 21:05:18 +0000 (21:05 +0000)]
[AMDGPU] Internalize non-kernel symbols
Since we have no call support and late linking we can produce code
only for used symbols. This saves compilation time, size of the final
executable, and size of any intermediate dumps.
Run Internalize pass early in the opt pipeline followed by global
DCE pass. To enable it RT can pass -amdgpu-internalize-symbols option.
Differential Revision: https://reviews.llvm.org/D29214
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293549
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Kevin Enderby [Mon, 30 Jan 2017 20:53:17 +0000 (20:53 +0000)]
Change the llvm-obdump(1) behavior with the -macho flag and inappropriate file types.
To better match the old darwin otool(1) behavior, when llvm-obdump(1) is used
with the -macho option and the input file is not an object file simply print
the file name and this message:
foo: is not an object file
and continue on to process other input files. Also in this case don’t exit
non-zero. This should help in some OSS projects' with autoconf scripts
that are expecting the old darwin otool(1) behavior.
rdar://
26828015
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293547
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Tim Northover [Mon, 30 Jan 2017 20:52:42 +0000 (20:52 +0000)]
GlobalISel: account for differing exception selector sizes.
For some reason the exception selector register must be a pointer (that's
assumed by SDag); on the other hand, it gets moved into an IR-level type which
might be entirely different (i32 on AArch64). IRTranslator needs to be aware of
this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293546
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Tim Northover [Mon, 30 Jan 2017 20:52:37 +0000 (20:52 +0000)]
GlobalISel: tidy up def/use test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293545
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Matt Arsenault [Mon, 30 Jan 2017 19:50:17 +0000 (19:50 +0000)]
LSR: Don't drop address space when type doesn't match
For targets with different addressing modes in each address space,
if this is dropped querying isLegalAddressingMode later with this
will give a nonsense result, breaking the isLegalUse assertions.
This is a candidate for the 4.0 release branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293542
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Tim Northover [Mon, 30 Jan 2017 19:33:07 +0000 (19:33 +0000)]
GlobalISel: translate memset & memmove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293541
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Matt Arsenault [Mon, 30 Jan 2017 19:30:24 +0000 (19:30 +0000)]
AMDGPU: Undo sub x, c -> add x, -c canonicalization
This is worse if the original constant is an inline immediate.
This should also be done for 64-bit adds, but requires fixing
operand folding bugs first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293540
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Krzysztof Parzyszek [Mon, 30 Jan 2017 19:16:30 +0000 (19:16 +0000)]
[RDF] Add support for regmasks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293538
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Tim Northover [Mon, 30 Jan 2017 19:12:50 +0000 (19:12 +0000)]
GlobalISel: permit unused vregs without a register-class after ISel.
This can happen if earlier combining has removed all uses of some VReg, which
is fine and shouldn't flag an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293537
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Benjamin Kramer [Mon, 30 Jan 2017 19:05:09 +0000 (19:05 +0000)]
Fix the GCC build.
This is fairly ugly, but apparently GCC still doesn't understand C++11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293535
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Michael Kuperstein [Mon, 30 Jan 2017 19:03:26 +0000 (19:03 +0000)]
Turn a TableGen FastISelEmitter warning into an error.
Tablegen emitted a warning when the fast isel emitter created dead
code by emitting a pattern that has no predicate before a pattern
that has one.
This should be an error but was originally only a warning because the X86
backend had a buggy definition that unintentionally caused this to be hit
(PR21575). That has been fixed a while ago (r222094), so it's safe to
upgrade the warning to an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293534
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Simon Pilgrim [Mon, 30 Jan 2017 18:59:25 +0000 (18:59 +0000)]
[X86][XOP] Fix test name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293533
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Simon Pilgrim [Mon, 30 Jan 2017 18:53:45 +0000 (18:53 +0000)]
Use SelectionDAG::getBuildVector helper function where possible. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293532
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Benjamin Kramer [Mon, 30 Jan 2017 18:49:24 +0000 (18:49 +0000)]
[IR] Remove global constructor from Function.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293528
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Benjamin Kramer [Mon, 30 Jan 2017 18:46:26 +0000 (18:46 +0000)]
[MC] Remove global constructors from MCSectionMachO.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293526
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Matt Arsenault [Mon, 30 Jan 2017 18:40:29 +0000 (18:40 +0000)]
AMDGPU: Run AMDGPUCodeGenPrepare after inlining
With leaf functions, this makes nonsensical decisions
based on the uniformity of the arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293525
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Sanjay Patel [Mon, 30 Jan 2017 18:40:23 +0000 (18:40 +0000)]
[InstCombine] enable (X >>?exact C1) << C2 --> X >>?exact (C1-C2) for vectors with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293524
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Justin Bogner [Mon, 30 Jan 2017 18:29:46 +0000 (18:29 +0000)]
SDAG: Update ChainNodesMatched during UpdateChains if a node is replaced
Previously, we would hit UB (or the ISD::DELETED_NODE assert) if we
happened to replace a node during UpdateChains, because it would be
left in the list we were iterating over. This nulls out the pointer
when that happens so that we can avoid the issue.
Fixes llvm.org/PR31710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293522
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Simon Pilgrim [Mon, 30 Jan 2017 18:20:42 +0000 (18:20 +0000)]
Use SelectionDAG::getBuildVector/getSplatBuildVector helper functions where possible. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293520
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Sanjay Patel [Mon, 30 Jan 2017 18:17:14 +0000 (18:17 +0000)]
[InstCombine] add vector splat tests for (X >>?exact C1) << C2 --> X >>?exact (C1-C2); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293517
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Marcos Pividori [Mon, 30 Jan 2017 18:14:53 +0000 (18:14 +0000)]
[libFuzzer] Implement TmpDir() for Windows.
Differential Revision: https://reviews.llvm.org/D28977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293516
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Daniel Berlin [Mon, 30 Jan 2017 18:12:56 +0000 (18:12 +0000)]
NewGVN: Instead of changeToUnreachable, insert an instruction SimplifyCFG will turn into unreachable when it runs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293515
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Matt Arsenault [Mon, 30 Jan 2017 18:11:38 +0000 (18:11 +0000)]
AMDGPU: Make i32 uaddo/usubo legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293514
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Matt Arsenault [Mon, 30 Jan 2017 17:57:28 +0000 (17:57 +0000)]
DAG: Fold fneg into compare with constant into the constant
fcmp (fneg x), c, pred -> fcmp x, -c, (swap pred)
InstCombine already does this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293512
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Benjamin Kramer [Mon, 30 Jan 2017 17:54:57 +0000 (17:54 +0000)]
[Orc] Add missing include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293511
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Krzysztof Parzyszek [Mon, 30 Jan 2017 17:46:56 +0000 (17:46 +0000)]
[RDF] Extract the physical register information into a separate class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293510
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Tom Stellard [Mon, 30 Jan 2017 17:42:41 +0000 (17:42 +0000)]
Revert "AMDGPU/GlobalISel: Add support for simple shaders"
This reverts commit r293503.
Revert while I investigate some of the buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293509
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Sanjay Patel [Mon, 30 Jan 2017 17:38:55 +0000 (17:38 +0000)]
[InstCombine] use auto with obvious type; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293508
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Sanjay Patel [Mon, 30 Jan 2017 17:19:32 +0000 (17:19 +0000)]
[InstCombine] enable (X <<nsw C1) >>s C2 --> X <<nsw (C1-C2) for vectors with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293507
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David Blaikie [Mon, 30 Jan 2017 17:13:56 +0000 (17:13 +0000)]
unique_ptrify some containers in GlobalISel::RegisterBankInfo
To simplify/clarify memory ownership, make leaks (as one was found/fixed
recently) harder to write, etc.
(also, while I was there - removed a duplicate lookup in a container)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293506
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Matt Arsenault [Mon, 30 Jan 2017 17:09:47 +0000 (17:09 +0000)]
AMDGPU: Fix atomic_inc/atomic_dec + ds_swizzle not being divergent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293504
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Tom Stellard [Mon, 30 Jan 2017 17:09:15 +0000 (17:09 +0000)]
AMDGPU/GlobalISel: Add support for simple shaders
Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP.
Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm
Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris
Differential Revision: https://reviews.llvm.org/D26730
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293503
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Daniel Berlin [Mon, 30 Jan 2017 17:08:06 +0000 (17:08 +0000)]
Update pr31758.ll for unreachable revert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293502
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Daniel Berlin [Mon, 30 Jan 2017 17:06:55 +0000 (17:06 +0000)]
Revert "NewGVN: Make unreachable blocks be marked with unreachable"
This reverts commit r293196
Besides making things look nicer, ATM, we'd like to preserve analysis
more than we'd like to destroy the CFG. We'll probably revisit in the future
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293501
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Simon Pilgrim [Mon, 30 Jan 2017 16:58:34 +0000 (16:58 +0000)]
[X86][SSE] Add support for combining PINSRW+ASSERTZEXT+PEXTRW patterns with target shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293500
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Matt Arsenault [Mon, 30 Jan 2017 16:57:41 +0000 (16:57 +0000)]
DAG: Constant fold fp16_to_fp/fp16_to_fp
This fixes emitting conversions of constants on targets
without legal f16 that need to use these for legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293499
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Sanjay Patel [Mon, 30 Jan 2017 16:53:03 +0000 (16:53 +0000)]
[InstCombine] fixed to propagate 'exact' on lshr
The original shift is bigger, so this may qualify as 'obvious',
but here's an attempt at an Alive-based proof:
Name: exact
Pre: (C1 u< C2)
%a = shl i8 %x, C1
%b = lshr exact i8 %a, C2
=>
%c = lshr exact i8 %x, C2 - C1
%b = and i8 %c, ((1 << width(C1)) - 1) u>> C2
Optimization is correct!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293498
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Sanjay Patel [Mon, 30 Jan 2017 16:38:49 +0000 (16:38 +0000)]
[InstCombine] add 'exact' to lshr to show that it got dropped; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293496
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Benjamin Kramer [Mon, 30 Jan 2017 16:32:20 +0000 (16:32 +0000)]
[Coroutines] Add header guard to header that's missing one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293494
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Adam Nemet [Mon, 30 Jan 2017 16:22:45 +0000 (16:22 +0000)]
[Inliner] Fold analysis remarks into missed remarks
This significantly reduces the noise level of these messages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293492
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Krzysztof Parzyszek [Mon, 30 Jan 2017 16:20:30 +0000 (16:20 +0000)]
[RDF] Add phis for entry block live-ins (in addition to function live-ins)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293491
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Haicheng Wu [Mon, 30 Jan 2017 16:15:14 +0000 (16:15 +0000)]
[Inliner] Fix a comment to match the code. NFC.
TotalAltCost => TotalSecondaryCost
Differential Revision: https://reviews.llvm.org/D29231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293490
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Sanjay Patel [Mon, 30 Jan 2017 16:11:40 +0000 (16:11 +0000)]
[InstCombine] enable lshr(shl X, C1), C2 folds for vectors with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293489
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Sanjay Patel [Mon, 30 Jan 2017 15:54:50 +0000 (15:54 +0000)]
[InstCombine] add tests for shift-shift patterns; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293487
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Rafael Espindola [Mon, 30 Jan 2017 15:49:20 +0000 (15:49 +0000)]
Bring back r293480. It is safe now.
Original message:
Fix the values of two xcore ELF flags.
The values in llvm grew from a pre-MC day when they would not show up
in .o files and are outside of the SHF_MASKPROC.
Fortunately the MC output is not currently used as xcore has its own
assemble and that assembler uses valid values. This updates llvm to
use the same values as the xmos assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293486
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Rafael Espindola [Mon, 30 Jan 2017 15:38:43 +0000 (15:38 +0000)]
Only print architecture dependent flags for that architecture.
Different architectures can have different meaning for flags in the
SHF_MASKPROC mask, so we should always check what the architecture use
before checking the flag.
NFC for now, but will allow fixing the value of an xmos flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293484
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Tom Stellard [Mon, 30 Jan 2017 15:07:01 +0000 (15:07 +0000)]
TableGen: Fix infinite recursion in RegisterBankEmitter
Summary:
AMDGPU has two register classes with the same set of registers, and this
was causing this tablegen backend would get stuck in infinite recursion.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: tpr, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D29049
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293483
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Benjamin Kramer [Mon, 30 Jan 2017 14:55:33 +0000 (14:55 +0000)]
[Hexagon] Make header self-contained.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293482
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Rafael Espindola [Mon, 30 Jan 2017 14:39:48 +0000 (14:39 +0000)]
Revert "Fix the values of two xcore ELF flags."
This reverts commit r293480.
The patch is correct, but found bugs in other areas that need to be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293481
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Rafael Espindola [Mon, 30 Jan 2017 14:07:43 +0000 (14:07 +0000)]
Fix the values of two xcore ELF flags.
The values in llvm grew from a pre-MC day when they would not show up
in .o files and are outside of the SHF_MASKPROC.
Fortunately the MC output is not currently used as xcore has its own
assemble and that assembler uses valid values. This updates llvm to
use the same values as the xmos assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293480
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Asaf Badouh [Mon, 30 Jan 2017 13:14:37 +0000 (13:14 +0000)]
[X86][MCU] Minor bug fix for r293469 + test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293478
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Marek Olsak [Mon, 30 Jan 2017 12:25:14 +0000 (12:25 +0000)]
AMDGPU: Remove a useless VI SMRD pattern
Summary: already covered by complex patterns
Reviewers: arsenm, nhaehnle, tstellarAMD
Subscribers: kzhuravl, wdng, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D28995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293477
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Marek Olsak [Mon, 30 Jan 2017 12:25:03 +0000 (12:25 +0000)]
AMDGPU: Fix assembler encoding for EXP instructions on VI
Reviewers: arsenm, tstellarAMD
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D28992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293476
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Daniel Berlin [Mon, 30 Jan 2017 11:35:39 +0000 (11:35 +0000)]
Revert "[MemorySSA] Revert r293361 and r293363, as the tests fail under asan."
This reverts commit r293471, reapplying r293361 and r293363 with a fix
for an out-of-bounds read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293474
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Sam McCall [Mon, 30 Jan 2017 09:19:50 +0000 (09:19 +0000)]
[MemorySSA] Revert r293361 and r293363, as the tests fail under asan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293471
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Kristof Beyls [Mon, 30 Jan 2017 09:13:18 +0000 (09:13 +0000)]
[GlobalISel] Add support for indirectbr
Differential Revision: https://reviews.llvm.org/D28079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293470
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Asaf Badouh [Mon, 30 Jan 2017 08:16:59 +0000 (08:16 +0000)]
[X86][MCU] replace select with bit manipulation instead of branches
Differential Revision: https://reviews.llvm.org/D28354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293469
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Alexey Bader [Mon, 30 Jan 2017 07:38:58 +0000 (07:38 +0000)]
[LanRef] Fix typo in getelementptr example.
Summary: Change B type from double to pointer to double.
Reviewers: delena, sanjoy
Reviewed By: sanjoy
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D29009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293467
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Craig Topper [Mon, 30 Jan 2017 06:59:06 +0000 (06:59 +0000)]
[AVX-512] Remove duplicate CodeGenOnly patterns for scalar register broadcast. We can use COPY_TO_REGCLASS like AVX does.
This causes stack spill slots be oversized sometimes, but the same should already be happening with AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293464
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Sam McCall [Mon, 30 Jan 2017 05:40:52 +0000 (05:40 +0000)]
Include LLVMDumpValue in release builds.
This part of the C API is still used in language bindings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293460
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Jonas Paulsson [Mon, 30 Jan 2017 05:38:05 +0000 (05:38 +0000)]
[LoopVectorize] Improve getVectorCallCost() getScalarizationOverhead() call.
By calling getScalarizationOverhead with the CallInst instead of the types of
its arguments, we make sure that only unique call arguments are added to the
scalarization cost.
getScalarizationOverhead() is extended to handle calls by only passing on the
actual call arguments (which is not all the operands).
This also eliminates a wrapper function with the same name.
review: Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293459
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Craig Topper [Mon, 30 Jan 2017 05:37:47 +0000 (05:37 +0000)]
[AVX-512] Remove KSET0B/KSET1B in favor of the patterns that select KSET0W/KSET1W for v8i1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293458
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Davide Italiano [Mon, 30 Jan 2017 03:16:43 +0000 (03:16 +0000)]
[MemorySSA] Correct an assertion surrounding with parentheses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293453
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Will Dietz [Mon, 30 Jan 2017 01:28:42 +0000 (01:28 +0000)]
Test RuntimeDyld doesn't crash with R_X86_64_NONE (r293388).
Largely based on LLD test for dtrace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293451
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Craig Topper [Mon, 30 Jan 2017 00:06:01 +0000 (00:06 +0000)]
[AVX-512] Don't reuse VSHLI/VSRLI for mask register shifts. VSHLI/VSHRI shift within elements while KSHIFT moves whole elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293448
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Chris Ray [Sun, 29 Jan 2017 23:02:47 +0000 (23:02 +0000)]
[X86][Disassembler] Added SALC instruction
Reviewers: joe.abbey, craig.topper
Reviewed By: craig.topper
Subscribers: majnemer, llvm-commits
Differential Revision: https://reviews.llvm.org/D29201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293447
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Craig Topper [Sun, 29 Jan 2017 22:53:33 +0000 (22:53 +0000)]
[AVX-512] Fix lowering for mask register concatenation with undef in the lower half.
Previously this test case fired an assertion in getNode because we tried to create an insert_subvector with both input types the same size and the index pointing to half the vector width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293446
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Chris Ray [Sun, 29 Jan 2017 20:05:30 +0000 (20:05 +0000)]
[X86] Fixing flag usage for RCL and RCR
Summary: The RCL and RCR instructions use the carry flag.
Reviewers: craig.topper
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D29237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293441
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Matthias Braun [Sun, 29 Jan 2017 18:20:42 +0000 (18:20 +0000)]
MachineInstr: Remove parameter from dump()
The primary use of the dump() functions in LLVM is for use in a
debugger. Unfortunately lldb does not seem to handle default arguments
so using `p SomeMI.dump()` fails and you have to type the longer `p
SomeMI.dump(nullptr)`. Remove the paramter to make the most common use
easy. (You can always construct something like `p
SomeMI.print(dbgs(),MyTII)` if you need more features).
Differential Revision: https://reviews.llvm.org/D29241
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293440
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Simon Pilgrim [Sun, 29 Jan 2017 18:13:37 +0000 (18:13 +0000)]
[X86][SSE] Lower scalar_to_vector(0) to zero vector
Replaces an xor+movd/movq with an xorps which will be shorter in codesize, avoid an int-fpu transfer, allow modern cores to fast path the result during decode and helps other combines recognise an all-zero vector.
The only reason I can think of that we'd want to keep scalar_to_vector in this case is to help recognise the upper elts are undef but this doesn't seem to be a problem.
Differential Revision: https://reviews.llvm.org/D29097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293438
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Zvi Rackover [Sun, 29 Jan 2017 17:57:26 +0000 (17:57 +0000)]
[X86] Reproducer for pr31719. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293437
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Matthias Braun [Sun, 29 Jan 2017 17:52:03 +0000 (17:52 +0000)]
llvm-c: Keep LLVMDumpModule() even in release builds
While this probably should be considered a dump debugger utility, the C
API currently has no other ways to print a module to stderr for error
reporting purposes, so keep it even in release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293436
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Sanjay Patel [Sun, 29 Jan 2017 17:11:18 +0000 (17:11 +0000)]
[InstCombine] enable (X >>?,exact C1) << C2 --> X << (C2 - C1) for vectors with splats
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293435
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Sanjay Patel [Sun, 29 Jan 2017 16:52:59 +0000 (16:52 +0000)]
[InstCombine] add tests for shl(shr X, C1), C2 transforms; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293434
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Saleem Abdulrasool [Sun, 29 Jan 2017 16:46:22 +0000 (16:46 +0000)]
ARM: support `-mlong-calls` with AEABI TLS on ELF
Support lowering AEABI TLS access (__aeabi_read_tp) with long calls.
This requires adjusting the call sequence to use an indirect call to get
full addressability.
Resolves PR31769!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293433
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Sanjay Patel [Sun, 29 Jan 2017 16:34:57 +0000 (16:34 +0000)]
[ValueTracking] clean up lookThroughCast; NFCI
1. Use auto with dyn_cast.
2. Don't use else after return.
3. Convert chain of 'else if' to switch.
4. Improve variable names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293432
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Elena Demikhovsky [Sun, 29 Jan 2017 13:18:30 +0000 (13:18 +0000)]
[X86 Codegen] Fixed a bug in unsigned saturation
PACKUSWB converts Signed word to Unsigned byte, (the same about DW) and it can't be used for umin+truncate pattern.
AVX-512 VPMOVUS* instructions fit the pattern since they convert Unsigned to Unsigned.
See https://llvm.org/bugs/show_bug.cgi?id=31773
Differential Revision: https://reviews.llvm.org/D29196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293431
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NAKAMURA Takumi [Sun, 29 Jan 2017 11:10:34 +0000 (11:10 +0000)]
Add -mtriple=aarch64-unknown to llvm/test/CodeGen/AArch64/GlobalISel/gisel-abort.ll.
Unsupported target might be induced if default target is neither macho nor elf. (e.g. *-win32)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293430
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Daniel Berlin [Sun, 29 Jan 2017 10:26:03 +0000 (10:26 +0000)]
NewGVN: Fix where newline is printed in debug printing of memory equivalence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293428
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