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Tom Stellard [Wed, 9 May 2012 15:06:48 +0000 (11:06 -0400)]
radeon/llvm: Add some comments
Tom Stellard [Thu, 10 May 2012 16:49:41 +0000 (12:49 -0400)]
radeon/llvm: Move util functions into AMDGPU namespace
Paul Berry [Mon, 30 Apr 2012 05:05:28 +0000 (22:05 -0700)]
i965/hiz: Convert gen{6,7}_hiz.h to gen{6,7}_blorp.h
This patch renames the gen6_hiz.h and gen7_hiz.h files to correspond
to the renames of the corresponding .cpp files (see previous commit).
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Mon, 30 Apr 2012 04:50:22 +0000 (21:50 -0700)]
i965/hiz: Convert gen{6,7}_hiz.c to C++
This patch converts the files gen6_hiz.c and gen7_hiz.c to C++, in
preparation for expanding the HiZ code to support arbitrary blits.
The new files are called gen6_blorp.cpp and gen7_blorp.cpp to reflect
the expanded role that this code will serve--"blorp" stands for "BLit
Or Resolve Pass".
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Thu, 26 Apr 2012 16:29:19 +0000 (09:29 -0700)]
i965/hiz: Make void pointer type casts explicit
Previous to this patch, gen6_hiz.c contained two implicit type casts
from void * to a a non-void pointer type. This is allowed in C but
not in C++. This patch makes the type casts explicit, so that
gen6_hiz.c can be converted into a C++ file.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Mon, 30 Apr 2012 04:46:47 +0000 (21:46 -0700)]
intel: Work around differences between C and C++ scoping rules.
In C++, if a struct is defined inside another struct, or its name is
first seen inside a struct or function, the struct is nested inside
the namespace of the struct or function it appears in. In C, all
structs are visible from toplevel.
This patch explicitly moves the decalartions of intel_batchbuffer to
toplevel, so that it does not get nested inside a namespace when
header files are included from C++.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Fri, 27 Apr 2012 14:40:34 +0000 (07:40 -0700)]
intel: Add extern "C" declarations to headers
These declarations are necessary to allow C++ code to call C code
without causing unresolved symbols (which would make the driver fail
to load).
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Tom Stellard [Thu, 10 May 2012 15:52:00 +0000 (11:52 -0400)]
radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_eg
Tom Stellard [Thu, 10 May 2012 15:31:52 +0000 (11:31 -0400)]
radeon/llvm: Delete all instructions that have been custom lowered
Michel Dänzer [Thu, 10 May 2012 11:54:39 +0000 (13:54 +0200)]
radeonsi: Set NONE format for unused vertex shader position export slots.
Michel Dänzer [Thu, 10 May 2012 11:54:27 +0000 (13:54 +0200)]
radeonsi: Eliminate one more magic number for texture image resources.
Michel Dänzer [Thu, 10 May 2012 11:54:27 +0000 (13:54 +0200)]
radeonsi: Fix vertex buffer resource for stride 0.
Tom Stellard [Wed, 9 May 2012 15:50:02 +0000 (11:50 -0400)]
radeon/llvm: Remove AMDGPUConstants.pm
Tom Stellard [Wed, 9 May 2012 15:44:27 +0000 (11:44 -0400)]
radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_const
Tom Stellard [Wed, 9 May 2012 15:43:17 +0000 (11:43 -0400)]
radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicate
Brian Paul [Wed, 9 May 2012 16:31:07 +0000 (10:31 -0600)]
svga: implement CEIL opcode translation
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Christoph Bumiller [Sat, 5 May 2012 12:38:09 +0000 (14:38 +0200)]
glsl_to_tgsi: use TGSI_OPCODE_CEIL for ir_unop_ceil
The implementation using FLR was buggy, the second negation could
get lost.
Christoph Bumiller [Sat, 5 May 2012 12:36:40 +0000 (14:36 +0200)]
gallium/drivers: handle TGSI_OPCODE_CEIL
Kai Wasserbäch [Mon, 7 May 2012 15:59:35 +0000 (17:59 +0200)]
r600g: Handle TGSI_OPCODE_CEIL (v2)
v2: Enabled CEIL on Cayman too.
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Dave Airlie [Mon, 6 Feb 2012 18:33:21 +0000 (18:33 +0000)]
gallivm: implement iabs/issg opcode.
Reimplemented by Olivier Galibert <galibert@pobox.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Yuanhan Liu [Wed, 2 May 2012 09:29:11 +0000 (17:29 +0800)]
i965: fix wrong cube/3D texture layout
Fix wrong cube/3D texture layout for the tailing levels whose width or
height is smaller than the align unit.
From 965 B-spec http://intellinuxgraphics.org/VOL_1_graphics_core.pdf at
page 135:
All of the LOD=0 q-planes are stacked vertically, then below that,
the LOD=1 qplanes are stacked two-wide, then the LOD=2 qplanes are
stacked four-wide below that, and so on.
Thus we should always inrease pack_x_nr, which results to the pitch of LODn
may greater than the pitch of LOD0. So we should refactor mt->total_width
when needed.
This would fix the following webgl test case on all gen4 platforms:
conformance/textures/texture-size-cube-maps.html
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Tom Stellard [Tue, 8 May 2012 19:37:59 +0000 (15:37 -0400)]
radeon/llvm: Remove AMDILUtilityFunctions.cpp
Tom Stellard [Tue, 8 May 2012 17:59:27 +0000 (13:59 -0400)]
radeon/llvm: Remove some unused functions from AMDILInstrInfo
Tom Stellard [Mon, 7 May 2012 18:52:11 +0000 (14:52 -0400)]
radeon/llvm: Add some comments and fix coding style
Tom Stellard [Tue, 8 May 2012 17:08:29 +0000 (13:08 -0400)]
radeon/llvm: Remove the EXPORT_REG instruction
Tom Stellard [Tue, 8 May 2012 15:33:05 +0000 (11:33 -0400)]
radeon/llvm: Use a custom inserter to lower RESERVE_REG
Tom Stellard [Tue, 8 May 2012 14:27:30 +0000 (10:27 -0400)]
radeon/llvm: Use a custom inserter to lower STORE_OUTPUT
Tom Stellard [Tue, 8 May 2012 14:04:44 +0000 (10:04 -0400)]
radeon/llvm: Remove AMDGPULowerShaderInstructions class
It is no longer used.
Tom Stellard [Tue, 8 May 2012 14:01:58 +0000 (10:01 -0400)]
radeon/llvm: Use a custom inserter to lower LOAD_INPUT
Tom Stellard [Mon, 7 May 2012 19:20:26 +0000 (15:20 -0400)]
radeon/llvm: Remove the ReorderPreloadInstructions pass
Tom Stellard [Mon, 7 May 2012 18:51:27 +0000 (14:51 -0400)]
radeon/llvm: Remove old comment from AMDIL.h
Paul Berry [Tue, 8 May 2012 18:03:55 +0000 (11:03 -0700)]
Add bin/compile to .gitignore
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Olivier Galibert [Wed, 2 May 2012 21:11:42 +0000 (23:11 +0200)]
glsl: Change built-in constant expression evaluation to run the IR.
This removes code duplication with
ir_expression::constant_expression_value and builtins/ir/*.
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Olivier Galibert [Wed, 2 May 2012 21:11:41 +0000 (23:11 +0200)]
glsl: Add an origin pointer in the function signature object.
This points to the object with the function body, allowing us to map
from a built-in prototype to the actual body with IR code to execute.
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Olivier Galibert [Wed, 2 May 2012 21:11:40 +0000 (23:11 +0200)]
glsl: Add methods to copy parts of one ir_constant into another.
- copy_masked_offset copies part of a constant into another,
assign-like.
- copy_offset copies a constant into (a subset of) another,
funcall-return like.
These methods are to be used to trace through assignments and function
calls when computing a constant expression.
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Olivier Galibert [Wed, 2 May 2012 21:11:39 +0000 (23:11 +0200)]
glsl: Add a constant_referenced method to ir_dereference*
The method is used to get a reference to an ir_constant * within the
context of evaluating an assignment when calculating a
constant_expression_value.
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Olivier Galibert [Wed, 2 May 2012 21:11:38 +0000 (23:11 +0200)]
glsl: Add a variable context to constant_expression_value().
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Olivier Galibert [Wed, 2 May 2012 21:11:37 +0000 (23:11 +0200)]
glsl: Extend ir_constant::zero to handle more types.
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Kenneth Graunke [Tue, 8 May 2012 19:04:45 +0000 (12:04 -0700)]
glsl: Fix broken constant expression handling for <, <=, >, and >=.
We were looping over all the vector components, but only dealing with
the first one. This was masked by the fact that constant expression
handling on built-ins went through custom code for the lessThan()
/function/ rather than the ir_binop_less expression operator.
NOTE: This is a candidate for all release branches.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Brian Paul [Tue, 8 May 2012 17:40:28 +0000 (11:40 -0600)]
vbo: add some comments
Brian Paul [Tue, 8 May 2012 15:32:43 +0000 (09:32 -0600)]
mesa: remove needless casts in save_EdgeFlag()
Brian Paul [Tue, 8 May 2012 15:12:35 +0000 (09:12 -0600)]
mesa: minor clean-ups in dlist material code
Brian Paul [Tue, 8 May 2012 15:11:04 +0000 (09:11 -0600)]
mesa: fix error strings in dlist code
Marek Olšák [Mon, 16 Apr 2012 02:56:12 +0000 (04:56 +0200)]
mesa: add gl_context::NewDriverState and use it for vertex arrays
The vbo module recomputes its states if _NEW_ARRAY is set, so it shouldn't use
the same flag to notify the driver. Since we've run out of bits in NewState
and NewState is for core Mesa anyway, we need to find another way.
This patch is the first to start decoupling the state flags meant only
for core Mesa and those only for drivers.
The idea is to have two flag sets:
- gl_context::NewState - used by core Mesa only
- gl_context::NewDriverState - used by drivers only (the flags are defined
by the driver and opaque to core Mesa)
It makes perfect sense to use NewState|=_NEW_ARRAY to notify the vbo module
that the user changed vertex arrays, and the vbo module in turn sets
a driver-specific flag to notify the driver that it should update its vertex
array bindings.
The driver decides which bits of NewDriverState should be set and stores them
in gl_context::DriverFlags. Then, Core Mesa can do this:
ctx->NewDriverState |= ctx->DriverFlags.NewArray;
This patch implements this behavior and adapts st/mesa.
DriverFlags.NewArray is set to ST_NEW_VERTEX_ARRAYS.
Core Mesa only sets NewDriverState. It's the driver's responsibility to read
it whenever it wants and reset it to 0.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Mon, 23 Apr 2012 16:20:56 +0000 (18:20 +0200)]
mesa: move gl_client_array*[] from vbo_draw_func into gl_context
In the future we'd like to treat vertex arrays as a state and
not as a parameter to the draw function. This is the first step
towards that goal. Part of the goal is to avoid array re-validation
for every draw call.
This commit adds:
const struct gl_client_array **gl_context::Array::_DrawArrays.
The pointer is changed in:
* vbo_draw_method
* vbo_rebase_prims - unused by gallium
* vbo_split_prims - unused by gallium
* st_RasterPos
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Mon, 23 Apr 2012 16:11:38 +0000 (18:11 +0200)]
vbo: move vbo_draw_method into vbo_context.h
I'll need vbo_context in that function soon.
Reviewed-by: Brian Paul <brianp@vmware.com>
Vadim Girlin [Mon, 7 May 2012 09:25:08 +0000 (13:25 +0400)]
radeon/llvm: add suport for cube textures
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 09:10:09 +0000 (13:10 +0400)]
radeon/llvm: add support for CUBE ALU instruction
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 09:06:22 +0000 (13:06 +0400)]
radeon/llvm: add support for some ALU instructions
Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG,
I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX,
IMIN, IMAX, UMIN, UMAX
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 09:02:46 +0000 (13:02 +0400)]
radeon/llvm: add missing cases for BREAK/CONTINUE
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 08:50:25 +0000 (12:50 +0400)]
radeon/llvm: add support for AHSR/LSHR/LSHL instructions
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 08:47:47 +0000 (12:47 +0400)]
radeon/llvm: add support for TXQ/TXF/DDX/DDY instructions
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 16:26:32 +0000 (20:26 +0400)]
radeon/llvm: add support for VertexID, InstanceID
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 13:38:01 +0000 (17:38 +0400)]
radeon/llvm: fix live-in handling for inputs
Set the input registers as live-in for entry basic block.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 16:24:13 +0000 (20:24 +0400)]
radeon/llvm: add support for v4i32
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 09:17:00 +0000 (13:17 +0400)]
radeon/llvm: fix ABS_i32 instruction lowering
Swap source operands.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 09:14:58 +0000 (13:14 +0400)]
radeon/llvm: use integer comparison for IF
Replacing "float equal to 1.0f" with "int not equal to 0".
This should help for further optimization of boolean computations.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Mon, 7 May 2012 16:22:29 +0000 (20:22 +0400)]
radeon/llvm: use bitcasts for integers
We're using float as default type, so basically for every instruction that
wants other types for dst/src operands we need to perform the bitcast
to/from default float. Currently bitcast produces no-op MOV instruction,
will be eliminated later.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Tom Stellard [Mon, 7 May 2012 19:04:08 +0000 (15:04 -0400)]
r600g: Fix out of tree builds that use the LLVM backend
https://bugs.freedesktop.org/show_bug.cgi?id=49567
Tom Stellard [Mon, 7 May 2012 17:53:40 +0000 (13:53 -0400)]
radeon/llvm: Remove references to DebugFlag and isCurrentDebugType()
These weren't being used at all and they were causing build failures
when LLVM was built with NDEBUG defined and mesa was not.
https://bugs.freedesktop.org/show_bug.cgi?id=49110
Paul Berry [Thu, 26 Apr 2012 13:35:56 +0000 (06:35 -0700)]
i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets.
In i965 Gen7, Mesa has for a long time used the "depth coordinate
offset X/Y" settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to
render to miplevels other than 0. Unfortunately, this doesn't work,
because these offsets must be aligned to multiples of 8, and miplevels
in the depth buffer are only guaranteed to be aligned to multiples of
4. When the offsets aren't aligned to a multiple of 8, the GPU
sometimes hangs.
As a temporary measure, to avoid GPU hangs, this patch smashes the 3
LSB's of "depth coordinate offset X/Y" to 0. This results in
incorrect rendering to mipmapped depth textures, but that seems like a
reasonable stopgap while we figure out a better solution.
Avoids GPU hangs in piglit test "depthstencil-render-miplevels" at
texture sizes that are not powers of 2.
Reviewed-by: Chad Verace <chad.versace@linux.intel.com>
Paul Berry [Thu, 26 Apr 2012 13:35:56 +0000 (06:35 -0700)]
i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.
In i965 Gen6, Mesa has for a long time used the "depth coordinate
offset X/Y" settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to
render to miplevels other than 0. Unfortunately, this doesn't work,
because these offsets must be aligned to multiples of 8, and miplevels
in the depth buffer are only guaranteed to be aligned to multiples of
4. When the offsets aren't aligned to a multiple of 8, the GPU
sometimes hangs.
As a temporary measure, to avoid GPU hangs, this patch smashes the 3
LSB's of "depth coordinate offset X/Y" to 0. This results in
incorrect rendering to mipmapped depth textures, but that seems like a
reasonable stopgap while we figure out a better solution.
(Note that we have only ever observed this GPU hang on Gen6 when HiZ
is enabled, so another possible stopgap would be to disable HiZ).
Avoids GPU hangs in piglit test "depthstencil-render-miplevels" at
texture sizes that are not powers of 2.
Reviewed-by: Chad Verace <chad.versace@linux.intel.com>
Paul Berry [Sat, 14 Apr 2012 04:50:08 +0000 (21:50 -0700)]
fbo: Only reuse depth/stencil attachments if the parameters match.
When the user attaches a texture to one of the depth/stencil
attachment points (GL_STENCIL_ATTACHMENT or GL_DEPTH_ATTACHMENT), we
check to see if the same texture is also attached to the other
attachment point, and if so, we re-use the existing texture
attachment. This is necessary to ensure that if the user later
queries what is attached to GL_DEPTH_STENCIL_ATTACHMENT, they will not
receive an error.
If, however, the user attaches buffers to the two different attachment
points using different parameters (e.g. a different miplevel), then we
can't re-use the existing texture attachment, because it is pointing
to the wrong part of the texture. This might occur as a transitory
condition if, for example, if the user attached miplevel zero of a
texture to GL_STENCIL_ATTACHMENT and GL_DEPTH_ATTACHMENT, rendered to
it, and then later attempted to attach miplevel one of the same
texture to GL_STENCIL_ATTACHMENT and GL_DEPTH_ATTACHMENT.
This patch causes Mesa to check that GL_STENCIL_ATTACHMENT and
GL_DEPTH_ATTACHMENT use the same attachment parameters before
attempting to share the texture attachment.
On i965 Gen6, fixes piglit tests
"texturing/depthstencil-render-miplevels 1024 depth_stencil_shared"
and "texturing/depthstencil-render-miplevels 1024
stencil_depth_shared".
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Paul Berry [Sun, 15 Apr 2012 17:35:01 +0000 (10:35 -0700)]
i965: Fix mipmap offsets for HiZ and separate stencil buffers.
When rendering to a miplevel other than 0 within a color, depth,
stencil, or HiZ buffer, we need to tell the GPU to render to an offset
within the buffer, so that the data is written into the correct
miplevel. We do this using a coarse offset (in pages), and a fine
adjustment (the so-called "tile_x" and "tile_y" values, which are
measured in pixels).
We have always computed the coarse offset and fine adjustment using
intel_renderbuffer_tile_offsets() function. This worked fine for
color and combined depth/stencil buffers, but failed to work properly
when HiZ and separate stencil were in use. It failed to work because
there is only one set of fine adjustment controls shared by the HiZ,
depth, and stencil buffers, so we need to choose tile_x and tile_y
values that are compatible with the tiling of all three buffers, and
then compute separate coarse offsets for each buffer.
This patch fixes the HiZ and separate stencil case by replacing the
call to intel_renderbuffer_tile_offsets() with calls to two functions:
intel_region_get_tile_masks(), which determines how much of the
adjustment can be performed using offsets and how much can be
performed using tile_x and tile_y, and
intel_region_get_aligned_offset(), which computes the coarse offset.
intel_region_get_tile_offsets() is still used for color renderbuffers,
so to avoid code duplication, I've re-worked it to use
intel_region_get_tile_masks() and intel_region_get_aligned_offset().
On i965 Gen6, fixes piglit tests
"texturing/depthstencil-render-miplevels 1024 X" where X is one of
(depth, depth_and_stencil, depth_stencil_single_binding, depth_x,
depth_x_and_stencil, stencil, stencil_and_depth, stencil_and_depth_x).
On i965 Gen7, the variants of
"texturing/depthstencil-render-miplevels" that contain a stencil
buffer still fail, due to another problem: Gen7 seems to ignore the 3
LSB's of the tile_y adjustment (and possibly also tile_x).
v2: Removed spurious comments. Added assertions to check
preconditions of intel_region_get_aligned_offset().
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chad Versace [Thu, 3 May 2012 23:02:50 +0000 (16:02 -0700)]
intel: Disable ARB_framebuffer_object in ES contexts
This patch removes ARB_framebuffer_object from the GLES1 and GLES2
extension lists in intel_extensions_es.c.
Fixes a crash in the Android browser on Ice Cream Sandwich.
The Android browser crashed because it did the following, which is legal
in GLES2 but not in ARB_framebuffer_object.
glGenFramebuffers(1, &fb);
glBindFramebuffer(GL_FRAMEBUFFER, fb);
// render render render...
glDeleteFramebuffers(1, &fb);
// go do other stuff...
glBindFramebuffer(GL_FRAMEBUFFER, fb);
// This bind unexpectedly failed, and the app panics.
The semantics of glBindFramebuffer specified by ARB_framebuffer_object (a
desktop GL extension) and GLES2 specs are incompatible. The ideal solution
to fix this is to create separate API entry points for glBindFramebuffer,
one for GL and the other for GLES2. But, until that work is complete,
disabling ARB_framebuffer_object in GLES2 contexts safely fixes the problem.
Likewise, the semantics of glBindFramebuffer in ARB_framebuffer_object and
of glBindFramebufferOES in OES_framebuffer_object (a GLES1 extension) are
incompatible. Even though the functions have different names, the semantic
difference still results in a bug because both API calls are implemented
by a single function, _mesa_BindFramebufferEXT, which handles the semantic
difference incorrectly. Again, disabling ARB_framebuffer_object in GLES1
contexts safely fixes this problem.
According to the ARB_framebuffer_object spec, the extension is an
amalgamation of
EXT_framebuffer_object
EXT_framebuffer_blit
EXT_packed_depth_stencil
EXT_framebuffer_multisample
By disabling this extension, however, no functionality is removed from
GLES1 and GLES2 contexts because 1) the first three extensions are
explicitly enabled in Intel's ES extension lists and 2) no functionality
of the last extension is exposed in an ES context.
Note: This is a candidate for the 8.0 branch.
See-also: http://www.mail-archive.com/mesa-dev@lists.freedesktop.org/msg21006.html
CC: Charles Johnson <charles.f.johnson@intel.com>
CC: Sean Kelley <sean.v.kelley@intel.com>
Reviewed-by: Ian Romanick <idr@freedesktop.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Brian Paul [Mon, 7 May 2012 13:30:04 +0000 (07:30 -0600)]
mesa: bump version to 8.1.0 in configs/default
Marcin Slusarz [Mon, 7 May 2012 12:05:35 +0000 (14:05 +0200)]
nv50: handle VP without inputs
Christoph Bumiller [Sat, 5 May 2012 15:57:50 +0000 (17:57 +0200)]
nvc0/ir: allow abs,neg source modifiers with ceil,floor,trunc
Christoph Bumiller [Sat, 5 May 2012 14:35:49 +0000 (16:35 +0200)]
nv50/ir/opt: don't lose saturation in tryCollapseChainedMULs
Christoph Bumiller [Sat, 5 May 2012 11:30:03 +0000 (13:30 +0200)]
nvc0/ir: fix lowering of textureGrad
Christoph Bumiller [Sat, 5 May 2012 11:28:19 +0000 (13:28 +0200)]
nouveau: fix nouveau_scratch_runout_release bo count underflow
Jordan Justen [Tue, 1 May 2012 07:01:08 +0000 (00:01 -0700)]
mesa: Add primitive restart support to glArrayElement
When primitive restart is enabled, and glArrayElement is called
with the restart index value, then call glPrimitiveRestartNV.
NOTE: This is a candidate for the 8.0 branch.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul<brianp@vmware.com>
Baldo Davide [Sat, 5 May 2012 03:50:19 +0000 (04:50 +0100)]
auxiliary/os: Add missing signal.h include.
The signal.h include was missed in the commit
bc16c73407d11bb6702cf7de9925bfaeb80a5272 which leads to broken
compilations under Linux.
Signed-off-by: José Fonseca <jose.r.fonseca@gmail.com>
Kenneth Graunke [Mon, 5 Mar 2012 21:54:29 +0000 (13:54 -0800)]
intel: Remove pointless software fallback for glBitmap on Gen6.
We already have a meta path below that works just fine; no apparent
regressions in oglconform.
NOTE: This is a candidate for the 8.0 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46834
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Tue, 24 Apr 2012 00:24:13 +0000 (17:24 -0700)]
glsl: Fix regression in function out-parameter lvalue detection.
When doing the var->assigned change in
f2475ca424f7e001be50f64dafa5700f6603d684, I overzealously indented the
second block of code into the "if (var)" test. Revert these blocks to
the way they were before, just taking advantage of "var" to avoid
re-calling variable_referenced().
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49066
Eric Anholt [Tue, 24 Apr 2012 00:12:04 +0000 (17:12 -0700)]
mesa: Prevent buffer underrun when handling MESA_GL_EXTENSION_OVERRIDE.
Eric Anholt [Mon, 23 Apr 2012 23:48:09 +0000 (16:48 -0700)]
i965/fs: Fix regression in comparison handling from ANDs change.
I had fixed up the logic ops for delayed ANDing, but not equality
comparisons on bools. Fixes new piglit fs-bool-less-compare-true.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48629
Eric Anholt [Mon, 23 Apr 2012 23:10:12 +0000 (16:10 -0700)]
glsl: Don't consider unused FS out variables as being statically assigned.
I only considered var->assigned for FragColor and FragData, but
ignored when it was false for out vars. Fixes piglit
write-gl_FragColor-and-not-user-output.frag
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49068
Eric Anholt [Mon, 23 Apr 2012 16:46:15 +0000 (09:46 -0700)]
i965: Add a comment about the state flag for sRGBEnabled.
I thought this might be _NEW_COLOR, but it isn't.
Eric Anholt [Mon, 23 Apr 2012 21:14:11 +0000 (14:14 -0700)]
intel: Return success when asked to allocate a 0-width/height renderbuffer.
It seems silly that GL lets you allocate these given that they're
framebuffer attachment incomplete, but the webgl conformance tests
actually go looking to see if the getters on 0-width/height
depth/stencil renderbuffers return good values. By failing out here,
they all got smashed to 0, which turned out to be correct for all the
getters they tested except for GL_RENDERBUFFER_INTERNAL_FORMAT. Now,
by succeeding but not making a miptree, that one also returns the
expected value.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 25 Apr 2012 21:59:25 +0000 (14:59 -0700)]
glsl: Always copy the index when cloning a variable.
The index is also used for GL_ARB_blend_func_extended. Cloning in
i965 was dropping a non-ARB_explicit_attrib_location index.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Eric Anholt [Wed, 25 Apr 2012 20:19:28 +0000 (13:19 -0700)]
i965: Add support for GL_ARB_draw_buffers_blend.
Tested with piglit fbo-draw-buffers-blend and intel oglconform.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Christoph Bumiller [Fri, 4 May 2012 15:40:33 +0000 (17:40 +0200)]
nv50: fix typo causing NULL-deref in nv50_resource_resolve
Introduced in
b328949a37fee7b0f68ed3e068ffc4426c083042.
Christoph Bumiller [Fri, 4 May 2012 16:00:40 +0000 (18:00 +0200)]
nv50/ir: move expansion of IMUL to later stage and handle memory operands
Christoph Bumiller [Thu, 3 May 2012 10:50:08 +0000 (12:50 +0200)]
nv50: implement stream output
Christoph Bumiller [Tue, 24 Apr 2012 21:21:41 +0000 (23:21 +0200)]
nv50: enable array textures
Brian Paul [Mon, 30 Apr 2012 22:01:08 +0000 (16:01 -0600)]
svga: specify 4-byte aligned vertex elements
We haven't found a case where this is needed, but it would be prudent
for some hosts, per Jose.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 3 May 2012 23:00:37 +0000 (17:00 -0600)]
gallivm: fix comment typo
Brian Paul [Tue, 1 May 2012 21:49:31 +0000 (15:49 -0600)]
docs: another viewperf bug
Brian Paul [Tue, 1 May 2012 20:46:04 +0000 (14:46 -0600)]
mesa: do more teximage error checking for generic compressed formats
When glTexImage or glCopyTexImage is called with internalFormat being a
generic compressed format (like GL_COMPRESSED_RGB) we need to do the same
error checks as for specific compressed formats. In particular, check if
the texture target is compatible with the format. None of the texture
compression formats we support so far work with GL_TEXTURE_1D, for example.
See also https://bugs.freedesktop.org/show_bug.cgi?id=49124
NOTE: This is a candidate for the 8.0 branch.
Vinson Lee [Tue, 1 May 2012 01:57:38 +0000 (18:57 -0700)]
scons: Do not build EGL on Solaris.
The current EGL headers do not support Solaris.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Jeremy Huddleston [Sun, 29 Apr 2012 06:19:42 +0000 (23:19 -0700)]
darwin: Use ASL for logging
Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
Jeremy Huddleston [Sat, 28 Apr 2012 23:50:00 +0000 (16:50 -0700)]
darwin: Make reported errors more user-friendly
Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
Jeremy Huddleston [Sun, 29 Apr 2012 07:27:03 +0000 (00:27 -0700)]
darwin: Fix an error message
Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
Robert Hooker [Wed, 2 May 2012 23:04:57 +0000 (19:04 -0400)]
egl_dri2: Fix out of tree builds with the wayland backend enabled
Otherwise it fails like so:
CC egl_dri2.lo
In file included from egl_dri2.h:40:0,
from egl_dri2.c:42:
../../../../../../src/egl/wayland/wayland-drm/wayland-drm.h:8:41:
fatal error: wayland-drm-server-protocol.h: No such file or directory
compilation terminated.
Kristian Høgsberg [Wed, 2 May 2012 19:30:13 +0000 (15:30 -0400)]
gbm: Add gbm_bo_write entry point
This new gbm entry point allows writing data into a gbm bo. The bo has
to be created with the GBM_BO_USE_WRITE flag, and it's only required to
work for GBM_BO_USE_CURSOR_64X64 bos.
The gbm API is designed to be the glue layer between EGL and KMS, but there
was never a mechanism initialize a buffer suitable for use with KMS
hw cursors. The hw cursor bo is typically not compatible with anything EGL
can render to, and thus there's no way to get data into such a bo.
gbm_bo_write() fills that gap while staying out of the efficient
cpu->gpu pixel transfer business.
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Tom Stellard [Mon, 30 Apr 2012 14:18:41 +0000 (10:18 -0400)]
r600g/llvm: Mask write of pred_inst in llvm_if()
Tom Stellard [Fri, 27 Apr 2012 20:22:58 +0000 (16:22 -0400)]
r600g/llvm: Lower ULT A, B, C to SETGT_UINT A, C, B
Tom Stellard [Fri, 27 Apr 2012 19:26:30 +0000 (15:26 -0400)]
r600g: Print integer values of literal constants in shader dumps
Tom Stellard [Fri, 27 Apr 2012 19:15:19 +0000 (15:15 -0400)]
r600g: Add support for reading BREAK_LOGICALZ_i32 from bytestream