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Matthew Simpson [Wed, 27 Apr 2016 18:21:36 +0000 (18:21 +0000)]
[LV] Reallow positive-stride interleaved load groups with gaps
We previously disallowed interleaved load groups that may cause us to
speculatively access memory out-of-bounds (r261331). We did this by ensuring
each load group had an access corresponding to the first and last member.
Instead of bailing out for these interleaved groups, this patch enables us to
peel off the last vector iteration, ensuring that we execute at least one
iteration of the scalar remainder loop. This solution was proposed in the
review of the previous patch.
Differential Revision: http://reviews.llvm.org/D19487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267751
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Arch D. Robison [Wed, 27 Apr 2016 17:46:25 +0000 (17:46 +0000)]
[SLPVectorizer] Refactor where MinVecRegSize and MaxVecRegSize live.
This is the first of two commits for extending SLP Vectorizer to deal with aggregates.
This commit merely refactors existing logic.
http://reviews.llvm.org/D14185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267748
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Gerolf Hoflehner [Wed, 27 Apr 2016 17:27:16 +0000 (17:27 +0000)]
[DAGCombiner] Follow coding convention for function name (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267745
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Marcin Koscielnicki [Wed, 27 Apr 2016 17:21:49 +0000 (17:21 +0000)]
[Mips] Add support for llvm.thread.pointer intrinsic.
This will be used to implement __builtin_thread_pointer in clang.
Differential Revision: http://reviews.llvm.org/D19569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267743
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Gerolf Hoflehner [Wed, 27 Apr 2016 17:19:54 +0000 (17:19 +0000)]
[InstCombine] Sharpended test case in pr21210.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267742
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Reid Kleckner [Wed, 27 Apr 2016 16:46:33 +0000 (16:46 +0000)]
Silence a -Wdangling-else
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267737
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Matthew Simpson [Wed, 27 Apr 2016 16:25:04 +0000 (16:25 +0000)]
Add parentheses to silence buildbot warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267734
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Artem Tamazov [Wed, 27 Apr 2016 16:20:23 +0000 (16:20 +0000)]
[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.
Added support of TTMP quads.
Reworked M0 exclusion machinery for SMRD and similar instructions
to enable usage of TTMP registers in those instructions as destinations.
Tests added.
Differential Revision: http://reviews.llvm.org/D19342
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267733
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Reid Kleckner [Wed, 27 Apr 2016 16:10:29 +0000 (16:10 +0000)]
[PDB] Fix function names for private symbols in PDBs
Summary:
llvm-symbolizer wants to get linkage names of functions for historical
reasons. Linkage names are only recorded in the PDB for public symbols,
and the linkage name is apparently stored separately in some "public
symbol" record. We had a workaround in PDBContext which would look for
such symbols when the user requested linkage names.
However, when given an address that was truly in a private function and
public funciton, we would accidentally find nearby public symbols and
return those function names. The fix is to look for both function
symbols and public symbols and only prefer the public symbol name if the
addresses of the symbols agree.
Fixes PR27492
Reviewers: zturner
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D19571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267732
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Nicolai Haehnle [Wed, 27 Apr 2016 15:46:01 +0000 (15:46 +0000)]
AMDGPU/SI: Add llvm.amdgcn.s.waitcnt.all intrinsic
Summary:
So it appears that to guarantee some of the ordering requirements of a GLSL
memoryBarrier() executed in the shader, we need to emit an s_waitcnt.
(We can't use an s_barrier, because memoryBarrier() may appear anywhere in
the shader, in particular it may appear in non-uniform control flow.)
Reviewers: arsenm, mareko, tstellarAMD
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D19203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267729
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Matthew Simpson [Wed, 27 Apr 2016 15:20:21 +0000 (15:20 +0000)]
[TTI] Add hook for vector extract with extension
This change adds a new hook for estimating the cost of vector extracts followed
by zero- and sign-extensions. The motivating example for this change is the
SMOV and UMOV instructions on AArch64. These instructions move data from vector
to general purpose registers while performing the corresponding extension
(sign-extend for SMOV and zero-extend for UMOV) at the same time. For these
operations, TargetTransformInfo can assume the extensions are free and only
report the cost of the vector extract. The SLP vectorizer has been updated to
make use of the new hook.
Differential Revision: http://reviews.llvm.org/D18523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267725
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Artem Tamazov [Wed, 27 Apr 2016 15:17:03 +0000 (15:17 +0000)]
[AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.
Possibility to specify code of hardware register kept.
Disassemble to symbolic name, if name is known.
Tests updated/added.
Differential Revision: http://reviews.llvm.org/D19335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267724
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Nico Weber [Wed, 27 Apr 2016 15:16:54 +0000 (15:16 +0000)]
Revert r267649, it caused PR27539.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267723
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Kristof Beyls [Wed, 27 Apr 2016 15:03:09 +0000 (15:03 +0000)]
Remove size 1 from check as that isn't part of what the test is meant to be testing.
This test also runs on e.g. ARM-native builds when the X86 backend is also
built. This test produces code for the default instruction set, even though it
is in a "X86" sub-directory. Given that this test doesn't seem to be testing
anything architecture-specific, it seems it's best to adapt the check to not
check for an architecture-dependent value (the size of the function), rather
than hard-code the test to target x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267722
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Teresa Johnson [Wed, 27 Apr 2016 14:19:38 +0000 (14:19 +0000)]
[ThinLTO] Refine fix to avoid renaming of uses in inline assembly.
Summary:
Refine the workaround from r266877 that attempts to prevent
renaming of locals in inline assembly, so that in addition to looking
for a llvm.used local value, that there is at least one inline assembly
call in the module. Otherwise, debug functions added to the llvm.used
can block importing/exporting unnecessarily.
Reviewers: joker.eph
Subscribers: llvm-commits, joker.eph
Differential Revision: http://reviews.llvm.org/D19573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267717
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Teresa Johnson [Wed, 27 Apr 2016 13:28:35 +0000 (13:28 +0000)]
[ThinLTO] Use valueid instead of bitcode offsets in combined index file
Summary:
With the removal of support for lazy parsing of combined index summary
records (e.g. r267344), we no longer need to include the summary record
bitcode offset in the VST entries for definitions. Change the combined
index format to be similar to the per-module index format in using value
ids to cross-reference from the summary record to the VST entry (rather
than the summary record bitcode offset to cross-reference in the other
direction).
The visible changes are:
1) Add the value id to the combined summary records
2) Remove the summary offset from the combined VST records, which has
the following effects:
- No longer need the VST_CODE_COMBINED_GVDEFENTRY record, as all
combined index VST entries now only contain the value id and
corresponding GUID.
- No longer have duplicate VST entries in the case where there are
multiple definitions of a symbol (e.g. weak/linkonce), as they all
have the same value id and GUID.
An implication of #2 above is that in order to hook up an alias to the
correct aliasee based on the value id of the aliasee recorded in the
combined index alias record, we need to scan the entries in the index
for that GUID to find the one from the same module (i.e. the case where
there are multiple entries for the aliasee). But the reader no longer
has to maintain a special map to hook up the alias/aliasee.
Reviewers: joker.eph
Subscribers: joker.eph, llvm-commits
Differential Revision: http://reviews.llvm.org/D19481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267712
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Artur Pilipenko [Wed, 27 Apr 2016 12:51:01 +0000 (12:51 +0000)]
NFC. Introduce Value::getPointerDerferecnceableBytes
Extract a part of isDereferenceableAndAlignedPointer functionality to Value::getPointerDerferecnceableBytes. Currently it's a NFC, but in future I'm going to accumulate all the logic about value dereferenceability in this function similarly to Value::getPointerAlignment function (D16144).
Reviewed By: reames
Differential Revision: http://reviews.llvm.org/D17572
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267708
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Simon Pilgrim [Wed, 27 Apr 2016 12:04:44 +0000 (12:04 +0000)]
[InstCombine][SSE] Regenerated vector shift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267699
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Zlatko Buljan [Wed, 27 Apr 2016 11:31:44 +0000 (11:31 +0000)]
[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions
Differential Revision: http://reviews.llvm.org/D16676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267694
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Zlatko Buljan [Wed, 27 Apr 2016 11:02:23 +0000 (11:02 +0000)]
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions
Differential Revision: http://reviews.llvm.org/D17989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267693
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Artur Pilipenko [Wed, 27 Apr 2016 11:00:48 +0000 (11:00 +0000)]
isSafeToLoadUnconditionally support queries without a context
This is required to use this function from isSafeToSpeculativelyExecute
Reviewed By: hfinkel
Differential Revision: http://reviews.llvm.org/D16231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267692
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Artur Pilipenko [Wed, 27 Apr 2016 10:42:29 +0000 (10:42 +0000)]
Use DL preferred alignment for alloca in Value::getPointerAlignment
Teach Value::getPointerAlignment that allocas with no explicit alignment are aligned to preferred alignment of the allocated type.
Reviewed By: hfinkel
Differential Revision: http://reviews.llvm.org/D17569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267689
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Simon Pilgrim [Wed, 27 Apr 2016 09:53:09 +0000 (09:53 +0000)]
[InstCombine][SSE] Added DemandedBits tests for MOVMSK instructions
MOVMSK zeros the upper bits of the gpr - we should be able to use this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267686
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Adam Nemet [Wed, 27 Apr 2016 05:59:51 +0000 (05:59 +0000)]
Fixed sphinx warning from r267672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267675
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Adam Nemet [Wed, 27 Apr 2016 05:28:18 +0000 (05:28 +0000)]
[LoopDist] Add llvm.loop.distribute.enable loop metadata
Summary:
D19403 adds a new pragma for loop distribution. This change adds
support for the corresponding metadata that the pragma is translated to
by the FE.
As part of this I had to rethink the flag -enable-loop-distribute. My
goal was to be backward compatible with the existing behavior:
A1. pass is off by default from the optimization pipeline
unless -enable-loop-distribute is specified
A2. pass is on when invoked directly from opt (e.g. for unit-testing)
The new pragma/metadata overrides these defaults so the new behavior is:
B1. A1 + enable distribution for individual loop with the pragma/metadata
B2. A2 + disable distribution for individual loop with the pragma/metadata
The default value whether the pass is on or off comes from the initiator
of the pass. From the PassManagerBuilder the default is off, from opt
it's on.
I moved -enable-loop-distribute under the pass. If the flag is
specified it overrides the default from above.
Then the pragma/metadata can further modifies this per loop.
As a side-effect, we can now also use -enable-loop-distribute=0 from opt
to emulate the default from the optimization pipeline. So to be precise
this is the new behavior:
C1. pass is off by default from the optimization pipeline
unless -enable-loop-distribute or the pragma/metadata enables it
C2. pass is on when invoked directly from opt
unless -enable-loop-distribute=0 or the pragma/metadata disables it
Reviewers: hfinkel
Subscribers: joker.eph, mzolotukhin, llvm-commits
Differential Revision: http://reviews.llvm.org/D19431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267672
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Vaivaswatha Nagaraj [Wed, 27 Apr 2016 05:25:09 +0000 (05:25 +0000)]
[Cloning] cloneLoopWithPreheader(): add assert to ensure no sub-loops
Summary:
cloneLoopWithPreheader() does not update LoopInfo for sub-loop of
the original loop being cloned. Add assert to ensure no sub-loops for loop being cloned.
Reviewers: anemet, ashutosh.nema, hfinkel
Subscribers: mzolotukhin, llvm-commits
Differential Revision: http://reviews.llvm.org/D15922
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267671
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Craig Topper [Wed, 27 Apr 2016 05:17:00 +0000 (05:17 +0000)]
[Support][X86] Add a few more Intel model numbers to getHostCPUName for airmont and knl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267670
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Craig Topper [Wed, 27 Apr 2016 05:16:58 +0000 (05:16 +0000)]
[Support][X86] Change the case values in the Intel family 6 code to hex so its easier to compare with Intel's docs. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267669
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Mehdi Amini [Wed, 27 Apr 2016 05:11:44 +0000 (05:11 +0000)]
Revert "Support "preserving" the summary information when using setModule() API in LTOCodeGenerator"
This reverts commit r267665.
ASAN shows that there is a use of undefined value.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267668
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Craig Topper [Wed, 27 Apr 2016 04:40:03 +0000 (04:40 +0000)]
[Support][X86] Add a couple more Broadwell CPU models numbers to getHostCPUName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267666
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Mehdi Amini [Wed, 27 Apr 2016 04:24:10 +0000 (04:24 +0000)]
Support "preserving" the summary information when using setModule() API in LTOCodeGenerator
Another attempt at r267655...
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267665
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Mehdi Amini [Wed, 27 Apr 2016 03:34:28 +0000 (03:34 +0000)]
Revert "Support "preserving" the summary information when using setModule() API in LTOCodeGenerator"
This reverts commit r267657, r267656, and r267655.
The test does not pass on multiple bots, I'm unsure why yet but let's unbreak them.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267664
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Evgeny Stupachenko [Wed, 27 Apr 2016 03:04:54 +0000 (03:04 +0000)]
The patch fixes PR27392.
Summary:
It is incorrect to compare TripCount (which is BECount + 1)
with extraiters (or Count) to check if we should enter unrolled
loop or not, because TripCount can potentially overflow
(when BECount is max unsigned integer).
While comparing BECount with (Count - 1) is overflow safe and
therefore correct.
Reviewer: hfinkel
Differential Revision: http://reviews.llvm.org/D19256
From: Evgeny Stupachenko <evstupac@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267662
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Philip Reames [Wed, 27 Apr 2016 03:03:15 +0000 (03:03 +0000)]
[LVI] Delete stale and misleading comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267661
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Chuang-Yu Cheng [Wed, 27 Apr 2016 02:59:28 +0000 (02:59 +0000)]
[ppc64] fix bug in prologue that mfocrf's cr operand should be explict state instead of implicit
This fixes PR27414
Reviewers: kbarton mgrang tjablin
http://reviews.llvm.org/D19255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267660
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Ahmed Bougacha [Wed, 27 Apr 2016 01:51:38 +0000 (01:51 +0000)]
[X86] Set AddPristinesAndCSRs to FixupBW LivePhysRegs. NFC.
We run after PEI, so we need to AddPristinesAndCSRs.
In practice, that makes no difference here, because we only ask about
liveness of super-registers of defined GR8/GR16 registers, so they
can't be pristine. Still, it's the correct thing to do.
Thanks to Quentin for noticing!
Follow-up to r267495.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267658
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Mehdi Amini [Wed, 27 Apr 2016 01:49:11 +0000 (01:49 +0000)]
Fix the test from r267656: Support "preserving" the summary information when using setModule() API in LTOCodeGenerator
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267657
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Mehdi Amini [Wed, 27 Apr 2016 01:47:46 +0000 (01:47 +0000)]
Add a test for r267655: Support "preserving" the summary information when using setModule() API in LTOCodeGenerator
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267656
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Mehdi Amini [Wed, 27 Apr 2016 01:46:48 +0000 (01:46 +0000)]
Support "preserving" the summary information when using setModule() API in LTOCodeGenerator
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267655
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Sanjoy Das [Wed, 27 Apr 2016 01:44:31 +0000 (01:44 +0000)]
Fix typo in comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267653
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Ahmed Bougacha [Wed, 27 Apr 2016 01:35:29 +0000 (01:35 +0000)]
[X86] Don't assume that MMX extractelts are from index 0.
It's probably the case for all 3 MMX users out there, but with
hand-crafted IR, you can trigger selection failures. Fix that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267652
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Ahmed Bougacha [Wed, 27 Apr 2016 01:35:25 +0000 (01:35 +0000)]
[X86] Re-enable MMX i32 extractelt combine.
This effectively adds back the extractelt combine removed by r262358:
the direct case can still occur (because x86_mmx is special, see
r262446), but it's the indirect case that's now superseded by the
generic combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267651
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Cong Hou [Wed, 27 Apr 2016 01:29:18 +0000 (01:29 +0000)]
Detects the SAD pattern on X86 so that much better code will be emitted once the pattern is matched.
Differential revision: http://reviews.llvm.org/D14840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267649
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Philip Reames [Wed, 27 Apr 2016 01:02:25 +0000 (01:02 +0000)]
[LVI] Add a comment explaining a subtle piece of code
Or at least, I didn't understand the implications the first several times I read it it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267648
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Adam Nemet [Wed, 27 Apr 2016 00:52:48 +0000 (00:52 +0000)]
[Docs] Try to clarify the concept of domains for noalias scope
Summary:
This tries to anchor down the concept of domains a bit better. I had
trouble initially relating this to anything. Also talking to David
Majnemer on IRC suggested that I wasn't the only one.
Reviewers: hfinkel
Subscribers: llvm-commits, majnemer
Differential Revision: http://reviews.llvm.org/D18799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267647
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Mehdi Amini [Wed, 27 Apr 2016 00:32:13 +0000 (00:32 +0000)]
ThinLTO: do not promote GlobalVariable that have a specific section.
Differential Revision: http://reviews.llvm.org/D18298
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267646
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Matt Arsenault [Wed, 27 Apr 2016 00:32:09 +0000 (00:32 +0000)]
SLSR: Use UnknownAddressSpace instead of 0 for pure arithmetic.
In the case where isLegalAddressingMode is used for cases
not related to addressing modes, such as pure adds and muls,
it should not be using address space 0. LSR already passes -1
as the address space in these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267645
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Mehdi Amini [Wed, 27 Apr 2016 00:32:02 +0000 (00:32 +0000)]
LTOCodeGenerator: turns linkonce(_odr) into weak_(odr) when present "MustPreserve" set
Summary:
If the linker requested to preserve a linkonce function, we should
honor this even if we drop all uses.
Reviewers: dexonsmith
Subscribers: llvm-commits, joker.eph
Differential Revision: http://reviews.llvm.org/D19527
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267644
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Adam Nemet [Wed, 27 Apr 2016 00:31:03 +0000 (00:31 +0000)]
[LoopDist] Split main class. NFC
This splits out the per-loop functionality from the Pass class.
With this the fact whether the loop is forced-distribute with the new
metadata/pragma can be cached in the per-loop class rather than passed
around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267643
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Philip Reames [Wed, 27 Apr 2016 00:30:55 +0000 (00:30 +0000)]
[LVI] Reduce compile time by lazily scanning blocks if needed
When encountering a non-local pointer, LVI would eagerly scan the block for dereferences of the given object to prove the pointer to be non null. That's all well and good, but *then* we'd go recurse through our input blocks. As a result, we could end up scanning each and every block we traverse, even if the final definition was obviously non null or we found a constant value somewhere up the chain. The previous code papered over this by using the isKnownNonNull routine from value tracking. This made the duplication less painful in the common case.
Instead, we know do the block scan only *after* we've gotten the recursive results back. This lets us stop scanning individual blocks as soon as we've determined it to be non-null in any predecessor block and use our usual merge rules to propagate that information cheaply through successor blocks. For a pointer which can be found non-null, this does strictly less work and sometimes substaintially so.
Note that the case where we *can't* prove something non-null is still the really expensive case. We end up scanning each and every block looking for a dereference and never end up finding one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267642
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Quentin Colombet [Wed, 27 Apr 2016 00:16:29 +0000 (00:16 +0000)]
[MachineInstrBundle] Actually set the PartialDeadDef flag only when the register
is defined!
The users were checking the proper thing (Defined + PartialDeadDef), but the
information may have been wrong for other use cases, so fix that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267641
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Quentin Colombet [Tue, 26 Apr 2016 23:55:41 +0000 (23:55 +0000)]
[MachineInstrBundle] Update the comment for PhysRegInfo::
DeadDef.
I missed read the comment when I commited r267621 and thought the
comment did not need update. Matthias kindly proved me wrong.
Fixing that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267638
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Andrew Kaylor [Tue, 26 Apr 2016 23:49:41 +0000 (23:49 +0000)]
Add optimization bisect opt-in calls for SystemZ passes
Differential Revision: http://reviews.llvm.org/D19562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267636
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Andrew Kaylor [Tue, 26 Apr 2016 23:44:31 +0000 (23:44 +0000)]
Add optimization bisect opt-in calls for NVPTX passes
Differential Revision: http://reviews.llvm.org/D19518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267635
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Quentin Colombet [Tue, 26 Apr 2016 23:44:14 +0000 (23:44 +0000)]
[X86] Make sure it is safe to clobber EFLAGS, if need be, when choosing
the prologue.
Do not use basic blocks that have EFLAGS live-in as prologue if we need
to realign the stack. Realigning the stack uses AND instruction and this
clobbers EFLAGS.
An other alternative would have been to save and restore EFLAGS around
the stack realignment code, but this is likely inefficient.
Fixes PR27531.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267634
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Justin Bogner [Tue, 26 Apr 2016 23:39:29 +0000 (23:39 +0000)]
PM: Port Reassociate to the new pass manager
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267631
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Mitch Bodart [Tue, 26 Apr 2016 23:36:38 +0000 (23:36 +0000)]
[X86] Replace -mcpu with -mattr in several tests
Differential Revision: http://reviews.llvm.org/D19568
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267629
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Justin Bogner [Tue, 26 Apr 2016 23:32:00 +0000 (23:32 +0000)]
Reassociate: Convert another functor into a lambda. NFC
Also move the explanatory comment with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267628
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Philip Reames [Tue, 26 Apr 2016 23:27:33 +0000 (23:27 +0000)]
[LVI] Cut short search if we know we can't return a useful result
Previously we were recursing on our operands for unary and binary operators regardless of whether we knew how to reason about the operator in question. This has the effect of doing a potentially large amount of work, only to throw it away. By checking whether the operation is one LVI can handle, we can cut short the search and return the (overdefined) answer more quickly. The quality of the results produced should not change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267626
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Sanjay Patel [Tue, 26 Apr 2016 23:15:48 +0000 (23:15 +0000)]
[SimplifyCFG] propagate branch metadata when creating select
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267624
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Quentin Colombet [Tue, 26 Apr 2016 23:14:32 +0000 (23:14 +0000)]
[X86] Teach the expansion of copy instructions how to do proper liveness.
When the simple analysis provided by MachineBasicBlock::computeRegisterLiveness
fails, fall back on the LivePhysReg utility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267623
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Quentin Colombet [Tue, 26 Apr 2016 23:14:29 +0000 (23:14 +0000)]
[MachineBasicBlock] Take advantage of the partially dead information.
Thanks to that information we wouldn't lie on a register being live whereas it
is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267622
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Quentin Colombet [Tue, 26 Apr 2016 23:14:24 +0000 (23:14 +0000)]
[MachineInstrBundle] Improvement the recognition of dead definitions.
Now, it is possible to know that partial definitions are dead definitions and
recognize that clobbered registers are also dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267621
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Philip Reames [Tue, 26 Apr 2016 23:10:35 +0000 (23:10 +0000)]
[LVI] Apply transfer rule for overdefine inputs for binary operators
As pointed out by John Regehr over in http://reviews.llvm.org/D19485, LVI was being incredibly stupid about applying its transfer rules. Rather than gathering local facts from the expression itself, it was simply giving up entirely if one of the inputs was overdefined. This greatly impacts the precision of the overall analysis and makes it far more fragile as well.
This patch builds on 267609 which did the same thing for unary casts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267620
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Jingyue Wu [Tue, 26 Apr 2016 22:59:25 +0000 (22:59 +0000)]
[NVPTX] Fix some usages of CodeGenOpt::None.
NVPTXLowerKernelArgs is required for correctness, so it should not be guarded
by CodeGenOpt::None.
NVPTXPeephole is optimization only, so it should be skipped when
CodeGenOpt::None.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267619
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Philip Reames [Tue, 26 Apr 2016 22:52:30 +0000 (22:52 +0000)]
[LVI] A better fix for the assertion error introduced by 267609
Essentially, I was using the wrong size function. For types which were sized, but not primitive, I wasn't getting a useful size for the operand and failed an assert. I fixed this, and also added a guard that the input is a sized type. Test case is for the original mistake. I'm not sure how to actually exercise the sized type check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267618
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Philip Reames [Tue, 26 Apr 2016 22:31:53 +0000 (22:31 +0000)]
[LVI] Speculative fix for assertion seen in clang bots
I'll clean this up and add a test case shortly. I want to make sure this does actually fix the bots; if not, I'll revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267617
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Sanjay Patel [Tue, 26 Apr 2016 22:23:38 +0000 (22:23 +0000)]
[LowerExpectIntrinsic] make default likely/unlikely ratio bigger
We need the default ratio to be sufficiently large that it triggers transforms
based on block frequency info (BFI) and plays well with the recently introduced
BranchProbability used by CGP.
Differential Revision: http://reviews.llvm.org/D19435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267615
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Justin Bogner [Tue, 26 Apr 2016 22:22:18 +0000 (22:22 +0000)]
Reassociate: Simplify using lambdas. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267614
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Philip Reames [Tue, 26 Apr 2016 21:48:16 +0000 (21:48 +0000)]
[LVI] Infer local facts from unary expressions
As pointed out by John Regehr over in http://reviews.llvm.org/D19485, LVI was being incredibly stupid about applying its transfer rules. Rather than gathering local facts from the expression itself, it was simply giving up entirely if one of the inputs was overdefined. This greatly impacts the precision of the overall analysis and makes it far more fragile as well.
This patch implements only the unary operation case. Once this is in, I'll implement the same for the binary operations.
Differential Revision: http://reviews.llvm.org/D19492
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267609
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Andrew Kaylor [Tue, 26 Apr 2016 21:44:24 +0000 (21:44 +0000)]
Optimization bisect support in X86-specific passes
Differential Revision: http://reviews.llvm.org/D19439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267608
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Ahmed Bougacha [Tue, 26 Apr 2016 21:15:30 +0000 (21:15 +0000)]
[CodeGen] Add getBuildVector and getSplatBuildVector helpers. NFCI.
Differential Revision: http://reviews.llvm.org/D17176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267606
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David Majnemer [Tue, 26 Apr 2016 21:04:47 +0000 (21:04 +0000)]
Revert "[SimplifyLibCalls] sprintf doesn't copy null bytes"
The destination buffer that sprintf uses is restrict qualified, we do
not need to worry about derived pointers referenced via format
specifiers.
This reverts commit r267580.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267605
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Nico Weber [Tue, 26 Apr 2016 20:32:51 +0000 (20:32 +0000)]
Try to get ResponseFile.ll passing on Windows after r267556.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267599
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Zachary Turner [Tue, 26 Apr 2016 20:32:35 +0000 (20:32 +0000)]
Remove more unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267598
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Elena Demikhovsky [Tue, 26 Apr 2016 20:18:04 +0000 (20:18 +0000)]
Masked Store in Loop Vectorizer - bugfix
Fixed a bug in loop vectorization with conditional store.
Differential Revision: http://reviews.llvm.org/D19532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267597
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Justin Bogner [Tue, 26 Apr 2016 20:15:52 +0000 (20:15 +0000)]
PM: Port Internalize to the new pass manager
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267596
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Zachary Turner [Tue, 26 Apr 2016 19:48:18 +0000 (19:48 +0000)]
[llvm-pdbdump] Fix version reading on big endian systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267595
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Andrew Kaylor [Tue, 26 Apr 2016 19:46:28 +0000 (19:46 +0000)]
Add optimization bisect opt-in calls for Hexagon passes
Differential Revision: http://reviews.llvm.org/D19509
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267593
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Zachary Turner [Tue, 26 Apr 2016 19:24:10 +0000 (19:24 +0000)]
Fix warnings and -Werror build on clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267589
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Zachary Turner [Tue, 26 Apr 2016 18:42:34 +0000 (18:42 +0000)]
Parse and dump PDB DBI Stream Header Information
The DBI stream contains a lot of bookkeeping information for other
streams. In particular it contains information about section contributions
and linked modules. This patch is a first attempt at parsing some of the
information out of the DBI stream. It currently only parses and dumps the
headers of the DBI stream, so none of the module data or section
contribution data is pulled out.
This is just a proof of concept that we understand the basic properties of
the DBI stream's metadata, and followup patches will try to extract more
detailed information out.
Differential Revision: http://reviews.llvm.org/D19500
Reviewed By: majnemer, ruiu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267585
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Krzysztof Parzyszek [Tue, 26 Apr 2016 18:36:34 +0000 (18:36 +0000)]
[Tail duplication] Handle source registers with subregisters
When a block is tail-duplicated, the PHI nodes from that block are
replaced with appropriate COPY instructions. When those PHI nodes
contained use operands with subregisters, the subregisters were
dropped from the COPY instructions, resulting in incorrect code.
Keep track of the subregister information and use this information
when remapping instructions from the duplicated block.
Differential Revision: http://reviews.llvm.org/D19337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267583
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Tim Northover [Tue, 26 Apr 2016 18:29:16 +0000 (18:29 +0000)]
Reapply: "ARM: put correct symbol index on indirect pointers in __thread_ptr.""
A latent bug in llvm-objdump used the wrong format specifier on 32-bit
targets, causing the test to fail. This fixes the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267582
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Justin Bogner [Tue, 26 Apr 2016 18:25:30 +0000 (18:25 +0000)]
Internalize: More consistent file header and include guards. NFC
Match the style here to the other headers in Transforms/IPO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267581
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David Majnemer [Tue, 26 Apr 2016 18:16:49 +0000 (18:16 +0000)]
[SimplifyLibCalls] sprintf doesn't copy null bytes
sprintf doesn't read or copy the terminating null byte from it's string
operands. sprintf will append it's own after processing all of the
format specifiers.
This fixes PR27526.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267580
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Manman Ren [Tue, 26 Apr 2016 18:08:06 +0000 (18:08 +0000)]
Swift Calling Convention: use %RAX for sret.
We don't need to copy the sret argument into %rax upon return.
rdar://
25671494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267579
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Saleem Abdulrasool [Tue, 26 Apr 2016 17:54:21 +0000 (17:54 +0000)]
tests: tweak MIR for ARM tests to correct MI issues
The Machine Instruction Verifier flagged some issues in the serialized MIR.
Adjust the input to correct them.
Fixes the remaining portion of PR27480.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267578
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Saleem Abdulrasool [Tue, 26 Apr 2016 17:54:16 +0000 (17:54 +0000)]
test: remove some bleeding whitespace
Kill bleeding whitespace. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267577
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Konstantin Zhuravlyov [Tue, 26 Apr 2016 17:24:40 +0000 (17:24 +0000)]
[AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunctionInfo + minor commenting changes
Differential Revision: http://reviews.llvm.org/D19537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267573
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Sanjay Patel [Tue, 26 Apr 2016 17:11:17 +0000 (17:11 +0000)]
[CodeGenPrepare] use branch weight metadata to decide if a select should be turned into a branch
This is part of solving PR27344:
https://llvm.org/bugs/show_bug.cgi?id=27344
CGP should undo the SimplifyCFG transform for the same reason that earlier patches have used this
same mechanism: it's possible that passes between SimplifyCFG and CGP may be able to optimize the
IR further with a select in place.
For the TLI hook default, >99% taken or not taken is chosen as the default threshold for a highly
predictable branch. Even the most limited HW branch predictors will be correct on this branch almost
all the time, so even a massive mispredict penalty perf loss would be overcome by the win from all
the times the branch was predicted correctly.
As a follow-up, we could make the default target hook less conservative by using the SchedMachineModel's
MispredictPenalty. Or we could just let targets override the default by implementing the hook with that
and other target-specific options. Note that trying to statically determine mispredict rates for
close-to-balanced profile weight data is generally impossible if the HW is sufficiently advanced. Ie,
50/50 taken/not-taken might still be 100% predictable.
Finally, note that this patch as-is will not solve PR27344 because the current __builtin_unpredictable()
branch weight default values are 4 and 64. A proposal to change that is in D19435.
Differential Revision: http://reviews.llvm.org/D19488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267572
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Zachary Turner [Tue, 26 Apr 2016 16:57:53 +0000 (16:57 +0000)]
Fix build broken due to order of initialization problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267571
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Zachary Turner [Tue, 26 Apr 2016 16:20:00 +0000 (16:20 +0000)]
Refactor some more PDB reading code into DebugInfoPDB.
Differential Revision: http://reviews.llvm.org/D19445
Reviewed By: David Majnemer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267564
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Konstantin Zhuravlyov [Tue, 26 Apr 2016 15:43:14 +0000 (15:43 +0000)]
[AMDGPU] Reserve VGPRs for trap handler usage if instructed
Differential Revision: http://reviews.llvm.org/D19235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267563
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Nico Weber [Tue, 26 Apr 2016 13:53:56 +0000 (13:53 +0000)]
Use gcc's rules for parsing gcc-style response files
In gcc, \ escapes every character in response files. It is true that this makes
it harder to mention Windows files in rsp files, but not doing this means clang
disagrees with gcc, and also disagrees with the shell (on non-Windows) which
rsp file quoting is supposed to match. clang isn't free to choose what to do
here.
In general, the idea for response files is to take bits of your command line
and write them to a file unchanged, and have things work the same way. Since
the command line would've been interpreted by the shell, things in the rsp file
need to be subject to the same shell quoting rules.
People who want to put Windows-style paths in their response files either need
to do any of:
* escape their backslashes
* or use clang-cl which uses cl.exe/cmd.exe quoting rules
* pass --rsp-quoting=windows to clang to tell it to use
cl.exe/cmd.exe quoting rules for response files.
Fixes PR27464.
http://reviews.llvm.org/D19417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267556
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Sam Kolton [Tue, 26 Apr 2016 13:33:56 +0000 (13:33 +0000)]
[AMDGPU] Assembler: basic support for SDWA instructions
Support for SDWA instructions for VOP1 and VOP2 encoding.
Not done yet:
- converters for support optional operands and modifiers
- VOPC
- sext() modifier
- intrinsics
- VOP2b (see vop_dpp.s)
- V_MAC_F32 (see vop_dpp.s)
Differential Revision: http://reviews.llvm.org/D19360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267553
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Andrey Turetskiy [Tue, 26 Apr 2016 12:18:12 +0000 (12:18 +0000)]
[X86] PR27502: Fix the LEA optimization pass.
Handle MachineBasicBlock as a memory displacement operand in the LEA optimization pass.
Differential Revision: http://reviews.llvm.org/D19409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267551
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Marcin Koscielnicki [Tue, 26 Apr 2016 10:43:47 +0000 (10:43 +0000)]
[Sparc] Fix build error introduced by rL267545.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267549
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Marcin Koscielnicki [Tue, 26 Apr 2016 10:37:22 +0000 (10:37 +0000)]
[PowerPC] Add support for llvm.thread.pointer
Differential Revision: http://reviews.llvm.org/D19304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267546
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Marcin Koscielnicki [Tue, 26 Apr 2016 10:37:14 +0000 (10:37 +0000)]
[SPARC] [SSP] Add support for LOAD_STACK_GUARD.
This fixes PR22248 on sparc.
Differential Revision: http://reviews.llvm.org/D19386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267545
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Marcin Koscielnicki [Tue, 26 Apr 2016 10:37:01 +0000 (10:37 +0000)]
[SPARC] Add support for llvm.thread.pointer.
Differential Revision: http://reviews.llvm.org/D19387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267544
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