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Adam Nemet [Fri, 11 Jul 2014 05:23:12 +0000 (05:23 +0000)]
[X86] AVX512: Simplify logic in isCDisp8
It was computing the VL/n case as:
MemObjSize = VectorByteSize / ElemByteSize / Divider * ElemByteSize
ElemByteSize not only falls out but VectorByteSize/Divider now actually
matches the definition of VL/n.
Also some formatting fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212794
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David Blaikie [Fri, 11 Jul 2014 02:42:57 +0000 (02:42 +0000)]
Revert "Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself.""
This reverts commit r212776.
Nope, still seems to be failing on the sanitizer bots... but hey, not
the msan self-host anymore, it's failing in asan now. I'll start looking
there next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212793
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Mark Heffernan [Thu, 10 Jul 2014 23:30:06 +0000 (23:30 +0000)]
Partially fix PR20058: reduce compile time for loop unrolling with very high count by reducing calls to SE->forgetLoop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212782
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Lang Hames [Thu, 10 Jul 2014 23:29:11 +0000 (23:29 +0000)]
[RuntimeDyld] Replace a crufty old ARM RuntimeDyld test with a new one that uses
RuntimeDyldChecker.
This allows us to remove one of the six remaining object files in the LLVM
source tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212780
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Lang Hames [Thu, 10 Jul 2014 23:26:20 +0000 (23:26 +0000)]
[RuntimeDyld] Improve error diagnostic in RuntimeDyldChecker.
The compiler often emits assembler-local labels (beginning with 'L') for use in
relocation expressions, however these aren't included in the object files.
Teach RuntimeDyldChecker to warn the user if they try to use one of these in an
expression, since it will never work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212777
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David Blaikie [Thu, 10 Jul 2014 22:59:39 +0000 (22:59 +0000)]
Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself."
Committed in r212205 and reverted in r212226 due to msan self-hosting
failure, I believe I've got that fixed by r212761 to Clang.
Original commit message:
"Originally committed in r211723, reverted in r211724 due to failure
cases found and fixed (ArgumentPromotion: r211872, Inlining: r212065),
committed again in r212085 and reverted again in r212089 after fixing
some other cases, such as debug info subprogram lists not keeping track
of the function they represent (r212128) and then short-circuiting
things like LiveDebugVariables that build LexicalScopes for functions
that might not have full debug info.
And again, I believe the invariant actually holds for some reasonable
amount of code (but I'll keep an eye on the buildbots and see what
happens... ).
Original commit message:
PR20038: DebugInfo: Inlined call sites where the caller has debug info
but the call itself has no debug location.
This situation does bad things when inlined, so I've fixed Clang not to
produce inlinable call sites without locations when the caller has debug
info (in the one case where I could find that this occurred). This
updates the PR20038 test case to be what clang now produces, and readds
the assertion that had to be removed due to this bug.
I've also beefed up the debug info verifier to help diagnose these
issues in the future, and I hope to add checks to the inliner to just
assert-fail if it encounters this situation. If, in the future, we
decide we have to cope with this situation, the right thing to do is
probably to just remove all the DebugLocs from the inlined
instructions."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212776
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David Blaikie [Thu, 10 Jul 2014 22:57:40 +0000 (22:57 +0000)]
This test case doesn't actually need the inliner to reproduce the input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212775
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Jan Vesely [Thu, 10 Jul 2014 22:40:21 +0000 (22:40 +0000)]
R600: Implement float to long/ulong
Use alg. from LegalizeDAG.cpp
Move Expand setting to SIISellowering
v2: Extend existing tests instead of creating new ones
v3: use separate LowerFPTOSINT function
v4: use TargetLowering::expandFP_TO_SINT
add comment about using FP_TO_SINT for uints
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212773
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Jan Vesely [Thu, 10 Jul 2014 22:40:18 +0000 (22:40 +0000)]
SelectionDAG: Factor FP_TO_SINT lower code out of DAGLegalizer
Move the code to a helper function to allow calls from TypeLegalizer.
No functionality change intended
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
Reviewed-by: Owen Anderson <resistor@mac.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212772
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Brad Smith [Thu, 10 Jul 2014 22:37:28 +0000 (22:37 +0000)]
Use the integrated assembler by default on OpenBSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212771
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Zoran Jovanovic [Thu, 10 Jul 2014 22:23:30 +0000 (22:23 +0000)]
[mips] Emit two CFI offset directives per double precision SDC1/LDC1
instead of just one for FR=1 registers
Differential Revision: http://reviews.llvm.org/D4310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212769
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Andrea Di Biagio [Thu, 10 Jul 2014 18:59:41 +0000 (18:59 +0000)]
Extend the test coverage in combine-vec-shuffle-2.ll adding some negative tests.
Add test cases where we don't expect to trigger the combine optimizations
introduced at revision 212748.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212756
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Matt Arsenault [Thu, 10 Jul 2014 18:21:04 +0000 (18:21 +0000)]
Revert "Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine.""
Don't try to convert the select condition type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212750
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Andrea Di Biagio [Thu, 10 Jul 2014 18:04:55 +0000 (18:04 +0000)]
[DAG] Further improve the logic in DAGCombiner that folds a pair of shuffles into a single shuffle if the resulting mask is legal.
This patch teaches the DAGCombiner how to fold shuffles according to the
following new rules:
1. shuffle(shuffle(x, y), undef) -> x
2. shuffle(shuffle(x, y), undef) -> y
3. shuffle(shuffle(x, y), undef) -> shuffle(x, undef)
4. shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
The backend avoids to combine shuffles according to rules 3. and 4. if
the resulting shuffle does not have a legal mask. This is to avoid introducing
illegal shuffles that are potentially expanded into a sub-optimal sequence of
target specific dag nodes during vector legalization.
Added test case combine-vec-shuffle-2.ll to verify that we correctly triggers
the new rules when combining shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212748
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Akira Hatanaka [Thu, 10 Jul 2014 18:00:53 +0000 (18:00 +0000)]
[X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0.
Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable
macro-fusion.
<rdar://problem/
15680770>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212747
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Eric Christopher [Thu, 10 Jul 2014 17:26:54 +0000 (17:26 +0000)]
Add the CSR company and the Kalimba DSP processor to Triple.
Patch by Matthew Gardiner with fixes by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212745
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Eric Christopher [Thu, 10 Jul 2014 17:26:51 +0000 (17:26 +0000)]
Make it possible for the Subtarget to change between function
passes in the mips back end. This, unfortunately, required a
bit of churn in the various predicates to use a pointer rather
than a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212744
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Duncan P. N. Exon Smith [Thu, 10 Jul 2014 17:13:27 +0000 (17:13 +0000)]
InstCombine: Fix a crash in Descale for multiply-by-zero
Fix a crash in `InstCombiner::Descale()` when a multiply-by-zero gets
created as an argument to a GEP partway through an iteration, causing
-instcombine to optimize the GEP before the multiply.
rdar://problem/
17615671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212742
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David Majnemer [Thu, 10 Jul 2014 16:26:10 +0000 (16:26 +0000)]
IR: Aliases don't belong to an explicit comdat
Aliases inherit their comdat from their aliasee, they don't have an
explicit comdat.
This fixes PR20279.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212732
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Hal Finkel [Thu, 10 Jul 2014 16:07:11 +0000 (16:07 +0000)]
Feeding isSafeToSpeculativelyExecute its DataLayout pointer (in Sink)
This is the one remaining place I see where passing
isSafeToSpeculativelyExecute a DataLayout pointer might matter (at least for
loads) -- I think I got the others in r212720. Most of the other remaining
callers of isSafeToSpeculativelyExecute only use it for call sites (or
otherwise exclude loads).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212730
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David Majnemer [Thu, 10 Jul 2014 16:04:04 +0000 (16:04 +0000)]
Mips: Silence a -Wcovered-switch-default
Remove a default label which covered no enumerators, replace it with a
llvm_unreachable.
No functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212729
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Zoran Jovanovic [Thu, 10 Jul 2014 15:36:12 +0000 (15:36 +0000)]
[mips] Added FPXX modeless calling convention.
Differential Revision: http://reviews.llvm.org/D4293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212726
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Arnaud A. de Grandmaison [Thu, 10 Jul 2014 15:12:26 +0000 (15:12 +0000)]
[AArch64] Add logical alias instructions to MC AsmParser
This patch teaches the AsmParser to accept some logical+immediate
instructions and convert them as shown:
bic Rd, Rn, #imm -> and Rd, Rn, #~imm
bics Rd, Rn, #imm -> ands Rd, Rn, #~imm
orn Rd, Rn, #imm -> orr Rd, Rn, #~imm
eon Rd, Rn, #imm -> eor Rd, Rn, #~imm
Those instructions are an alternate syntax available to assembly coders,
and are needed in order to support code already compiling with some other
assemblers. For example, the bic construct is used by the linux kernel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212722
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Hal Finkel [Thu, 10 Jul 2014 14:41:31 +0000 (14:41 +0000)]
Feeding isSafeToSpeculativelyExecute its DataLayout pointer
isSafeToSpeculativelyExecute can optionally take a DataLayout pointer. In the
past, this was mainly used to make better decisions regarding divisions known
not to trap, and so was not all that important for users concerned with "cheap"
instructions. However, now it also helps look through bitcasts for
dereferencable loads, and will also be important if/when we add a
dereferencable pointer attribute.
This is some initial work to feed a DataLayout pointer through to callers of
isSafeToSpeculativelyExecute, generally where one was already available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212720
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Tim Northover [Thu, 10 Jul 2014 14:18:46 +0000 (14:18 +0000)]
AArch64: correctly fast-isel i8 & i16 multiplies
We were asking for a register for type i8 or i16 which caused an assert.
rdar://problem/
17620015
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212718
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Daniel Sanders [Thu, 10 Jul 2014 13:38:23 +0000 (13:38 +0000)]
[mips] Add support for -modd-spreg/-mno-odd-spreg
Summary:
When -mno-odd-spreg is in effect, 32-bit floating point values are not
permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit
floating point comparison results from being written to odd registers.
This option has three purposes:
* It allows support for certain MIPS implementations such as loongson-3a that
do not allow the use of odd registers for single precision arithmetic.
* When using -mfpxx, -mno-odd-spreg is the default and this allows us to
statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1
instructions to/from odd registers are guaranteed not to appear for any
reason. Once this has been established, the user can then re-enable
-modd-spreg to regain the use of all 32 single-precision registers.
* When using -mfp64 and -mno-odd-spreg together, an O32 extension named
O32 FP64A is used as the ABI. This is intended to provide almost all
functionality of an FR=1 processor but can also be executed on a FR=0 core
with the assistance of a hardware compatibility mode which emulates FR=0
behaviour on an FR=1 processor.
* Added '.module oddspreg' and '.module nooddspreg' each of which update
the .MIPS.abiflags section appropriately
* Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller
doesn't have to remember to do it.
* MipsABIFlags now calculates the flags1 and flags2 member on demand rather
than trying to maintain them in the same format they will be emitted in.
There is one portion of the -mfp64 and -mno-odd-spreg combination that is not
implemented yet. Moves to/from odd-numbered double-precision registers must not
use mtc1. I will fix this in a follow-up.
Differential Revision: http://reviews.llvm.org/D4383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212717
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Zinovy Nis [Thu, 10 Jul 2014 13:03:26 +0000 (13:03 +0000)]
[x32] Add AsmBackend for X32 which uses ELF32 with x86_64 (the author is Pavel Chupin).
This is minimal change for backend required to have "hello world" compiled and working on x32 target (x86_64-linux-gnux32). More patches for x32 will follow.
Differential Revision: http://reviews.llvm.org/D4181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212716
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Chandler Carruth [Thu, 10 Jul 2014 12:32:32 +0000 (12:32 +0000)]
[x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogous
to the zero-extend-vector-inreg node introduced previously for the same
purpose: manage the type legalization of widened extend operations,
especially to support the experimental widening mode for x86.
I'm adding both because sign-extend is expanded in terms of any-extend
with shifts to propagate the sign bit. This removes the last
fundamental scalarization from vec_cast2.ll (a test case that hit many
really bad edge cases for widening legalization), although the trunc
tests in that file still appear scalarized because the the shuffle
legalization is scalarizing. Funny thing, I've been working on that.
Some initial experiments with this and SSE2 scenarios is showing
moderately good behavior already for sign extension. Still some work to
do on the shuffle combining on X86 before we're generating optimal
sequences, but avoiding scalarization is a huge step forward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212714
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Richard Sandiford [Thu, 10 Jul 2014 11:44:37 +0000 (11:44 +0000)]
[SystemZ] Use SystemZCallingConv.td to define callee-saved registers
Just a clean-up. No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212711
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NAKAMURA Takumi [Thu, 10 Jul 2014 11:39:59 +0000 (11:39 +0000)]
SpecialCaseList.h: Fix -Wdocumentation with \code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212710
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NAKAMURA Takumi [Thu, 10 Jul 2014 11:37:39 +0000 (11:37 +0000)]
llvm/test/CodeGen/X86/shift-parts.ll: FileCheck-ize. (from r212640)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212709
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NAKAMURA Takumi [Thu, 10 Jul 2014 11:37:28 +0000 (11:37 +0000)]
Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine."
This caused miscompilation on, at least, x86-64. SExt(i1 cond) confused other optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212708
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Richard Sandiford [Thu, 10 Jul 2014 11:29:23 +0000 (11:29 +0000)]
[SystemZ] Tweak instruction format classifications
There's no real need to have Shift as a separate format type from Binary.
The comments for other format types were too specific and in some cases
no longer accurate.
Just a clean-up, no behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212707
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Chandler Carruth [Thu, 10 Jul 2014 11:09:29 +0000 (11:09 +0000)]
[x86] Add another combine that is particularly useful for the new vector
shuffle lowering: match shuffle patterns equivalent to an unpcklwd or
unpckhwd instruction.
This allows us to use generic lowering code for v8i16 shuffles and match
the unpack pattern late.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212705
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Richard Sandiford [Thu, 10 Jul 2014 11:00:55 +0000 (11:00 +0000)]
[SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA
These instructions aren't used for codegen since the original L*DB instructions
are suitable for fround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212703
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Richard Sandiford [Thu, 10 Jul 2014 10:52:51 +0000 (10:52 +0000)]
[SystemZ] Avoid using i8 constants for immediate fields
Immediate fields that have no natural MVT type tended to use i8 if the
field was small enough. This was a bit confusing since i8 isn't a legal
type for the target. Fields for short immediates in a 32-bit or 64-bit
operation use i32 or i64 instead, so it would be better to do the same
for all fields.
No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212702
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Richard Sandiford [Thu, 10 Jul 2014 10:45:11 +0000 (10:45 +0000)]
[SystemZ] Fix FPR dwarf numbering
The dwarf FPR numbers are supposed to have the order F0, F2, F4, F6,
F1, F3, F5, F7, F8, etc., which matches the pairing of registers for
long doubles. E.g. a long double stored in F0 is paired with F2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212701
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Daniel Sanders [Thu, 10 Jul 2014 10:18:12 +0000 (10:18 +0000)]
Make it possible for ints/floats to return different values from getBooleanContents()
Summary:
On MIPS32r6/MIPS64r6, floating point comparisons return 0 or -1 but integer
comparisons return 0 or 1.
Updated the various uses of getBooleanContents. Two simplifications had to be
disabled when float and int boolean contents differ:
- ScalarizeVecRes_VSELECT except when the kind of boolean contents is trivially
discoverable (i.e. when the condition of the VSELECT is a SETCC node).
- visitVSELECT (select C, 0, 1) -> (xor C, 1).
Come to think of it, this one could test for the common case of 'C'
being a SETCC too.
Preserved existing behaviour for all other targets and updated the affected
MIPS32r6/MIPS64r6 tests. This also fixes the pi benchmark where the 'low'
variable was counting in the wrong direction because it thought it could simply
add the result of the comparison.
Reviewers: hfinkel
Reviewed By: hfinkel
Subscribers: hfinkel, jholewinski, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D4389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212697
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Chandler Carruth [Thu, 10 Jul 2014 09:57:36 +0000 (09:57 +0000)]
[x86] Expand the target DAG combining for PSHUFD nodes to be able to
combine into half-shuffles through unpack instructions that expand the
half to a whole vector without messing with the dword lanes.
This fixes some redundant instructions in splat-like lowerings for
v16i8, which are now getting to be *really* nice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212695
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Chandler Carruth [Thu, 10 Jul 2014 09:16:40 +0000 (09:16 +0000)]
[x86] Tweak the v16i8 single input special case lowering for shuffles
that splat i8s into i16s.
Previously, we would try much too hard to arrange a sequence of i8s in
one half of the input such that we could unpack them into i16s and
shuffle those into place. This isn't always going to be a cheaper i8
shuffle than our other strategies. The case where it is always going to
be cheaper is when we can arrange all the necessary inputs into one half
using just i16 shuffles. It happens that viewing the problem this way
also makes it much easier to produce an efficient set of shuffles to
move the inputs into one half and then unpack them.
With this, our splat code gets one step closer to being not terrible
with the new experimental lowering strategy. It also exposes two
combines missing which I will add next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212692
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Hal Finkel [Thu, 10 Jul 2014 07:04:37 +0000 (07:04 +0000)]
A test case for not asserting in isDereferenceablePointer upon unsized types
This is the test case for r212687.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212688
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Hal Finkel [Thu, 10 Jul 2014 06:06:11 +0000 (06:06 +0000)]
Fix isDereferenceablePointer not to try to take the size of an unsized type.
I'll add a test-case shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212687
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Hal Finkel [Thu, 10 Jul 2014 05:27:53 +0000 (05:27 +0000)]
Allow isDereferenceablePointer to look through some bitcasts
isDereferenceablePointer should not give up upon encountering any bitcast. If
we're casting from a pointer to a larger type to a pointer to a small type, we
can continue by examining the bitcast's operand. This missing capability
was noted in a comment in the function.
In order for this to work, isDereferenceablePointer now takes an optional
DataLayout pointer (essentially all callers already had such a pointer
available). Most code uses isDereferenceablePointer though
isSafeToSpeculativelyExecute (which already took an optional DataLayout
pointer), and to enable the LICM test case, LICM needs to actually provide its DL
pointer to isSafeToSpeculativelyExecute (which it was not doing previously).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212686
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Saleem Abdulrasool [Thu, 10 Jul 2014 04:50:09 +0000 (04:50 +0000)]
MC: modernise for loop
Convert a for loop to range bsaed form. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212684
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Saleem Abdulrasool [Thu, 10 Jul 2014 04:50:06 +0000 (04:50 +0000)]
MC: add and use an accessor for WinCFI
This adds a utility method to access the WinCFI information in bulk and uses
that to iterate rather than requesting the count and individually iterating
them. This is in preparation for restructuring WinCFI handling to enable more
clear sharing across architectures to enable unwind information emission for
Windows on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212683
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Peter Collingbourne [Thu, 10 Jul 2014 04:39:40 +0000 (04:39 +0000)]
Remove move assignment operator to appease older GCCs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212682
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Chandler Carruth [Thu, 10 Jul 2014 04:34:06 +0000 (04:34 +0000)]
[x86] Initial improvements to the new shuffle lowering for v16i8
shuffles specifically for cases where a small subset of the elements in
the input vector are actually used.
This is specifically targetted at improving the shuffles generated for
trunc operations, but also helps out splat-like operations.
There is still some really low-hanging fruit here that I want to address
but this is a huge step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212680
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Peter Collingbourne [Thu, 10 Jul 2014 04:29:06 +0000 (04:29 +0000)]
Explicitly define move constructor and move assignment operator to appease MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212679
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Peter Collingbourne [Thu, 10 Jul 2014 03:55:02 +0000 (03:55 +0000)]
SpecialCaseList: use std::unique_ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212678
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Hao Liu [Thu, 10 Jul 2014 03:41:50 +0000 (03:41 +0000)]
[AArch64]Fix an assertion failure in DAG Combiner about concating 2 build_vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212677
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Matt Arsenault [Thu, 10 Jul 2014 03:22:20 +0000 (03:22 +0000)]
R600/SI: Add support for llvm.convert.{to|from}.fp16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212676
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Matt Arsenault [Thu, 10 Jul 2014 03:22:16 +0000 (03:22 +0000)]
Fix types in documentation.
The examples were using f32, but the IR type is called float
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212675
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Chandler Carruth [Thu, 10 Jul 2014 02:24:26 +0000 (02:24 +0000)]
[x86] Refactor some of the new code for lowering v16i8 shuffles to
remove duplication and make it easier to select different strategies.
No functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212674
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Peter Collingbourne [Thu, 10 Jul 2014 01:30:39 +0000 (01:30 +0000)]
[dfsan] Handle bitcast aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212668
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Chandler Carruth [Wed, 9 Jul 2014 22:53:04 +0000 (22:53 +0000)]
[SDAG] Make the new zext-vector-inreg node default to expand so targets
don't need to set it manually.
This is based on feedback from Tom who pointed out that if every target
needs to handle this we need to reach out to those maintainers. In fact,
it doesn't make sense to duplicate everything when anything other than
expand seems unlikely at this stage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212661
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David Blaikie [Wed, 9 Jul 2014 21:02:41 +0000 (21:02 +0000)]
Recommit r212203: Don't try to construct debug LexicalScopes hierarchy for functions that do not have top level debug information.
Reverted by Eric Christopher (Thanks!) in r212203 after Bob Wilson
reported LTO issues. Duncan Exon Smith and Aditya Nandakumar helped
provide a reduced reproduction, though the failure wasn't too hard to
guess, and even easier with the example to confirm.
The assertion that the subprogram metadata associated with an
llvm::Function matches the scope data referenced by the DbgLocs on the
instructions in that function is not valid under LTO. In LTO, a C++
inline function might exist in multiple CUs and the subprogram metadata
nodes will refer to the same llvm::Function. In this case, depending on
the order of the CUs, the first intance of the subprogram metadata may
not be the one referenced by the instructions in that function and the
assertion will fail.
A test case (test/DebugInfo/cross-cu-linkonce-distinct.ll) is added, the
assertion removed and a comment added to explain this situation.
Original commit message:
If a function isn't actually in a CU's subprogram list in the debug info
metadata, ignore all the DebugLocs and don't try to build scopes, track
variables, etc.
While this is possibly a minor optimization, it's also a correctness fix
for an incoming patch that will add assertions to LexicalScopes and the
debug info verifier to ensure that all scope chains lead to debug info
for the current function.
Fix up a few test cases that had broken/incomplete debug info that could
violate this constraint.
Add a test case where this occurs by design (inlining a
debug-info-having function in an attribute nodebug function - we want
this to work because /if/ the nodebug function is then inlined into a
debug-info-having function, it should be fine (and will work fine - we
just stitch the scopes up as usual), but should the inlining not happen
we need to not assert fail either).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212649
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Alexey Samsonov [Wed, 9 Jul 2014 19:40:08 +0000 (19:40 +0000)]
Decouple llvm::SpecialCaseList text representation and its LLVM IR semantics.
Turn llvm::SpecialCaseList into a simple class that parses text files in
a specified format and knows nothing about LLVM IR. Move this class into
LLVMSupport library. Implement two users of this class:
* DFSanABIList in DFSan instrumentation pass.
* SanitizerBlacklist in Clang CodeGen library.
The latter will be modified to use actual source-level information from frontend
(source file names) instead of unstable LLVM IR things (LLVM Module identifier).
Remove dependency edge from ClangCodeGen/ClangDriver to LLVMTransformUtils.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212643
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Tim Northover [Wed, 9 Jul 2014 19:14:34 +0000 (19:14 +0000)]
Use simpler constructor for range adapter.
It is a good idea, it's slightly clearer and simpler. Unfortunately
the headline news is: we save one line!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212641
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Matt Arsenault [Wed, 9 Jul 2014 19:12:07 +0000 (19:12 +0000)]
Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine.
Do this if the truncate is free and the select is legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212640
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Jim Grosbach [Wed, 9 Jul 2014 18:55:52 +0000 (18:55 +0000)]
AArch64: Better codegen for storing to __fp16.
Storing will generally be immediately preceded by rounding from an f32
or f64, so make sure to match those patterns directly to convert into the
FPR16 register class directly rather than going through the integer GPRs.
This also eliminates an extra step in the convert-from-f64 path
which was first converting to f32 and then to f16 from there.
rdar://
17594379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212638
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Jim Grosbach [Wed, 9 Jul 2014 18:55:49 +0000 (18:55 +0000)]
Change an assert() to a diagnostic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212637
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Benjamin Kramer [Wed, 9 Jul 2014 18:53:57 +0000 (18:53 +0000)]
TargetRegisterInfo: Remove function that fell out of use years ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212636
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Cameron McInally [Wed, 9 Jul 2014 18:29:55 +0000 (18:29 +0000)]
Update ReleaseNotes to mention Atomic NAND semantic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212635
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Adam Nemet [Wed, 9 Jul 2014 18:22:33 +0000 (18:22 +0000)]
[X86] AVX512: Enable it in the Loop Vectorizer
This lets us experiment with 512-bit vectorization without passing
force-vector-width manually.
The code generated for a simple integer memset loop is properly vectorized.
Disassembly is still broken for it though :(.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212634
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Louis Gerbarg [Wed, 9 Jul 2014 17:54:32 +0000 (17:54 +0000)]
Make AArch64FastISel::EmitIntExt explicitly check its source and destination types
This is a follow up to r212492. There should be no functional difference, but
this patch makes it clear that SrcVT must be an i1/i8/16/i32 and DestVT must be
an i8/i16/i32/i64.
rdar://
17516686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212633
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Sanjay Patel [Wed, 9 Jul 2014 17:49:58 +0000 (17:49 +0000)]
removed duplicate testcase
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212632
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Sanjay Patel [Wed, 9 Jul 2014 16:34:54 +0000 (16:34 +0000)]
Fix for PR20059 (instcombine reorders shufflevector after instruction that may trap)
In PR20059 ( http://llvm.org/pr20059 ), instcombine eliminates shuffles that are necessary before performing an operation that can trap (srem).
This patch calls isSafeToSpeculativelyExecute() and bails out of the optimization in SimplifyVectorOp() if needed.
Differential Revision: http://reviews.llvm.org/D4424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212629
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Daniel Sanders [Wed, 9 Jul 2014 16:03:10 +0000 (16:03 +0000)]
Add Imagination Technologies to the vendors in llvm::Triple
Summary: This is a pre-requisite for supporting the mips-img-linux-gnu triple in clang.
Differential Revision: http://reviews.llvm.org/D4435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212626
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Tim Northover [Wed, 9 Jul 2014 13:03:37 +0000 (13:03 +0000)]
Generic: add range-adapter for option parsing.
I want to use it in lld, but while I'm here I'll update LLVM uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212615
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Chandler Carruth [Wed, 9 Jul 2014 12:36:54 +0000 (12:36 +0000)]
[x86] Fix a bug in my new zext-vector-inreg DAG trickery where we were
not widening the input type to the node sufficiently to let the ext take
place in a register.
This would in turn result in a mysterious bitcast assertion failure
downstream. First change here is to add back the helpful assert I had in
an earlier version of the code to catch this immediately.
Next change is to add support to the type legalization to detect when we
have widened the operand either too little or too much (for whatever
reason) and find a size-matched legal vector type to convert it to
first. This can also fail so we get a new fallback path, but that seems
OK.
With this, we no longer crash on vec_cast2.ll when using widening. I've
also added the CHECK lines for the zero-extend cases here. We still need
to support sign-extend and trunc (or something) to get plausible code
for the other two thirds of this test which is one of the regression
tests that showed the most scalarization when widening was
force-enabled. Slowly closing in on widening being a viable legalization
strategy without it resorting to scalarization at every turn. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212614
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Chandler Carruth [Wed, 9 Jul 2014 11:13:16 +0000 (11:13 +0000)]
Sink two variables only used in an assert into the assert itself. Should
fix the release builds with Werror.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212612
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Benjamin Kramer [Wed, 9 Jul 2014 11:12:39 +0000 (11:12 +0000)]
X86: When lowering v8i32 himuls use the correct shuffle masks for AVX2.
Turns out my trick of using the same masks for SSE4.1 and AVX2 didn't work out
as we have to blend two vectors. While there remove unecessary cross-lane moves
from the shuffles so the backend can lower it to palignr instead of vperm.
Fixes PR20118, a miscompilation of vector sdiv by constant on AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212611
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Chandler Carruth [Wed, 9 Jul 2014 10:58:18 +0000 (10:58 +0000)]
[x86] Add a ZERO_EXTEND_VECTOR_INREG DAG node and use it when widening
vector types to be legal and a ZERO_EXTEND node is encountered.
When we use widening to legalize vector types, extend nodes are a real
challenge. Either the input or output is likely to be legal, but in many
cases not both. As a consequence, we don't really have any way to
represent this situation and the prior code in the widening legalization
framework would just scalarize the extend operation completely.
This patch introduces a new DAG node to represent doing a zero extend of
a vector "in register". The core of the idea is to allow legal but
different vector types in the input and output. The output vector must
have fewer lanes but wider elements. The operation is defined to zero
extend the low elements of the input to the size of the output elements,
and drop all of the high elements which don't have a corresponding lane
in the output vector.
It also includes generic expansion of this node in terms of blending
a zero vector into the high elements of the vector and bitcasting
across. This in turn yields extremely nice code for x86 SSE2 when we use
the new widening legalization logic in conjunction with the new shuffle
lowering logic.
There is still more to do here. We need to support sign extension, any
extension, and potentially int-to-float conversions. My current plan is
to continue using similar synthetic nodes to model each of these
transitions with generic lowering code for each one.
However, with this patch LLVM already reaches performance parity with
GCC for the core C loops of the x264 code (assuming you disable the
hand-written assembly versions) when compiling for SSE2 and SSE3
architectures and enabling the new widening and lowering logic for
vectors.
Differential Revision: http://reviews.llvm.org/D4405
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212610
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Daniel Sanders [Wed, 9 Jul 2014 10:47:26 +0000 (10:47 +0000)]
[mips][mips64r6] Correct select patterns that have the condition or true/false values backwards
Summary: This bug caused SingleSource/Regression/C/uint64_to_float and SingleSource/UnitTests/2002-05-02-CastTest3 to fail (among others).
Differential Revision: http://reviews.llvm.org/D4388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212608
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Daniel Sanders [Wed, 9 Jul 2014 10:40:20 +0000 (10:40 +0000)]
[mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions
Summary:
It seems we accidentally read the wrong column of the table MIPS64r6 spec
and used the names for c.cond.fmt instead of cmp.cond.fmt.
Differential Revision: http://reviews.llvm.org/D4387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212607
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Chandler Carruth [Wed, 9 Jul 2014 10:36:42 +0000 (10:36 +0000)]
[x86] Initialize a pointer to null to fix a bug in r212602.
This should restore GCC hosts (which happen to put the bad stuff into
the pointer) and MSan, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212606
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Daniel Sanders [Wed, 9 Jul 2014 10:21:59 +0000 (10:21 +0000)]
[mips][mips64r6] Use JALR for indirect branches instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
This completes the change to use JALR instead of JR on MIPS32r6/MIPS64r6.
Reviewers: jkolek, vmedic, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212605
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Daniel Sanders [Wed, 9 Jul 2014 10:16:07 +0000 (10:16 +0000)]
[mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212604
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Daniel Sanders [Wed, 9 Jul 2014 10:07:36 +0000 (10:07 +0000)]
Add ability to emit internal instruction representation to CodeGen assembly output.
Summary:
This patch re-uses the implementation of 'llvm-mc -show-inst' and makes it
available to llc as 'llc -asm-show-inst'.
This is necessary to test parts of MIPS32r6/MIPS64r6 without resorting to
'llc -filetype=obj' tests. For example, on MIPS32r2 and earlier we use the
'jr $rs' instruction for indirect branches and returns. On MIPS32r6, we no
longer have 'jr $rs' and use 'jalr $zero, $rs' instead. The catch is that,
on MIPS32r6, 'jr $rs' is an alias for 'jalr $zero, $rs' and is the preferred
way of writing this instruction. As a result, all MIPS ISA's emit 'jr $rs' in
their assembly output and the assembler encodes this to different opcodes
according to the ISA.
Using this option, we can check that the MCInst really is a JR or a JALR by
matching the emitted comment. This removes the need for a 'llc -filetype=obj'
test.
Reviewers: rafael, dsanders
Reviewed By: dsanders
Subscribers: zoran.jovanovic, llvm-commits
Differential Revision: http://reviews.llvm.org/D4267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212603
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Chandler Carruth [Wed, 9 Jul 2014 10:06:58 +0000 (10:06 +0000)]
[x86] Re-apply a variant of the x86 side of r212324 now that the rest
has settled without incident, removing the x86-specific and overly
strict 'isVectorSplat' routine in favor of generic and more powerful
splat detection.
The primary motivation and result of this is that the x86 backend can
now see through splats which contain undef elements. This is essential
if we are using a widening form of legalization and I've updated a test
case to also run in that mode as before this change the generated code
for the test case was completely scalarized.
This version of the patch much more carefully handles the undef lanes.
- We aren't overly conservative about them in the shift lowering
(where we will never use the splat itself).
- One place where the splat would have been re-used by the existing code
now explicitly constructs a new constant splat that will be safe.
- The broadcast lowering is much more reasonable with undefs by doing
a correct check of whether the splat is the only user of a loaded
value, checking that the splat actually crosses multiple lanes before
using a broadcast, and handling broadcasts of non-constant splats.
As a consequence of the last bullet, the weird usage of vpshufd instead
of vbroadcast is gone, and we actually can lower an AVX splat with
vbroadcastss where before we emitted a really strange pattern of
a vector load and a manual splat across the vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212602
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Timur Iskhodzhanov [Wed, 9 Jul 2014 08:35:33 +0000 (08:35 +0000)]
[ASan/Win] Don't instrument COMDAT globals. Properly fixes PR20244.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212596
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Dmitri Gribenko [Wed, 9 Jul 2014 08:30:15 +0000 (08:30 +0000)]
SourceMgr: consistently use 'unsigned' for the memory buffer ID type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212595
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Alp Toker [Wed, 9 Jul 2014 06:27:05 +0000 (06:27 +0000)]
Prospective -fsanitize=memory build fix following r212586
This -f group flag appears to influence linker flags, breaking the usual rules
and causing CMake's link invocation to fail during feature detection due to
missing link dependencies (msan_*).
Let's forcibly add it for now to get things the way they were before feature
detection started working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212590
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Nikola Smiljanic [Wed, 9 Jul 2014 05:34:24 +0000 (05:34 +0000)]
Use correct memeber when displaying StringMap's size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212588
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Alp Toker [Wed, 9 Jul 2014 03:39:32 +0000 (03:39 +0000)]
CMake: make __DATE__, __TIME__ etc. macro usage an error
When LLVM_ENABLE_TIMESTAMPS has been disabled we can prevent the preprocessor
from embedding dates, times and file timestamps.
There are a few motivations for this:
1) Validate the recent CMake feature detection bugfix from LLVM r212586 with
a flag that's not actually available everywhere.
2) Dogfood clang's new -Wdate-time warning from r210511 when bootstrapping.
3) Encourage reproducible builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212587
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Alp Toker [Wed, 9 Jul 2014 03:38:19 +0000 (03:38 +0000)]
CMake: fix compiler feature detection
add_flag_if_supported() and add_flag_or_print_warning() were effectively
no-ops, just returning the value of the first result (usually
'-fno-omit-frame-pointer') for all subsequent checks for different flags.
Due to the way CMake caches feature detection results, we need to provide
symbolic variable names which will persist the cached results. This commit
fixes feature detection using these two macros.
The feature checks now run and get stored correctly, and the correct output can
be observed in configure logs:
-- Performing Test C_SUPPORTS_FPIC
-- Performing Test C_SUPPORTS_FPIC - Success
-- Performing Test CXX_SUPPORTS_FPIC
-- Performing Test CXX_SUPPORTS_FPIC - Success
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212586
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Chandler Carruth [Wed, 9 Jul 2014 00:41:34 +0000 (00:41 +0000)]
[SDAG] At the suggestion of Hal, switch to an output parameter that
tracks which elements of the build vector are in fact undef.
This should make actually inpsecting them (likely in my next patch)
reasonably pretty. Also makes the output parameter optional as it is
clear now that *most* users are happy with undefs in their splats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212581
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Ehsan Akhgari [Wed, 9 Jul 2014 00:40:50 +0000 (00:40 +0000)]
[ms-coff] Add a test for proper handling of full Windows path names in the .drectve section
Summary: This test ensures that we can correctly specify a full Windows path to the clang ASAN runtime libraries. This is in preparation to fix PR20246.
Reviewers: rafael
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212580
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NAKAMURA Takumi [Tue, 8 Jul 2014 23:48:22 +0000 (23:48 +0000)]
MipsTargetStreamer.h: Avoid "using" to appease msc17.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212577
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Kevin Enderby [Tue, 8 Jul 2014 23:47:31 +0000 (23:47 +0000)]
Changed the lvm-nm alias "-s" for -print-armap to "-M".
This will allow the "-s" flag to implemented in the future as it
is in darwin’s nm(1) to list symbols only in the specified section.
Given a LGTM by Shankar Easwaran who originally implemented
the support for lvm-nm’s -print-armap and archive map symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212576
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Jim Grosbach [Tue, 8 Jul 2014 23:28:48 +0000 (23:28 +0000)]
AArch64: Better codegen for loading from __fp16.
Loading will generally extend to an f32 or an 64, so make sure
to match those patterns directly to load into the FPR16 register
class directly rather than going through the integer GPRs.
This also eliminates an extra step in the convert-to-f64 path
which was first converting to f32 and then to f64 from there.
rdar://
17594379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212573
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Hal Finkel [Tue, 8 Jul 2014 23:16:49 +0000 (23:16 +0000)]
Improve BasicAA CS-CS queries
BasicAA contains knowledge of certain intrinsics, such as memcpy and memset,
and uses that information to form more-accurate answers to CallSite vs. Loc
ModRef queries. Unfortunately, it did not use this information when answering
CallSite vs. CallSite queries.
Generically, when an intrinsic takes one or more pointers and the intrinsic is
marked only to read/write from its arguments, the offset/size is unknown. As a
result, the generic code that answers CallSite vs. CallSite (and CallSite vs.
Loc) queries in AA uses UnknownSize when forming Locs from an intrinsic's
arguments. While BasicAA's CallSite vs. Loc override could use more-accurate
size information for some intrinsics, it did not do the same for CallSite vs.
CallSite queries.
This change refactors the intrinsic-specific logic in BasicAA into a generic AA
query function: getArgLocation, which is overridden by BasicAA to supply the
intrinsic-specific knowledge, and used by AA's generic implementation. This
allows the intrinsic-specific knowledge to be used by both CallSite vs. Loc and
CallSite vs. CallSite queries, and simplifies the BasicAA implementation.
Currently, only one function, Mac's memset_pattern16, is handled by BasicAA
(all the rest are intrinsics). As a side-effect of this refactoring, BasicAA's
getModRefBehavior override now also returns OnlyAccessesArgumentPointees for
this function (which is an improvement).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212572
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Tobias Grosser [Tue, 8 Jul 2014 22:51:03 +0000 (22:51 +0000)]
DominanceInfo is strongly preferred over RegionInfo
This is and always was strong community consensus. Make this clear in the header
in case newcomers may not be aware.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212570
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Kevin Enderby [Tue, 8 Jul 2014 22:10:02 +0000 (22:10 +0000)]
Add support for BSD format Archive map symbols (aka the table of contents
from a __.SYMDEF or "__.SYMDEF SORTED" archive member).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212568
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Pete Cooper [Tue, 8 Jul 2014 17:06:03 +0000 (17:06 +0000)]
Revert "GlobalDCE: Delete available_externally initializers if it allows removing the value the initializer is referring to."
This reverts commit
5b55a47e94e28fbb56d0cd5d72c3db9105c15b4c.
A test case was found to crash after this was applied. I'll file a bug to track fixing this with the test case needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212550
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Ulrich Weigand [Tue, 8 Jul 2014 16:16:02 +0000 (16:16 +0000)]
[PowerPC] Implement atomic NAND operations as actual NAND
This changes the implementation of atomic NAND operations
from "a & ~b" (compatible with GCC < 4.4) to actual "~(a & b)"
(compatible with GCC >= 4.4).
This is in line with the common-code and ARM back-end change
implemented in r212433.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212547
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Andrea Di Biagio [Tue, 8 Jul 2014 15:22:29 +0000 (15:22 +0000)]
[DAG] Teach how to combine a pair of shuffles into a single shuffle if the resulting mask is legal.
This patch teaches how to fold a shuffle according to rule:
shuffle (shuffle (x, undef, M0), undef, M1) -> shuffle(x, undef, M2)
We do this only if the resulting mask M2 is legal; this is to avoid introducing
illegal shuffles that are potentially expanded into a sub-optimal sequence
of target specific dag nodes.
This patch has the advantage of being target independent, since it works on ISD
nodes. Therefore, all targets (not only x86) can take advantage of this rule.
The idea behind this patch is that most shuffle pairs can be safely combined
before we run the legalizer on vector operations. This allows us to
combine/simplify dag nodes earlier in the process and not only immediately
before instruction selection stage.
That said. This patch is not meant to replace any existing target specific
combine rules; backends might still introduce new shuffles during legalization
stage. Also, this rule is very simple and avoids to aggressively optimize
shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212539
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Benjamin Kramer [Tue, 8 Jul 2014 14:55:06 +0000 (14:55 +0000)]
Fix some Twine locals.
Two of those are use after frees. Found by clang-tidy, fixed by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212537
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Timur Iskhodzhanov [Tue, 8 Jul 2014 13:18:58 +0000 (13:18 +0000)]
[ASan/Win] Don't instrument private COMDAT globals until PR20244 is properly fixed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212530
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Daniel Sanders [Tue, 8 Jul 2014 13:13:42 +0000 (13:13 +0000)]
[mips] Fixed struct/class mismatch introduced in r212522.
Clang emits a warning about this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212528
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