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Bart Oldeman [Sun, 3 Feb 2019 02:57:10 +0000 (02:57 +0000)]
gallium-xlib: query MIT-SHM before using it.
When Mesa is compiled for gallium-xlib using e.g.
./configure --enable-glx=gallium-xlib --disable-dri --disable-gbm
-disable-egl
and is used by an X server (usually remotely via SSH X11 forwarding)
that does not support MIT-SHM such as XMing or MobaXterm, OpenGL
clients report error messages such as
Xlib: extension "MIT-SHM" missing on display "localhost:11.0".
ad infinitum.
The reason is that the code in src/gallium/winsys/sw/xlib uses
MIT-SHM without checking for its existence, unlike the code
in src/glx/drisw_glx.c and src/mesa/drivers/x11/xm_api.c.
I copied the same check using XQueryExtension, and tested with
glxgears on MobaXterm.
This issue was reported before here:
https://lists.freedesktop.org/archives/mesa-users/2016-July/001183.html
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
a203eaa4f4fb672b95426289b8dad3a8998f92d7)
Emil Velikov [Tue, 12 Feb 2019 21:07:17 +0000 (21:07 +0000)]
cherry-ignore: nv50,nvc0: add explicit settings for recent caps
stable Explicit 19.0 only nomination.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Marek Olšák [Thu, 24 Jan 2019 00:48:26 +0000 (19:48 -0500)]
meson: drop the xcb-xrandr version requirement
autotools doesn't have any requirement. This fixes meson on Ubuntu 16.04.
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit
1e85cfb91a08565f28f51cc19573324722765823)
Jason Ekstrand [Tue, 15 Jan 2019 16:53:44 +0000 (10:53 -0600)]
intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode
Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions. If you have a SIMD8 instruction in a SIMD16 shader,
neither would trigger and the restriction could still be hit.
Fixes:
232ed8980217dd "i965/fs: Register allocator shoudn't use grf127..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
b4f0d062cd12b4f675bac900ac41d1085a79239a)
Ernestas Kulik [Thu, 30 Aug 2018 16:02:46 +0000 (19:02 +0300)]
v3d: Fix leak in resource setup error path
Reported by Coverity: in the case of unsupported modifier request, the
code does not jump to the “fail” label to destroy the acquired resource.
CID:
1435704
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Fixes:
45bb8f295710 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.")
(cherry picked from commit
90458bef544ac46a912f06e73f71c3cb20fdaaf6)
Ernestas Kulik [Thu, 30 Aug 2018 16:02:47 +0000 (19:02 +0300)]
vc4: Fix leak in HW queries error path
Reported by Coverity: in the case where there exist hardware and
non-hardware queries, the code does not jump to err_free_query and leaks
the query.
CID:
1430194
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Fixes:
9ea90ffb98fb ("broadcom/vc4: Add support for HW perfmon")
(cherry picked from commit
f6e49d5ad0fde19a074644491475470d684dd721)
Jason Ekstrand [Wed, 31 Oct 2018 15:18:21 +0000 (10:18 -0500)]
intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()
Like all the other sends, it's just mlen * REG_SIZE.
Fixes:
3cbc02e4693 "intel: Use TXS for image_size when we have..."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
cf42b0f9e2d2d612f92b24ec8a5a77ff107b92ab)
Rob Clark [Tue, 29 Jan 2019 17:23:28 +0000 (12:23 -0500)]
freedreno: stop frob'ing pipe_resource::nr_samples
Previously we tried to normalize nr_samples to MAX2(1, nr_samples) to
avoid having to deal with 0 vs 1 everywhere. But this causes problems
in mesa/st, for example st_finalize_texture() will think there is a
nr_samples mismatch and recreate the texture. Somehow this manifests
as corrupt x11 font rendering on generations that do not support MSAA
(but apparently works fine on a5xx and a6xx which do support MSAA.)
Fixes:
cf0c7258ee0 freedreno/a5xx: MSAA
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
c3baa077bf6db9f9d46be62ed7cbbc3167e68c8f)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/drivers/freedreno/freedreno_batch_cache.c
Emil Velikov [Thu, 31 Jan 2019 21:08:36 +0000 (21:08 +0000)]
docs: add sha256 checksums for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 31 Jan 2019 20:58:09 +0000 (20:58 +0000)]
docs: add release notes for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Danylo Piliaiev [Thu, 10 Jan 2019 16:16:59 +0000 (18:16 +0200)]
glsl: Fix copying function's out to temp if dereferenced by array
Function's out variable could be an array dereferenced by an array:
func(v[w[i]]);
or something more complicated.
Copy index in any case.
Fixes:
76c27e47b906 ("glsl: Copy function out to temp if we don't directly ref a variable")
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
0862929bf64222e85e8242824aecf05e494c157c)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109488
Nominated-by: Matt Turner <mattst88@gmail.com>
Timothy Arceri [Mon, 9 Apr 2018 04:40:40 +0000 (14:40 +1000)]
glsl: Copy function out to temp if we don't directly ref a variable
Otherwise we can end up with IR that looks like this:
(
(declare (temporary ) vec4 f@8)
(assign (xyzw) (var_ref f@8) (var_ref f) )
(call f16 ((swiz y (var_ref f@8) )))
(assign (xyzw) (var_ref f) (var_ref f@8) )
))
When we really need:
(declare (temporary ) float inout_tmp)
(assign (x) (var_ref inout_tmp) (swiz y (var_ref f) ))
(call f16 ((var_ref inout_tmp) ))
(assign (y) (var_ref f) (swiz y (swiz xxxx (var_ref inout_tmp) )))
(declare (temporary ) void void_var)
The GLSL IR function inlining code seemed to produce correct code
even without this but we need the correct IR for GLSL IR -> NIR to
be able to understand whats going on.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
76c27e47b90647df047e785d6b3ab5d0d979a1ee)
Nominated-by: Matt Turner <mattst88@gmail.com>
Tomeu Vizoso [Mon, 17 Dec 2018 08:56:00 +0000 (09:56 +0100)]
etnaviv: Consolidate buffer references from framebuffers
We were leaking surfaces because the references taken in
etna_set_framebuffer_state weren't being released on context destroy.
Instead of just directly releasing those references in
etna_context_destroy, use the util_copy_framebuffer_state helper.
Take the chance to remove the duplicated buffer references in
compiled_framebuffer_state to avoid confusion.
The leak can be reproduced with a client that continuously creates and
destroys contexts.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reported-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit
bf1dfcc3e8120400c9a78d03dd914a786728b5f7)
[Emil: resolve trivial conflict - dummy_rt does not exist in branch]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/drivers/etnaviv/etnaviv_context.c
Eric Anholt [Mon, 28 Jan 2019 19:39:12 +0000 (11:39 -0800)]
vc4: Enable NEON asm on meson cross-builds.
The core Mesa with_asm_arch and USE_ARM_ASM flags are disabled for meson
cross-builds because of the need to run host binaries on the build system.
vc4 doesn't need to do that, so skip with_asm_arch to enable NEON on my
cross-builds.
Fixes:
ebcb4c2156e9 ("meson: Enable VC4's NEON assembly support.")
(cherry picked from commit
932ed9c00b99e6ec92146ec9e820f546cf3e6551)
Vinson Lee [Sat, 26 Jan 2019 08:21:06 +0000 (00:21 -0800)]
meson: Fix typo.
meson.build:166:21: ERROR: Unknown method "verson_compare" for a string.
Fixes:
c1efa240c91e ("meson: Add warnings and errors when using ICC")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
be5b271ea76d81d32e3dc490ef5b32a61c3fb965)
Carsten Haitzler (Rasterman) [Tue, 8 Jan 2019 16:28:30 +0000 (16:28 +0000)]
vc4: Declare the cpu pointers as being modified in NEON asm.
Otherwise, the compiler is free to reuse the register containing the input
for another call and assume that the value hasn't been modified. Fixes
crashes on texture upload/download with current gcc.
We now have to have a temporary for the cpu2 value, since outputs must be
lvalues.
(commit message by anholt)
Fixes:
4d30024238ef ("vc4: Use NEON to speed up utile loads on Pi2.")
(cherry picked from commit
300d3ae8b1445b5060f92c77c0f577f4b7b2c7d6)
[Emil: apply the patch to vc4_tiling_lt.c instead of v3d_cpu_tiling.h]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/broadcom/common/v3d_cpu_tiling.h
Squashed with commit:
vc4: Declare the last cpu pointer as being modified in NEON asm.
Earlier commit addressed 7 of the 8 instances available.
v2: Rebase patch back to master (by anholt)
Cc: Carsten Haitzler (Rasterman) <raster@rasterman.com>
Cc: Eric Anholt <eric@anholt.net>
Fixes:
300d3ae8b14 ("vc4: Declare the cpu pointers as being modified in NEON asm.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
385843ac3ce1b868d9e24fcb2dbc0c8d5f5a7c99)
Conflicts:
src/broadcom/common/v3d_cpu_tiling.h
Carsten Haitzler (Rasterman) [Tue, 29 Jan 2019 16:55:30 +0000 (16:55 +0000)]
vc4: Use named parameters for the NEON inline asm.
This makes the asm code more intelligible and clarifies the functional
change in the next commit.
(commit message and commit squashing by anholt)
(cherry picked from commiti
522f68847152e9111def094f7fb35b44f3d0fc80)
[Emil: apply the patch to vc4_tiling_lt.c instead of v3d_cpu_tiling.h]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/broadcom/common/v3d_cpu_tiling.h
Timothy Arceri [Mon, 28 Jan 2019 06:15:34 +0000 (17:15 +1100)]
glsl: use remap location when serialising uniform program resource data
This allows us to avoid expensive string compares since we already have
a map to the pointers.
These compares were taking ~30 seconds for a single shader compile
in Godot due to it using 64,000+ uniforms.
Fixes:
c4cff5f40254 ("glsl: add basic support for resource list to shader cache")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109229
(cherry picked from commit
fb78a6cb72270de271f75d6f6c9b5ebadba7a898)
Timothy Arceri [Thu, 24 Jan 2019 05:02:17 +0000 (16:02 +1100)]
radv/ac: fix some fp16 handling
Fixes:
b722b29f10d4 ("radv: add support for 16bit input/output")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
0907ae35ad0e7733535516fada04948ea7125291)
Niklas Haas [Thu, 22 Nov 2018 23:32:29 +0000 (00:32 +0100)]
radv: correctly use vulkan 1.0 by default
From the vulkan spec 3.2 "Instances":
"Providing a NULL VkInstanceCreateInfo::pApplicationInfo or providing an
apiVersion of 0 is equivalent to providing an apiVersion of
VK_MAKE_VERSION(1,0,0)."
Fixes:
ffa15861ef7c924a33e1f "radv: UseEnumerateInstanceVersion for the default version."
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
d12dc3939620dcc942523a30a7fcc3271e751a6c)
Axel Davy [Tue, 22 Jan 2019 19:14:43 +0000 (20:14 +0100)]
st/nine: Immediately upload user provided textures
Fixes regression caused by
42d672fa6a766363e5703f119607f7c7975918aa
st/nine: Bind src not dst in nine_context_box_upload
Before that patch, for user provided textures,
when the texture was destroyed, the safety
check for pending uploads, which according to
the code "Following condition cannot happen currently",
was flushing the queue and thus triggering the upload.
After the patch, the texture destruction was delayed after
the upload. However the user frees the texture buffer,
as it thinks the texture released.
Instead of reverting the faulty patch,
this patch instead flushes the csmt queue right away
after queuing the upload for this type of textures.
This is more future-proof, as we may want to bind the
surface for other reasons in the future.
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
d7433c22e6c9624ca5275a3cd35be79caed9fffc)
Dylan Baker [Mon, 14 Jan 2019 23:23:41 +0000 (15:23 -0800)]
meson: Add warnings and errors when using ICC
ICC tries to be helpful by not erroring when it sees something that it
doesn't understand, which is completely the opposite of helpful. Meson
0.49.0 does much better at handling this by really trying to make ICC
error, but there are some things in mesa that still get ignored until
0.49.1
v2: - Fix id check, which is 'intel' not 'icc'
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
(cherry picked from commit
c1efa240c91e78385e8e433af134289b006016d0)
Lionel Landwerlin [Thu, 17 Jan 2019 18:19:59 +0000 (18:19 +0000)]
anv: fix invalid binding table index computation
The ++ operator strikes again.
Fixes:
f92c5bc8f3f517 ("anv/device: fix maximum number of images supported")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
4149d41f2e4ea02ca86975d25ab160e69bf0f8e5)
Emil Velikov [Tue, 29 Jan 2019 15:38:06 +0000 (15:38 +0000)]
cherry-ignore: WARNING: Commit XXX lists invalid sha
warn The commits refer stale sha, yet don't fix anything in particular.
98984b7cdd79c15cc7331c791f8be61e873b8bbd
9f86f1da7c68b5b900cd6f60925610ff1225a72d
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Timothy Arceri [Wed, 23 Jan 2019 03:58:40 +0000 (14:58 +1100)]
ac/nir_to_llvm: fix clamp shadow reference for more hardware
Fixes the following piglit test on my VEGA and matches the behaviour in the
tgsi backend.
tests/spec/glsl-1.10/execution/samplers/glsl-fs-shadow2D-clamp-z.shader_test
Fixes:
625dcbbc4566 ("amd/common: pass address components individually to ac_build_image_intrinsic")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
5d66f7103f0df6b996951e65483fc5873d9b66df)
Eric Engestrom [Tue, 11 Dec 2018 16:51:25 +0000 (16:51 +0000)]
meson/vdpau: add missing soversion
This mirrors what autotools does in src/gallium/state_trackers/vdpau/Makefile.am
and src/gallium/targets/vdpau/Makefile.am:
VDPAU_MAJOR = 1
VDPAU_MINOR = 0
libvdpau_gallium_la_LDFLAGS = -version-number $(VDPAU_MAJOR):$(VDPAU_MINOR)
Reported-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Fixes:
68076b87474e7959c161 "meson: build gallium vdpau state tracker"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
69e944036720d826d0548a019f8fe18b9ed57e6e)
Dylan Baker [Mon, 14 Jan 2019 23:15:09 +0000 (15:15 -0800)]
meson: Fix compiler checks for SWR with ICC
This is a bit fragile, as the way this "fixes" the check is to move the
one that we know is correct before the one that is incorrectly reported
as working. In meson 0.49.1 (which isn't out yet) this is fixed that the
incorrect check is reported as a failure.
Fixes:
e0b037d6979b266d4959c1e31746d4d19c941fdb
("meson: Build SWR driver")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109129
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
7cb7f35bc76bf21d15ca4b1f4ee724e9ff1e2804)
Dylan Baker [Mon, 14 Jan 2019 22:44:30 +0000 (14:44 -0800)]
meson: fix swr KNL build
There's a typo in one of the #defines that breaks compilation.
Fixes:
e0b037d6979b266d4959c1e31746d4d19c941fdb
("meson: Build SWR driver")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109023
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
3ba7ab8d2c8454346c3349ddc56cb480eea4f958)
Dave Airlie [Thu, 27 Dec 2018 04:26:49 +0000 (14:26 +1000)]
gallium: use put image shm2 path (v2)
This fixes the drisw paths to use the new shm2 interface, so that
we don't trigger the X server overflow checks when the x offset is non-zero.
This just hides the versioning in drisw, and either passes the src_x
or adds the offset fixup for the fallback path.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit
1f6b92b47652e7f48f03ef6a4228a19537022d23)
Dave Airlie [Thu, 27 Dec 2018 04:26:33 +0000 (14:26 +1000)]
glx: add support for putimageshm2 path (v2)
v2: pass x,0 in as the offset coords at glx level not earlier
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit
00af91ca463a2486c043c635d94d9958fb1e8700)
Dave Airlie [Thu, 27 Dec 2018 04:26:04 +0000 (14:26 +1000)]
dri_interface: add put shm image2 (v2)
This adds a new interface to the swrast interface to fix an shm put image bug.
The current code adds the x,y src offsets into the offset parameters,
however if the x offset is > 0, and the put image copies up to the height
of the image, this can trigger an X server validation check to fail and
the renderering to get BadMatch.
This patch fixes it to pass the x offset coord in as a src x.
We cannot pass the Y coordinate due to the horrible code mangling the
image w/h vs stride in swrastXPutImage.
v2: drop srcx,y from api
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit
db83a2b40f95fa3b9a741e9797dbf3e18f065a71)
Marek Olšák [Mon, 21 Jan 2019 17:09:07 +0000 (12:09 -0500)]
st/mesa: purge framebuffers when unbinding a context
This fixes pipe_surface "leaks".
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
c89e8470e58066637c4bfd5c76a2247eb3608b8b)
Rob Clark [Tue, 22 Jan 2019 19:08:41 +0000 (14:08 -0500)]
loader: fix the no-modifiers case
Normally modifiers take precendence over use flags, as they are more
explicit. But if the driver supports modifiers, but the xserver does
not, then we should fallback to the old mechanism of allocating a buffer
using 'use' flags.
Fixes:
069fdd5f9facbd72fb6a289696c7b74e3237e70f
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
(cherry picked from commit
c56fe4118a2dd991ff1b2a532c0f234eddd435e9)
Marek Olšák [Thu, 10 Jan 2019 19:32:42 +0000 (14:32 -0500)]
radeonsi: fix rendering to tiny viewports where the viewport center is > 8K
This fixes an assertion failure with GL CTS when cts-runner is used.
(not a specific test)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108877
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
4c4c8bb1f047234d738ab9bb70938bee4733ed2e)
Marek Olšák [Fri, 11 Jan 2019 20:11:30 +0000 (15:11 -0500)]
radeonsi: fix a u_blitter crash after a shader with FBFETCH
This fixes an assertion failure with GL CTS when cts-runner is used.
(not a specific test)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108877
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
caa2dcd7309311c3f707b1855c7e30c1c72818e2)
Jason Ekstrand [Thu, 6 Dec 2018 22:49:27 +0000 (16:49 -0600)]
nir/xfb: Fix offset accounting for dvec3/4
Before, we were double-counting the component slots when we had a dvec3
or dvec4. Instead, just add them in once and manually offset the
recorded output offset.
Fixes:
19064b8c "nir: Add a pass for gathering transform feedback info"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit
4f99ac9144abda9b4e7d0891571eb1691b853c25)
Eric Engestrom [Mon, 21 Jan 2019 19:44:45 +0000 (19:44 +0000)]
configure: EGL requirements only apply if EGL is built
Issue was hit with this configuration:
--disable-{egl,gbm} --with-platform=drm
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes:
3208fd2e46b ("configure: move platform handling further up")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
610f956fdead37da49ee2857a2261c3dfd8fc3cd)
Jason Ekstrand [Sat, 19 Jan 2019 15:40:12 +0000 (09:40 -0600)]
anv: Only parse pImmutableSamplers if the descriptor has samplers
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
c7f4a2867ce492d78c1f8e2870c0a593d280572d)
Karol Herbst [Fri, 18 Jan 2019 13:13:25 +0000 (14:13 +0100)]
glsl/lower_output_reads: set invariant and precise flags on temporaries
fixes a couple of deqp tests (on nvc0 and potential other drivers):
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_3
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_3
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_3
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
987744be9850bfe3a7c3c9556ae5d48ee5c34352)
Timothy Arceri [Thu, 10 Jan 2019 04:54:43 +0000 (15:54 +1100)]
ac/nir_to_llvm: fix interpolateAt* for arrays
This builds on the recent interpolate fix by Rhys
ee8488ea3b99.
This fixes the arb_gpu_shader5 interpolateAt* tests that contain
arrays.
Fixes:
ee8488ea3b99 ("ac/nir,radv,radeonsi/nir: use correct indices for interpolation intrinsics")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
9e669ed22b52857495593b92537d53c9ead7d424)
Karol Herbst [Thu, 17 Jan 2019 22:32:19 +0000 (23:32 +0100)]
nv50/ir: disable tryCollapseChainedMULs in ConstantFolding for precise instructions
fixes dEQP-GLES2.functional.shaders.invariance.mediump.loop_3
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
30b5c9eda2fe4c335cc15cb921e4f7774af0879e)
Bas Nieuwenhuizen [Thu, 17 Jan 2019 18:54:20 +0000 (19:54 +0100)]
nir: Account for atomics in copy propagation.
Otherwise writes get propagated across atomics if no barrier is
used. Without barrier writes should still be visible in the same
invocation, so an atomic has to be considered a write.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Fixes:
b3c61469255 "nir: Copy propagation between blocks"
Fixes:
62332d139c8 "nir: Add a local variable-based copy propagation pass"
(cherry picked from commit
8424cd8fbd1671c4c13f57cfa34bf8145d0fffcf)
Iago Toral Quiroga [Thu, 10 Jan 2019 12:34:07 +0000 (13:34 +0100)]
anv/device: fix maximum number of images supported
We had defined MAX_IMAGES as 8, which we used to size the array for
image push constant data. The comment there stated that this was for
gen8, but anv_nir_apply_pipeline_layout runs for all gens and writes
that array, asserting that we don't exceed that number of images,
which imposes a limit of MAX_IMAGES on all gens.
Furthermore, despite this, we are exposing up to 64 images per shader
stage on all gens, gen8 included.
This patch lowers the number of images we expose in gen8 to 8 and
keeps 64 images for gen9+ while making sure that only pre-SKL gens
use push constant space to handle images.
v2:
- <= instead of < in the assert (Eric, Lionel)
- Change the way the assertion is written (Eric)
v3:
- Revert the way the assertion is written to the form it had in v1,
the version in v2 was not equivalent and was incorrect. (Lionel)
v4:
- gen9+ doesn't need push constants for images at all (Jason)
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v3)
(cherry picked from commit
f92c5bc8f3f517f3dadab27c5fcf28a6c2747204)
Jason Ekstrand [Wed, 21 Nov 2018 23:19:37 +0000 (17:19 -0600)]
anv/nir: Rework arguments to apply_pipeline_layout
Instead of taking a whole pipeline (which could be anything!), just take
a physical device and robust_buffer_access boolean. This makes it
easier to verify that only the things in the hash actually affect
pipeline compilation.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
a24654b49d36609b43a5ef6f04453ab284a6ea4f)
Eric Anholt [Wed, 16 Jan 2019 00:02:23 +0000 (16:02 -0800)]
vc4: Don't leak the GPU fd for renderonly usage.
Noticed while debugging V3D -- the ro->gpu_fd was freshly opened in ro
setup, and it needs to stay open until screen close (since it may be used
by renderonly) and should be the same one used by the vc4 screen.
Fixes:
7029ec05e2c7 ("gallium: Add renderonly-based support for pl111+vc4.")
(cherry picked from commit
99ef66c325a99b3e191987d8327e7e4cd4aafcd7)
Dylan Baker [Tue, 15 Jan 2019 19:55:36 +0000 (11:55 -0800)]
meson: allow building dri driver without window system if osmesa is classic
This was already enabled for gallium based osmesa with gallium drivers
in
9d10581897ef7cfa0f6c392e2048cc04357281b9, so do the same for classic
driver with classic osmesa.
Fixes:
cbbd5bb889a2c271a504c379f36a7cb717a85af4
("meson: build classic osmesa")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit
431e9abaaba6386aa7fbc1ec0e2566a3f8999f5d)
Bruce Cherniak [Fri, 4 Jan 2019 20:53:59 +0000 (14:53 -0600)]
gallium/swr: Fix multi-context sync fence deadlock.
Various recreation scenarios lead to API thread getting stuck in
swr_fence_finish(). This is a multi-context issue, whereby one context
overwrites the fence read-value with a previous sync's lesser value.
The fence sync value is supposed to be always increasing.
In swr_fence_cb(), only update the "read" value if the new value is
greater.
(This may seem like we're not waiting on the other context to finish, but
had we needed for it to finish there would have been a wait prior to
submitting a new sync.)
cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
ed7673afd2d1a31bfcec0520743acd2681b462e6)
Pierre Moreau [Wed, 9 Jan 2019 22:03:45 +0000 (23:03 +0100)]
meson: Fix with_gallium_icd to with_opencl_icd
`with_gallium_icd` is never used throughout the different Meson build
files, whereas `with_opencl_icd` tracks whether or not `gallium-opencl`
was set to "icd".
Fixes:
42ea0631f108d82554339530d6c88aa1b448af1e
("meson: build clover")
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
0b736f7fd4852bdea2ac6be9a018a41065252233)
Bas Nieuwenhuizen [Sat, 12 Jan 2019 19:09:23 +0000 (20:09 +0100)]
radv: Set partial_vs_wave for pipelines with just GS, not tess.
Looking at -pro we need to enable it for pipelines with just a
GS too.
This seems to reduce the hangs from
https://bugs.freedesktop.org/show_bug.cgi?id=109242 on a RX 550 to
the point where I can't reproduce, after the false start with the
wd_switch_on_eop patch due to flakiness.
(but people are reporting it does not fix the issue completely for
them on polaris 11)
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
568e7a2998e39263c41ec70ec67bcc5601477781)
Samuel Pitoiset [Thu, 8 Nov 2018 13:00:36 +0000 (14:00 +0100)]
radv: clean up setting partial_es_wave for distributed tess on VI
Only needed when the pipeline actually uses tessellation. I don't
think that changes anything, except improving readability.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
d9d14346c2ba66bfef7ca120ccbcd3201ca32359)
Marek Olšák [Mon, 14 Jan 2019 23:24:08 +0000 (18:24 -0500)]
radeonsi: also apply the GS hang workaround to draws without tessellation
ported from AMDVLK.
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
5183e794affbbbf7dc959332619b0852c21536d6)
Bas Nieuwenhuizen [Mon, 14 Jan 2019 13:44:15 +0000 (14:44 +0100)]
radv: Only use 32 KiB per threadgroup on Stoney.
Causes hangs on some machines.
What works for dEQP-VK.tessellation.shader_input_output.barrier:
- running num_patches = 6 (which limits LDS to 32 KiB)
- running num_patches = 8, and artificially cutting LDS size at 32 KiB.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
76b12fa564a5f48e3f2264718dea0158d0c05b4c)
Andres Gomez [Fri, 11 Jan 2019 14:43:27 +0000 (16:43 +0200)]
bin/get-pick-list.sh: fix redirection in sh
"&>" is bash specific.
Fixes:
e0dbfc99537 ("bin/get-pick-list.sh: warn when commit lists invalid sha")
Cc: Juan A. Suarez <jasuarez@igalia.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit
3ec9ab80b870efffb5ba7c7a00b86b2df729ec6d)
Andres Gomez [Fri, 11 Jan 2019 14:42:25 +0000 (16:42 +0200)]
bin/get-pick-list.sh: fix the oneline printing
"--summary" will also print extended header information such as
creations, renames and mode changes.
Let's just use "--no-patch", which suppresses the diff output.
v2: Use "--no-patch" instead of the "-s" abbreviation (Eric).
Fixes:
559c32d2412 ("bin/get-pick-list.sh: simplify git oneline printing")
Cc: Juan A. Suarez <jasuarez@igalia.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit
716ed41a36037459ed5bfe0775484ac2cbd90707)
Emil Velikov [Tue, 29 Jan 2019 15:10:34 +0000 (15:10 +0000)]
cherry-ignore: spirv: Handle arbitrary bit sizes for deref array indices
stable The commits aren't suitable in their present form.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Tue, 29 Jan 2019 14:58:15 +0000 (14:58 +0000)]
cherry-ignore: radv: Fix multiview depth clears
fixes: This commit requires commits
aeaf8dbd097 and
7484bc894b9 which
did not land in branch.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 17 Jan 2019 11:30:49 +0000 (11:30 +0000)]
docs: add sha256 checksums for 18.3.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 17 Jan 2019 11:24:36 +0000 (11:24 +0000)]
docs: add release notes for 18.3.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 17 Jan 2019 11:15:36 +0000 (11:15 +0000)]
Update version to 18.3.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Rhys Perry [Mon, 17 Dec 2018 15:37:05 +0000 (15:37 +0000)]
ac: split 16-bit ssbo loads that may not be dword aligned
This ends up refactoring visit_load_buffer() a little.
Fixes:
7e7ee826982 ('ac: add support for 16bit buffer loads')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108114
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
bde9f482de69528db5ccf5dd6bbfd8359adfbb19)
Note: this is a backport of the above commit provided by Rhys.
Nicolai Hähnle [Wed, 5 Dec 2018 12:28:03 +0000 (13:28 +0100)]
meson: link LLVM 'native' component when LLVM is available
Linking against LLVM built with BUILD_SHARED_LIBS fails otherwise,
as the component is required for the draw module.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
4275cae95c8cb217d6164dfeeafae7b56484b13d)
Karol Herbst [Fri, 7 Dec 2018 08:44:55 +0000 (09:44 +0100)]
nv50/ir: fix use-after-free in ConstantFolding::visit
opnd() might delete the passed in instruction, but it's used through
i->srcExists() later in visit
v2: use continue instead return
v3: use brackets for the outer if/else chain
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
77944fb2b7c9b40539084f600b5df4fff18e9640)
Jason Ekstrand [Wed, 17 Oct 2018 16:34:32 +0000 (11:34 -0500)]
intel/peephole_ffma: Fix swizzle propagation
The num_components value passed into get_mul_for_src is used to only
compose the parts of the swizzle that we know will be used so we don't
compose invalid swizzle components. However, we had a bug where we
passed the number of components of the add all the way through. For the
given source, we need the number of components read from that source.
In the case where we have a narrow add, say 2 components, that is
sourced from a chain of wider instructions, we may not compose all the
swizzles. All we really need to do is pass through the right number of
components at each level.
Fixes:
2231cf0ba3a "nir: Fix output swizzle in get_mul_for_src"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit
1ede463b6e66eb0a6df5250261810b6985c35eb9)
Andres Gomez [Mon, 7 Jan 2019 14:11:44 +0000 (16:11 +0200)]
glsl/linker: specify proper direction in location aliasing error
The check for location aliasing was always asuming output variables
but this validation is also called for input variables.
Fixes:
e2abb75b0e4 ("glsl/linker: validate explicit locations for SSO programs")
Cc: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
428164d87f8dc1d378236b4913538803653770c6)
Francisco Jerez [Fri, 7 Dec 2018 22:26:23 +0000 (14:26 -0800)]
intel/fs: Respect CHV/BXT regioning restrictions in copy propagation pass.
Currently the visitor attempts to enforce the regioning restrictions
that apply to double-precision instructions on CHV/BXT at NIR-to-i965
translation time. It is possible though for the copy propagation pass
to violate this restriction if a strided move is propagated into one
of the affected instructions. I've only reproduced this issue on a
future platform but it could affect CHV/BXT too under the right
conditions.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
c301f447ea8449804208e414f189c0571e4339a8)
Francisco Jerez [Fri, 7 Dec 2018 22:05:52 +0000 (14:05 -0800)]
intel/eu/gen7: Fix brw_MOV() with DF destination and strided source.
I triggered this bug while prototyping code for a future platform on
IVB. Could be a problem today though if a strided move is
copy-propagated into a type-converting move with DF destination.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
464e79144f8090eb42b8994a983470628c248be0)
Francisco Jerez [Fri, 7 Dec 2018 22:15:50 +0000 (14:15 -0800)]
intel/fs: Fix bug in lower_simd_width while splitting an instruction which was already split.
This seems to be a problem in combination with the lower_regioning
pass introduced by a future commit, which can modify a SIMD-split
instruction causing its execution size to become illegal again. A
subsequent call to lower_simd_width() would hit this bug on a future
platform.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
bc781a0323d719634e29d82b5f14e22db943536e)
Francisco Jerez [Thu, 6 Dec 2018 22:11:34 +0000 (14:11 -0800)]
intel/fs: Implement quad swizzles on ICL+.
Align16 is no longer a thing, so a new implementation is provided
using Align1 instead. Not all possible swizzles can be represented as
a single Align1 region, but some fast paths are provided for
frequently used swizzles that can be represented efficiently in Align1
mode.
Fixes ~90 subgroup quad swap Vulkan CTS tests.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
812ede088f5f6bea4e6fba991bd59d5cce264212)
Francisco Jerez [Sat, 29 Dec 2018 09:44:00 +0000 (01:44 -0800)]
intel/fs: Handle source modifiers in lower_integer_multiplication().
lower_integer_multiplication() implements 32x32-bit multiplication on
some platforms by bit-casting one of the 32-bit sources into two
16-bit unsigned integer portions. This can give incorrect results if
the original instruction specified a source modifier. Fix it by
emitting an additional MOV instruction implementing the source
modifiers where necessary.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
c5f9c0009d5161e059e54a76fbdb910a6c151f9f)
Marek Olšák [Tue, 8 Jan 2019 16:12:05 +0000 (11:12 -0500)]
st/mesa: don't leak pipe_surface if pipe_context is not current
We have found some pipe_surface leaks internally.
This is the same code as surface_destroy in radeonsi.
Ideally, surface_destroy would be in pipe_screen.
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit
e986c1ca1d61bd7492936f43e45996cd4f8bdb61)
Mario Kleiner [Mon, 7 Jan 2019 18:42:29 +0000 (19:42 +0100)]
radeonsi: Fix use of 1- or 2- component GL_DOUBLE vbo's.
With Mesa 18.1, commit
be973ed21f6e, si_llvm_load_input_vs()
changed the number of source 32-bit wide dword components
used for fetching vertex attributes into the vertex shader
from a constant 4 to a variable num_channels number, depending
on input data format, with some special case handling for
input data formats like 64-Bit doubles.
In the case of a GL_DOUBLE input data format with one
or two components though, e.g, submitted via ...
a) glTexCoordPointer(1, GL_DOUBLE, 0, buffer);
b) glTexCoordPointer(2, GL_DOUBLE, 0, buffer);
... the input format would be SI_FIX_FETCH_RG_64_FLOAT,
but no special case handling was implemented for that
case, so in the default path the number of 32-bit
dwords would be set to the number of float input components
derived from info->input_usage_mask. This ends with corrupted
input to the vertex shader, because fetching a 64-bit double
from the vbo requires fetching two 32-bit dwords instead of 1,
and fetching a two double input requires 4 dword fetches
instead of 2, so in these cases the vertex shader receives
incomplete/truncated input data:
a) float v = gl_MultiTexCoord0.x; -> v.x is corrupted.
b) vec2 v = gl_MultiTexCoord0.xy; -> v.x is assigned
correctly, but v.y is corrupted.
This happens with the standard TGSI IR compiled shaders.
Under NIR with R600_DEBUG=nir, we got correct behavior
because the current radeonsi nir code always assigns
info->input_usage_mask = TGSI_WRITEMASK_XYZW, thereby
always fetches 4 dwords regardless of what the shader
actually needs.
Fix this by properly assigning 2 or 4 dword fetches for
one or two component GL_DOUBLE input.
Fixes:
be973ed21f6e ("radeonsi: load the right number of
components for VS inputs and TBOs")
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
5e30e54e057300f65019c927482e633c367963fc)
Rhys Perry [Wed, 9 Jan 2019 11:09:33 +0000 (11:09 +0000)]
ac/nir,radv,radeonsi/nir: use correct indices for interpolation intrinsics
Fixes artifacts in World of Warcraft when Multi-sample Alpha-Test is
enabled with DXVK.
It also fixes artifacts with Fallout 4's god rays with DXVK.
Various piglit interpolateAt*() tests under NIR are also fixed.
v2: formatting fix
update commit message to include Fallout 4 and the Fixes tag
Fixes:
f4e499ec791 ('radv: add initial non-conformant radv vulkan driver')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106595
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
(cherry picked from commit
ee8488ea3b99ad0632e5eac6defcef0264d8782c)
Dylan Baker [Tue, 18 Dec 2018 22:37:52 +0000 (14:37 -0800)]
autotools: Remove tegra vdpau driver
This has never functioned and probably wont ever function, due to the
way gallium media state trackers are architected and the tegra video
decoder is architected.
Cc: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Fixes:
1755f608f5201e0a23f00cc3ea1b01edd07eb6ef
("tegra: Initial support")
(cherry picked from commit
401dca1c73cad4e6ac3137fdd5513e350d060f25)
Lionel Landwerlin [Sun, 23 Dec 2018 17:49:23 +0000 (17:49 +0000)]
anv: flush fast clear colors into compressed surfaces
In the following scenario :
1. Create image format R8G8B8A8_UNORM
2. Create image view format R8G8B8A8_SRGB
3. Clear the view through a sub pass to a particular color
4. Barrier on the image to from color attachment to source transfer
5. Copy the image into a linear buffer to check the content
The step 4 resolving the clear color is unaware of the SRGB format of
the view, because the blorp resolve operations operate on images the
color associated with the resolve will not operate on SRGB format but
UNORM. Leading to the wrong color being written into surfaces.
This change forces a clear color resolve at the end of the render pass
so following resolves won't have to deal with the clear color with a
format that doesn't match the image's format.
On gfxbench vulkan_5_normal 1280x720, this appear to cost us ~0.5fps,
from 49.316 down to 48.949.
v2: Only fast clear resolve when image & view have different formats
(Lionel)
v3: Update warning (Jason)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
add5a2ec92f4b3f7ac8353e5986dc04186a7b6da)
Lionel Landwerlin [Mon, 24 Dec 2018 10:11:59 +0000 (10:11 +0000)]
anv: explictly specify format for blorp ccs/mcs op
Resolve operations can happen when dealing with view (begin/end
subpasses) in which case the view's format needs to apply, not the
image's format.
v2: Relayout arguments of a ccs_op() call (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
366eb656ac6fe677828f20295d8916506552a0e8)
Jason Ekstrand [Sat, 15 Dec 2018 15:57:26 +0000 (09:57 -0600)]
spirv: Sign-extend array indices
The SPIR-V spec was recently updated to clarify that array indices are
treated as signed integers.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit
c59f07684c0c99fad0c246dd4a475f6bef5d3cbc)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/compiler/spirv/vtn_variables.c
Jason Ekstrand [Fri, 14 Dec 2018 00:33:46 +0000 (18:33 -0600)]
anv/apply_pipeline_layout: Set the cursor in lower_res_reindex_intrinsic
The loop through instructions doesn't set the cursor for us so unless we
set it somewhere, we may end up emitting instructions in the wrong
place. The only reason why we haven't been bitten by this in the past
is that it only happens in a few variable pointers cases and the CTS
tests for those don't use much control flow so things were getting
emitted in the correct order by accident.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit
f8992eb5badf91e0d9ad3732d56a4e3d78fd1abf)
Jason Ekstrand [Fri, 14 Dec 2018 16:54:08 +0000 (10:54 -0600)]
spirv: Handle any bit size in vector_insert/extract
This crops up both in the actual SPIR-V VectorInsert/Extract opcodes as
well as various places where we deal with vector derefs.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit
42b2f3e91f6d6c4eead40ef91e5edde68019f23c)
Bas Nieuwenhuizen [Sun, 6 Jan 2019 11:34:24 +0000 (12:34 +0100)]
spirv: Fix matrix parameters in function calls.
They can be handled exactly the same as arrays, we just need to handle
the base type correctly in the switches.
Fixes:
a45b6fb4524 "spirv: Pass SSA values through functions"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109204
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
70ed049cc6a682fba084cf57e06728fa5934881b)
Bas Nieuwenhuizen [Wed, 2 Jan 2019 16:53:41 +0000 (17:53 +0100)]
radv: Fix rasterization precision bits.
Note that these limits are exact, not a "precision is at least x",
as texel coords also get snapped to a multiple of this step size
before filtering.
This fixes CTS tests
dEQP-VK.texture.explicit_lod.2d.sizes.31x55_nearest_linear_mipmap_nearest_repeat
dEQP-VK.texture.explicit_lod.2d.sizes.57x35_nearest_linear_mipmap_nearest_repeat
Fixes:
f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109151
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
3cc940277a45285d9932ed62398d7a54d2afffb8)
Andres Gomez [Mon, 7 Jan 2019 13:50:35 +0000 (15:50 +0200)]
glsl: correct typo in GLSL compilation error message
v2: Add the "fix" tag (Erik).
Fixes:
037f68d81e1 ("glsl: apply align layout qualifier rules to block offsets")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit
0cc01f45e7294122a2ae171b09ac3375b2a75d83)
Bas Nieuwenhuizen [Wed, 5 Dec 2018 10:28:12 +0000 (11:28 +0100)]
anv/android: Do not reject storage images.
We do the ImageFormatProperties check already, and rejecting an usage
flag when both ImageFormatProperties and the WSI (which is Android)
support it is not allowed.
Intel does support storage for some of the support WSI formats, such
as R8G8B8A8_UNORM, and looking at the ISL_SURF_USAGE_DISABLE_AUX_BIT,
the imported images do not have any form of compression that would
prevent this fix.
v2: Also consider STORAGE bit for Gralloc usage bits.
(From Kevin Strasser <kevin.strasser@intel.com>)
Fixes:
053d4c328fa "anv: Implement VK_ANDROID_native_buffer (v9)"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit
110564fdecd0948e7aa9b1a607af7631430092ff)
Bas Nieuwenhuizen [Mon, 24 Dec 2018 14:41:56 +0000 (15:41 +0100)]
radv: Implement buffer stores with less than 4 components.
We started using it in the btoi paths for r32g32b32, and the LLVM IR
checker will complain about it because we end up with intrinsics with
the wrong type extension in the name.
Fixes:
593996bc02 ("radv: implement buffer to image operations for R32G32B32")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
9a45a190ad22849a492506389413046948e0b093)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
Jason Ekstrand [Fri, 4 Jan 2019 17:32:40 +0000 (11:32 -0600)]
intel/blorp: Be more conservative about copying clear colors
In
92eb5bbc68d7324 we attempted to avoid copying clear colors whenever
we weren't doing a resolve. However, this broke MSAA resolves because
we need the clear color in the source. This patch makes blorp much more
conservative such that it only avoids the clear color copy if either
aux_usage == NONE or it's explicitly doing a fast-clear.
Fixes:
92eb5bbc68d7 "intel/blorp: Only copy clear color when doing..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107728
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
(cherry picked from commit
19c608fe43ae7e1578920326690a361ff1be9d88)
Caio Marcelo de Oliveira Filho [Wed, 19 Dec 2018 23:23:28 +0000 (15:23 -0800)]
nir: remove dead code from copy_prop_vars
When copy_prop_vars also took care of dead write handling, intrin was
used as part of store_to_entry. Now it isn't, so this assignment
isn't used really used. Add a comment clarifying what happens to
intrin.
Fixes:
4dfa7adc100 "nir: Remove handling of dead writes from copy_prop_vars"
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
bbf9ee9b18b5917632e6bb74e5859398e6cea224)
Lionel Landwerlin [Thu, 3 Jan 2019 16:18:48 +0000 (16:18 +0000)]
i965: add CS stall on VF invalidation workaround
Even with the previous commit, hangs are still happening. The problem
there is that the VF cache invalidate do happen immediately without
waiting for previous rendering to complete. What happens is that we
invalidate the cache the moment the PIPE_CONTROL is parsed but we
still have old rendering in the pipe which continues to pull data into
the cache with the old high address bits. The later rendering with the
new high address bits then doesn't have the clean cache that it
expects/needs.
v2: Update commit message/explanation with Jason's
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes:
a363bb2cd0e2a1 ("i965: Allocate VMA in userspace for full-PPGTT systems.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072
(cherry picked from commit
31e4c9ce400341df9b0136419b3b3c73b8c9eb7e)
Lionel Landwerlin [Thu, 3 Jan 2019 16:17:04 +0000 (16:17 +0000)]
i965: include draw_params/derived_draw_params for VF cache workaround
These buffers are using VB slots and should be included in the
workaround decision.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes:
a363bb2cd0e2a1 ("i965: Allocate VMA in userspace for full-PPGTT systems.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072
(cherry picked from commit
92b7407090b1f11af49133968b63d583eba9b803)
Dylan Baker [Tue, 1 Jan 2019 03:23:52 +0000 (19:23 -0800)]
meson: Error out if building nouveau and using LLVM without rtti
Nouveau requires rtti. Often LLVM is configured without rtti, and code
with and without cannot be linked safely. Lets just error out if nouveau
is requested and llvm is built without rtti.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109202
Fixes:
c5a97d658ec19cc02719d7f86c1b0715e3d9ffc4
("meson: fix builds against LLVM built without rtti")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
a2596450ac7330c8965c819491038fb1ad454333)
Alexander von Gluck IV [Thu, 27 Dec 2018 20:41:47 +0000 (20:41 +0000)]
egl/haiku: Fix reference to disp vs dpy
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes:
00992700c9a812a54563 "egl: set the EGLDevice when creating a display"
(cherry picked from commit
1b97a72328b7b549aa8d050495f504815444c0dd)
Timothy Arceri [Fri, 14 Dec 2018 04:36:02 +0000 (15:36 +1100)]
tgsi/scan: correctly walk instructions in tgsi_scan_tess_ctrl()
The previous code used a do while loop and continues after walking
a nested loop/if-statement. This means we end up evaluating the
last instruction from the nested block against the while condition
and potentially exit early if it matches the exit condition of the
outer block.
Fixes:
386d165d8d09 ("tgsi/scan: add a new pass that analyzes tess factor writes")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
4dda4457504ee5cafa0388543620d4598b8561cf)
Timothy Arceri [Fri, 14 Dec 2018 04:09:38 +0000 (15:09 +1100)]
tgsi/scan: fix loop exit point in tgsi_scan_tess_ctrl()
This just happened not to crash/assert because all loops have at
least 1 if-statement and due to a second bug we end up matching
the same ENDIF to exit both the iteration over the if-statment
and the loop.
The second bug is fixed in the following patch.
Fixes:
386d165d8d09 ("tgsi/scan: add a new pass that analyzes tess factor writes")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
dd061eb0442a25cad0cc775103ae31d62280fa44)
Bas Nieuwenhuizen [Sun, 30 Dec 2018 22:37:11 +0000 (23:37 +0100)]
radv: Do a cache flush if needed before reading predicates.
This caused random failures for two conditional rendering tests:
dEQP-VK.conditional_rendering.draw_clear.draw.update_with_rendering_discard
dEQP-VK.conditional_rendering.draw_clear.draw.update_with_rendering_no_discard
These wrote the predicate with the vertex shader, did a barrier and then
started the conditional rendering. However the cache flushes for the barrier
only happen on first draw, so after the predicate has been read.
Fixes:
e45ba51ea45 "radv: add support for VK_EXT_conditional_rendering"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
8c93ef5de98a90a93434d351c769f3c06f206397)
Dylan Baker [Tue, 4 Dec 2018 21:52:19 +0000 (13:52 -0800)]
meson: Override C++ standard to gnu++11 when building with altivec on ppc64
Otherwise there will be symbol collisions for the vector name.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108943
Distro Bug: https://bugs.gentoo.org/673622
Fixes:
42ea0631f108d82554339530d6c88aa1b448af1e
("meson: build clover")
Acked-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit
133a5b838306e25b469cc514ba2ea92b4e6ce4b5)
Dave Airlie [Thu, 27 Dec 2018 06:09:19 +0000 (16:09 +1000)]
virgl/vtest: fix front buffer flush with protocol version 0.
Older versions of virglrenderer before
33da7361aec486290df0aec4ad8dfa8ff6adde2c
in vtest mode, misrender gears.
Fixes:
9d81cd8e7c (virgl: Pass resource size and transfer offsets)
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit
d1ce7eba8b056bfd7d8f29cc0f583777a7ee30e5)
Eric Anholt [Thu, 20 Dec 2018 16:12:50 +0000 (08:12 -0800)]
gallium/ttn: Fix setup of outputs_written.
We need a 64-bit value, otherwise we only handle the low 32, and happen to
sign-extend to claim to write all varying slots if VARYING_SLOT_VAR2 was
used.
Fixes:
4d0b2c7aaac3 ("ttn: Update shader->info as we generate code.")
Reviewed-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
7d7ecfbcbc2236ba76d9ad9dc7c589ce5a6bfa32)
Lionel Landwerlin [Mon, 3 Dec 2018 18:40:10 +0000 (18:40 +0000)]
anv: don't do partial resolve on layer > 0
We've made the choice not to use fast clears on layer > 0 with
multilayer images. This is partly because we would need to store
multiple clear colors for each layer, making the existing memory
layout, already including aux surfaces, fast clear color, image state,
etc... even more complex.
Partial resolves are the operations transfering the clear colors into
the auxiliary buffers. This operation is currently implemented in
Blorp by loading the clear color from the image's BO, into a shader
that then samples from the auxiliary buffer and writes the color only
if it isn't there already.
The problem here is that because we store only one clear color for all
layers and it is used for partial resolves. If you trigger a partial
clear on a layer > 0, then you're likely to deal with a color that is
not what you actually want. In the particular issues below, we have
multiple layers, each cleared with a different color but the partial
resolve just writes the wrong color into the auxiliary buffers for
layers > 0.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108910
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
e2ae5f2f0a0dbdae08e026b88e30552728c4abd6)
Axel Davy [Mon, 3 Dec 2018 20:24:54 +0000 (21:24 +0100)]
st/nine: Add src reference to nine_context_range_upload
Just like nine_context_box_upload, nine_context_range_upload
should reference the src, which holds the ram source buffer.
Fixes: https://github.com/iXit/Mesa-3D/issues/327
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
104681c5d528a823a3fdc3f7d9c6f8133c27201c)
Axel Davy [Mon, 3 Dec 2018 20:15:47 +0000 (21:15 +0100)]
st/nine: Bind src not dst in nine_context_box_upload
nine_context_box_upload uploads a ram buffer (from src)
to a pipe_resource (dst).
We already have a refcount on the pipe_resource,
what needs to be protected from release is the ram buffer,
thus a reference to src.
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
42d672fa6a766363e5703f119607f7c7975918aa)
Axel Davy [Sun, 25 Nov 2018 13:37:53 +0000 (14:37 +0100)]
st/nine: Fix volumetexture dtor on ctor failure
The dtor is called on allocation failure,
thus we must check the volumes are allocated
before trying to release them.
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
f91f748fabd7fec8f571124df23296c07102a983)
Alex Deucher [Thu, 20 Dec 2018 15:11:01 +0000 (10:11 -0500)]
pci_ids: add new VegaM pci id
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
516160d717b81141a65a03060ac440a1cad8ae94)