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Roman Tereshin [Wed, 30 May 2018 22:10:04 +0000 (22:10 +0000)]
[GlobalISel][AArch64] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) call w/o fixing bugs
This is to make it clear what kind of bugs the LegalizerInfo::verifier
is able to catch and test its output
Reviewers: aemerson, qcolombet
Reviewed By: aemerson
Differential Revision: https://reviews.llvm.org/D46338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333597
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Joel E. Denny [Wed, 30 May 2018 21:07:27 +0000 (21:07 +0000)]
Revert r333584: [lit] Report line number for failed RUN command
It breaks test-suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333592
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Florian Hahn [Wed, 30 May 2018 21:00:18 +0000 (21:00 +0000)]
[TableGen] Avoid leaking TreePatternNodes by using shared_ptr.
By using std::shared_ptr for TreePatternNode, we can avoid leaking them.
Reviewers: craig.topper, dsanders, stoklund, tstellar, zturner
Reviewed By: dsanders
Differential Revision: https://reviews.llvm.org/D47463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333591
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Jonas Devlieghere [Wed, 30 May 2018 20:47:18 +0000 (20:47 +0000)]
[ADT] Add unit test for PrintHTMLEscaped
Add unit tests for PrintHTMLEscaped which was added in r333565.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333590
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Daniel Neilson [Wed, 30 May 2018 20:02:56 +0000 (20:02 +0000)]
[IRBuilder] Add APIs for creating calls to atomic memmove and memset intrinsics. (NFC)
Summary:
Creating the IRBuilder methods:
CreateElementUnorderedAtomicMemSet
CreateElementUnorderedAtomicMemMove
These mirror the methods that create calls to the regular (non-atomic) memmove and
memset intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333588
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Simon Pilgrim [Wed, 30 May 2018 19:50:26 +0000 (19:50 +0000)]
Fix Wdocumentation warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333586
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Joel E. Denny [Wed, 30 May 2018 19:42:27 +0000 (19:42 +0000)]
[lit] Report line number for failed RUN command
(Relands r330755 (reverted in r330848) with fix for PR37239.)
When debugging test failures with -vv (or -v in the case of the
internal shell), this makes it easier to locate the RUN line that
failed. For example, clang's test/Driver/linux-ld.c has 892 total RUN
lines, and clang's test/Driver/arm-cortex-cpus.c has 424 RUN lines
after concatenation for line continuations.
When reading the generated shell script, this also makes it easier to
locate the RUN line that produced each command.
To support reporting RUN line numbers in the case of the internal
shell, this patch extends the internal shell to support the null
command, ":", except pipelines are not supported.
To support reporting RUN line numbers in the case of windows cmd.exe
as the external shell, this patch extends -vv to set "echo on" instead
of "echo off" in bat files. (Support for windows cmd.exe as a lit
external shell will likely be dropped later, but I found out too
late.)
Reviewed By: delcypher, asmith, stella.stamenova, jmorse, lebedev.ri, rnk
Differential Revision: https://reviews.llvm.org/D44598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333584
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Benjamin Kramer [Wed, 30 May 2018 19:31:11 +0000 (19:31 +0000)]
[CalledValuePropagation] Just use a sorted vector instead of a set.
The set properties are never used, so a vector is enough. No
functionality change intended.
While there add some std::moves to SparseSolver.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333582
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Peter Collingbourne [Wed, 30 May 2018 19:30:39 +0000 (19:30 +0000)]
llvm-objcopy: Set sh_link to 0 on unrecognized symtab-linked sections.
Per discussion on the generic-abi mailing list:
https://groups.google.com/forum/#!topic/generic-abi/MPr8TVtnVn4
An object file manipulation tool must either write out a symbol
table with the same number of entries as the original symbol table
and in the same order, or if this is impossible, refuse to operate
on the object file if it has unrecognized sections that are linked
to the symtab section. However, existing tools (namely GNU strip,
GNU objcopy and ld.{bfd,gold,lld} -r) do not comply with this at
present: they change symbol table indexes and set sh_link to 0 on
the unrecognized symtab-linked sections.
We intend to use the latter as a (temporary) signal that a tool has
operated on a proposed new symtab-linked section and invalidated the
symbol table indexes. However, llvm-objcopy currently keeps sh_link
pointing to the new symtab section. This patch changes llvm-objcopy
to set sh_link to 0 to match the behaviour of the other tools.
Differential Revision: https://reviews.llvm.org/D47404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333581
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Simon Pilgrim [Wed, 30 May 2018 19:16:59 +0000 (19:16 +0000)]
[X86][SSE] Pulled out splat detection helper from LowerScalarVariableShift (NFCI)
Created the IsSplatValue helper from the splat detection code in LowerScalarVariableShift as a first NFC step towards improving support for splat rotations, which is an extension of PR37426.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333580
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Galina Kistanova [Wed, 30 May 2018 18:51:08 +0000 (18:51 +0000)]
Reverted r333424 as it broke multiple build bots and left unfixed for a long time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333578
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Roman Tereshin [Wed, 30 May 2018 18:45:32 +0000 (18:45 +0000)]
[GlobalISel][Legalizer] LegalizerInfo verifier: check rules cover type indices
This commit adds a simple verifier that tracks type indices being
touched by legalization rules' builders.
Every target will now have an opportunity to call
LegalizerInfo::verify(...) at the end of its derived LegalizerInfo's
constructor and check there are no obvious mistakes like checking only
first type for an opcode that has more than one type index and therefore
implicitly declaring any type for the second (and higher) type index
legal.
The check is only ran in assert builds and should have very minor
performance impact in assert builds and none in release builds.
This commit does not add LegalizerInfo::verify(...) calls to
target-specific legalizers, look for separate commits for that.
This commit also doesn't make the verification errors fatal, only
produces an error message, look for a later commit that does.
Reviewers: aemerson, qcolombet
Reviewed By: aemerson
Differential Revision: https://reviews.llvm.org/D46338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333576
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Craig Topper [Wed, 30 May 2018 18:30:44 +0000 (18:30 +0000)]
[X86] Update the fast-isel tests for _mm_rcp_ss, _mm_rsqrt_ss, and _mm_sqrt_ss to match clang codegen after r333572.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333573
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Jonas Devlieghere [Wed, 30 May 2018 17:47:11 +0000 (17:47 +0000)]
[dsymutil] Escape HTML special characters in plist.
When printing string in the Plist, we weren't escaping the characters
which lead to invalid XML. This patch adds the escape logic to
StringExtras.
rdar://
39785334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333565
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Roman Tereshin [Wed, 30 May 2018 16:54:01 +0000 (16:54 +0000)]
[GlobalISel][Legalizer] NFC mostly reducing LegalizeRuleSet's methods' inter-dependecies
Making LegalizeRuleSet's implementation a little more dumb and
straightforward to make it easier to read and change, in particular in
order to add the initial version of LegalizerInfo verifier
Reviewers: aemerson, qcolombet
Reviewed By: aemerson
Differential Revision: https://reviews.llvm.org/D46338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333562
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Simon Pilgrim [Wed, 30 May 2018 16:29:06 +0000 (16:29 +0000)]
[X86][AVX512BW] Fixed check prefix copy+paste typo in avx512bw-intrinsics.ll
Prefix was for AVX512F instead of AVX512BW
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333560
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Mark Searles [Wed, 30 May 2018 16:27:57 +0000 (16:27 +0000)]
[AMDGPU][Waitcnt] Fix build error: unused variable 'SWaitInst'
https://reviews.llvm.org/rL333556 caused a buildbot failure.
See http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/21876/steps/build_Lld/logs/stdio
/Users/buildslave/as-bldslv9/lld-x86_64-darwin13/llvm.src/lib/Target/AMDGPU/SIInsertWaitcnts.cpp:2007:10: error: unused variable 'SWaitInst' [-Werror,-Wunused-variable]
auto SWaitInst = BuildMI(EntryBB, EntryBB.getFirstNonPHI(),
The unused variable was for debugging purposes; removing that piece of code
to fix the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333559
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Matt Arsenault [Wed, 30 May 2018 16:17:51 +0000 (16:17 +0000)]
AMDGPU: Use better alignment for kernarg lowering
This was just emitting loads with the ABI alignment
for the raw type. The true alignment is often better,
especially when an illegal vector type was scalarized.
The better alignment allows using a scalar load
more often.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333558
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Karl-Johan Karlsson [Wed, 30 May 2018 15:56:46 +0000 (15:56 +0000)]
[ValueTracking] Fix endless recursion in isKnownNonZero()
Summary:
The isKnownNonZero() function have checks that abort the recursion when
it reaches the specified max depth. However one of the recursive calls
was placed before the max depth check was done, resulting in a endless
recursion that eventually triggered a segmentation fault.
Fixed the problem by moving the max depth check above the first
recursive call.
Reviewers: Prazek, nlopes, spatel, craig.topper, hfinkel
Reviewed By: hfinkel
Subscribers: hfinkel, bjope, llvm-commits
Differential Revision: https://reviews.llvm.org/D47531
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333557
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Mark Searles [Wed, 30 May 2018 15:47:45 +0000 (15:47 +0000)]
[AMDGPU][Waitcnt] Fix handling of loops with many bottom blocks
In terms of waitcnt insertion/if necessary, the waitcnt pass forces convergence
for a loop. Previously, that kicked if greater than 2 passes over a loop, which
doesn't account for loop with many bottom blocks. So, increase the threshold to
(n+1), where n is the number of bottom blocks. This gives the pass an
opportunity to consider the contribution of each bottom block, to the overall
loop, before the forced convergence potentially kicks in.
Differential Revision: https://reviews.llvm.org/D47488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333556
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Gabor Buella [Wed, 30 May 2018 15:25:16 +0000 (15:25 +0000)]
[X86] Lowering FMA intrinsics to native IR (LLVM part)
Support for Clang lowering of fused intrinsics. This patch:
1. Removes bindings to clang fma intrinsics.
2. Introduces new LLVM unmasked intrinsics with rounding mode:
int_x86_avx512_vfmadd_pd_512
int_x86_avx512_vfmadd_ps_512
int_x86_avx512_vfmaddsub_pd_512
int_x86_avx512_vfmaddsub_ps_512
supported with a new intrinsic type (INTR_TYPE_3OP_RM).
3. Introduces new x86 fmaddsub/fmsubadd folding.
4. Introduces new tests for code emitted by sequentions introduced in Clang part.
Patch by tkrupa
Reviewers: craig.topper, sroland, spatel, RKSimon
Reviewed By: craig.topper, RKSimon
Differential Revision: https://reviews.llvm.org/D47443
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333554
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Daniel Neilson [Wed, 30 May 2018 14:43:39 +0000 (14:43 +0000)]
[AliasSet] Teach the alias set how to handle atomic memcpy/memmove/memset
Summary:
The atomic variants of the memcpy/memmove/memset intrinsics can be treated
the same was as the regular forms, with respect to aliasing. Update the
AliasSetTracker to treat the atomic forms the same was as the regular forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333551
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Alexandros Lamprineas [Wed, 30 May 2018 14:38:50 +0000 (14:38 +0000)]
[InstCombine, ARM, AArch64] Convert table lookup to shuffle vector
Turning a table lookup intrinsic into a shuffle vector instruction
can be beneficial. If the mask used for the lookup is the constant
vector {7,6,5,4,3,2,1,0}, then the back-end generates byte reverse
instructions instead.
Differential Revision: https://reviews.llvm.org/D46133
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333550
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Simon Pilgrim [Wed, 30 May 2018 14:36:41 +0000 (14:36 +0000)]
[X86][AVX512] Replace -cpu=knl with -mattr=+avx512f for avx512-intrinsics tests
It was noticed on D47377 that these tests were being unnecessarily affected by scheduler changes.
This adds vzeroupper at the end of some tests as we lose the 'FeatureFastPartialYMMorZMMWrite' feature from KNL, since Skylake+ don't support this its probably better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333549
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Simon Pilgrim [Wed, 30 May 2018 14:11:57 +0000 (14:11 +0000)]
[X86][SSE] Remove unnecessary -cpu from sttni tests
It was noticed on D47377 that these tests (for PR37246) were being unnecessarily affected by scheduler changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333546
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Simon Pilgrim [Wed, 30 May 2018 14:01:21 +0000 (14:01 +0000)]
[X86][SSE] Replace -cpu with equivalent -mattr for vec_cast tests
It was noticed on D47377 that these tests were being unnecessarily affected by scheduler changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333545
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Amaury Sechet [Wed, 30 May 2018 13:45:43 +0000 (13:45 +0000)]
[ARM] Remove code handling ADDC/ADDE/SUBC/SUBE
Summary: This code is now dead as the ARM backend uses ADDCARRY/SUBCARRY/SETCCCARRY .
Reviewers: rogfer01, efriedma, rengolin, javed.absar
Subscribers: kristof.beyls, chrib, llvm-commits
Differential Revision: https://reviews.llvm.org/D47413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333544
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Krzysztof Parzyszek [Wed, 30 May 2018 13:45:34 +0000 (13:45 +0000)]
[Hexagon] Use vector align-left when shift amount fits in 3 bits
This saves an instruction because for align-right the shift amount
would need to be put in a register first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333543
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Simon Dardis [Wed, 30 May 2018 13:21:13 +0000 (13:21 +0000)]
[mips] Correct the definition of CTC2/CFC2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333542
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Simon Dardis [Wed, 30 May 2018 13:16:17 +0000 (13:16 +0000)]
[mips] Correct the predicates of microMIPS compact branch instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333541
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Simon Dardis [Wed, 30 May 2018 12:40:53 +0000 (12:40 +0000)]
[mips] Sink PredicateControl further down the class hierarchy.
Previously PredicateControl in some cases was a member of <X>Inst classes
for some X (DSP, EVA) or was in more irregular place in the hierarchry
for any given instruction.
This patch moves PredicateControl down to the root so that it is consistently
available. Then correct the base class of microMIPS instructions as using
EncodingPredicates instead of the general Predicates field of Instruction.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D47526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333536
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Simon Dardis [Wed, 30 May 2018 11:33:35 +0000 (11:33 +0000)]
[mips] Correct the predicates of arithmetic and logic instructions.
As part of this effort, duplicate and correct the predicates of some
aliases. Also disable code generation of some short form instructions
for FastISel, as it would otherwise reject them.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D47075
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333530
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Ilya Biryukov [Wed, 30 May 2018 10:40:11 +0000 (10:40 +0000)]
[YAML] Quote multiline string scalars
Summary:
Otherwise, the YAML parser breaks when trying to read them back in
'key: multiline_string_value' cases.
This patch fixes a problem when serializing structs which contain multi-line strings.
E.g., if we try to serialize the following struct
```
{ "key1": "first line\nsecond line",
"key2": "another string" }`
```
Before this patch, we got the YAML output that failed to parse:
```
key1: first line
second line
key2: another string
```
After the patch, we get:
```
key1: 'first line
second line'
key2: another string
```
Reviewers: sammccall
Reviewed By: sammccall
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333527
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Tim Northover [Wed, 30 May 2018 09:54:59 +0000 (09:54 +0000)]
AArch64: print correct annotation for ADRP addresses.
The immediate on an ADRP MCInst needs to be multiplied by 0x1000 to obtain the
actual PC-offset that will be calculated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333525
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Sander de Smalen [Wed, 30 May 2018 09:54:19 +0000 (09:54 +0000)]
[AArch64][AsmParser] Fix segfault on illegal fpimm.
Floating point immediate combining a negative sign and
a hexadecimal number, e.g. #-0x0 caused the compiler to crash.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: javed.absar
Differential Revision: https://reviews.llvm.org/D47483
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333524
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Daniel Cederman [Wed, 30 May 2018 09:52:18 +0000 (09:52 +0000)]
[Sparc] Treat %fxx registers with value type Other as single precision
They get type Other when used in the clobber list in inline assembly.
This fixes tests fp128.ll and float.ll that failed after r333512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333523
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Hans Wennborg [Wed, 30 May 2018 09:04:57 +0000 (09:04 +0000)]
Set underlying type for enum with GNU_PROPERTY_X86_FEATURE_1_AND constant
The constant was causing a -Wc++11-narrowing error when compiled with
clang-cl (see PR30776).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333520
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Serge Pavlov [Wed, 30 May 2018 09:01:12 +0000 (09:01 +0000)]
Revert commit 333506
It looks like this commit is responsible for the fail:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/24382.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333518
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Daniel Cederman [Wed, 30 May 2018 06:07:55 +0000 (06:07 +0000)]
[Sparc] Select correct register class for FP register constraints
Summary: The fX version of floating-point registers only supports
single precision. We need to map the name to dX for doubles and qX
for long doubles if we want getRegForInlineAsmConstraint() to be
able to pick the correct register class.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D47258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333512
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Craig Topper [Wed, 30 May 2018 05:25:59 +0000 (05:25 +0000)]
[X86] Add unmasked AVX512VNNI instrinsics. Use a select in IR instead.
A future patch will remove the old masked intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333508
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Serge Pavlov [Wed, 30 May 2018 05:13:19 +0000 (05:13 +0000)]
Use uniform mechanism for OOM errors handling
This is a recommit of r333390, which was reverted in r333395, because it
caused cyclic dependency when building shared library `LLVMDemangle.so`.
In this commit `ItaniumDemangler.cpp` was not changed.
The original commit message is below.
In r325551 many calls of malloc/calloc/realloc were replaces with calls of
their safe counterparts defined in the namespace llvm. There functions
generate crash if memory cannot be allocated, such behavior facilitates
handling of out of memory errors on Windows.
If the result of *alloc function were checked for success, the function was
not replaced with the safe variant. In these cases the calling function made
the error handling, like:
T *NewElts = static_cast<T*>(malloc(NewCapacity*sizeof(T)));
if (NewElts == nullptr)
report_bad_alloc_error("Allocation of SmallVector element failed.");
Actually knowledge about the function where OOM occurred is useless. Moreover
having a single entry point for OOM handling is convenient for investigation
of memory problems. This change removes custom OOM errors handling and
replaces them with calls to functions `llvm::safe_*alloc`.
Declarations of `safe_*alloc` are moved to a separate include file, to avoid
cyclic dependency in SmallVector.h
Differential Revision: https://reviews.llvm.org/D47440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333506
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Hiroshi Inoue [Wed, 30 May 2018 04:48:29 +0000 (04:48 +0000)]
[PowerPC] fix broken JIT-compiled code with tail call optimization
The relocation for branch instructions in the dynamic loader of ExecutionEngine assumes branch instructions with R_PPC64_REL24 relocation type are only bl. However, with the tail call optimization, b instructions can be also used to jump into another function.
This patch makes the relocation to keep bits in the branch instruction other than the jump offset to avoid relocation rewrites a b instruction into bl.
Differential Revision: https://reviews.llvm.org/D47456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333502
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Sam Clegg [Wed, 30 May 2018 03:37:26 +0000 (03:37 +0000)]
MC: Remove redundant substr() call
Differential Revision: https://reviews.llvm.org/D47047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333496
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Sam Clegg [Wed, 30 May 2018 03:26:28 +0000 (03:26 +0000)]
Fix use of `echo` command in test script
On win32 we use lit's executeBuiltinEcho to implement the
echo command and this version only currently supports flags
that are separate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333495
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Sam Clegg [Wed, 30 May 2018 02:57:20 +0000 (02:57 +0000)]
[WebAssembly] MC: Add compile-twice test and fix corresponding bug
Differential Revision: https://reviews.llvm.org/D47398
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333494
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Chandler Carruth [Wed, 30 May 2018 02:46:45 +0000 (02:46 +0000)]
[PM/LoopUnswitch] When using the new SimpleLoopUnswitch pass, schedule
loop-cleanup passes at the beginning of the loop pass pipeline, and
re-enqueue loops after even trivial unswitching.
This will allow us to much more consistently avoid simplifying code
while doing trivial unswitching. I've also added a test case that
specifically shows effective iteration using this technique.
I've unconditionally updated the new PM as that is always using the
SimpleLoopUnswitch pass, and I've made the pipeline changes for the old
PM conditional on using this new unswitch pass. I added a bunch of
comments to the loop pass pipeline in the old PM to make it more clear
what is going on when reviewing.
Hopefully this will unblock doing *partial* unswitching instead of just
full unswitching.
Differential Revision: https://reviews.llvm.org/D47408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333493
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Lang Hames [Wed, 30 May 2018 02:40:40 +0000 (02:40 +0000)]
[ORC] Fix an ambiguous make_unique call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333492
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Lang Hames [Wed, 30 May 2018 01:57:45 +0000 (01:57 +0000)]
[ORC] Update JITCompileCallbackManager to support multi-threaded code.
Previously JITCompileCallbackManager only supported single threaded code. This
patch embeds a VSO (see include/llvm/ExecutionEngine/Orc/Core.h) in the callback
manager. The VSO ensures that the compile callback is only executed once and that
the resulting address cached for use by subsequent re-entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333490
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Shiva Chen [Wed, 30 May 2018 01:16:36 +0000 (01:16 +0000)]
[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table
Resolving fixup_riscv_call by assembler when the linker relaxation diabled
and the function and callsite within the same compile unit.
And also adding static_assert after Infos array declaration
to avoid missing any new fixup in MCFixupKindInfo in the future.
Differential Revision: https://reviews.llvm.org/D47126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333487
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Diego Caballero [Tue, 29 May 2018 23:10:44 +0000 (23:10 +0000)]
[VPlan] Replace LLVM_ATTRIBUTE_USED with ifndef NDEBUG
Minor replacement. LLVM_ATTRIBUTE_USED was introduced to silence
a warning but using #ifndef NDEBUG makes more sense in this case.
Reviewers: dblaikie, fhahn, hsaito
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D47498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333476
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Craig Topper [Tue, 29 May 2018 22:52:09 +0000 (22:52 +0000)]
[X86] Remove some of the extractelts from the new MOVSS+FMA patterns.
We only need the extractelt that corresponds to the register we're trying to insert back into. We can't guarantee the others haven't been optimized out depending on how those operands were produced.
So instead just look for an FR32/FR64 input and emit a COPY_TO_REGCLASS to VR128 in the output pattern. This matches what we do for ADD/SUB/MUL/DIV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333473
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Craig Topper [Tue, 29 May 2018 20:46:27 +0000 (20:46 +0000)]
[X86] Use VR128X instead of VR128 in EVEX instruction patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333464
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Craig Topper [Tue, 29 May 2018 20:46:26 +0000 (20:46 +0000)]
[X86] Rename the operands in the recently introduced MOVSS+FMA patterns so that the operand names in the output pattern are always in 1, 2, 3 order since those are the operand names in the instruction.
The order should be controlled in the input pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333463
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Sam Clegg [Tue, 29 May 2018 20:16:47 +0000 (20:16 +0000)]
Fix build error introduced in rL333459
The DEBUG macro was renamed LLVM_DEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333462
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Chandler Carruth [Tue, 29 May 2018 20:15:38 +0000 (20:15 +0000)]
[LoopInstSimplify] Re-implement the core logic of loop-instsimplify to
be both simpler and substantially more efficient.
Rather than use a hand-rolled iteration technique that isn't quite the
same as RPO, use the pre-built RPO loop body traversal utility.
Once visiting the loop body in RPO, we can assert that we visit defs
before uses reliably. When this is the case, the only need to iterate is
when simplifying a def that is used by a PHI node along a back-edge.
With this patch, the first pass over the loop body is just a complete
simplification of every instruction across the loop body. When we
encounter a use of a simplified instruction that stems from a PHI node
in the loop body that has already been visited (due to some cyclic CFG,
potentially the loop itself, or a nested loop, or unstructured control
flow), we recall that specific PHI node for the second iteration.
Nothing else needs to be preserved from iteration to iteration.
On the second and later iterations, only instructions known to have
simplified inputs are considered, each time starting from a set of PHIs
that had simplified inputs along the backedges.
Dead instructions are collected along the way, but deleted in a batch at
the end of each iteration making the iterations themselves substantially
simpler. This uses a new batch API for recursively deleting dead
instructions.
This alsa changes the routine to visit subloops. Because simplification
is fundamentally transitive, we may need to visit the entire loop body,
including subloops, to handle knock-on simplification.
I've added a basic test file that helps demonstrate that all of these
changes work. It includes both straight-forward loops with
simplifications as well as interesting PHI-structures, CFG-structures,
and a nested loop case.
Differential Revision: https://reviews.llvm.org/D47407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333461
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Craig Topper [Tue, 29 May 2018 20:04:10 +0000 (20:04 +0000)]
[X86] Fix a potential crash that occur after r333419.
The code could issue a truncate from a small type to larger type. We need to extend in that case instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333460
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Sam Clegg [Tue, 29 May 2018 19:58:59 +0000 (19:58 +0000)]
[WebAssembly] Add more error checking to object file parsing
This should address some of the assert failures the fuzzer has been
finding such as:
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=6719
Differential Revision: https://reviews.llvm.org/D47086
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333459
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Matt Arsenault [Tue, 29 May 2018 19:35:53 +0000 (19:35 +0000)]
AMDGPU: Fix broken check lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333458
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Matt Arsenault [Tue, 29 May 2018 19:35:46 +0000 (19:35 +0000)]
AMDGPU: Fix typo in option description
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333457
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Matt Arsenault [Tue, 29 May 2018 19:35:00 +0000 (19:35 +0000)]
AMDGPU: Round up kernel argument allocation size
AFAIK the driver's allocation will actually have to round this
up anyway. It is useful to track the rounded up size, so that
the end of the kernel segment is known to be dereferencable so
a wider s_load_dword can be used for a short argument at the end
of the segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333456
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Sameer AbuAsal [Tue, 29 May 2018 19:34:54 +0000 (19:34 +0000)]
[RISCV] Add peepholes for Global Address lowering patterns
Summary:
Base and offset are always separated when a GlobalAddress node is lowered
(rL332641) as an optimization to reduce instruction count. However, this
optimization is not profitable if the Global Address ends up being used in only
instruction.
This patch adds peephole optimizations that merge an offset of
an address calculation into the LUI %%hi and ADD %lo of the lowering sequence.
The peephole handles three patterns:
1) ADDI (ADDI (LUI %hi(global)) %lo(global)), offset
--->
ADDI (LUI %hi(global + offset)) %lo(global + offset).
This generates:
lui a0, hi (global + offset)
add a0, a0, lo (global + offset)
Instead of
lui a0, hi (global)
addi a0, hi (global)
addi a0, offset
This pattern is for cases when the offset is small enough to fit in the
immediate filed of ADDI (less than 12 bits).
2) ADD ((ADDI (LUI %hi(global)) %lo(global)), (LUI hi_offset))
--->
offset = hi_offset << 12
ADDI (LUI %hi(global + offset)) %lo(global + offset)
Which generates the ASM:
lui a0, hi(global + offset)
addi a0, lo(global + offset)
Instead of:
lui a0, hi(global)
addi a0, lo(global)
lui a1, (offset)
add a0, a0, a1
This pattern is for cases when the offset doesn't fit in an immediate field
of ADDI but the lower 12 bits are all zeros.
3) ADD ((ADDI (LUI %hi(global)) %lo(global)), (ADDI lo_offset, (LUI hi_offset)))
--->
offset = global + offhi20<<12 + offlo12
ADDI (LUI %hi(global + offset)) %lo(global + offset)
Which generates the ASM:
lui a1, %hi(global + offset)
addi a1, %lo(global + offset)
Instead of:
lui a0, hi(global)
addi a0, lo(global)
lui a1, (offhi20)
addi a1, (offlo12)
add a0, a0, a1
This pattern is for cases when the offset doesn't fit in an immediate field
of ADDI and both the lower 1 bits and high 20 bits are non zero.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos,
niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333455
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Daniel Neilson [Tue, 29 May 2018 19:23:50 +0000 (19:23 +0000)]
[BasicAA] Teach the analysis about atomic memcpy
Summary:
A simple change to derive mod/ref info from the atomic memcpy
intrinsic in the same way as from the regular memcpy intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333454
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Douglas Yung [Tue, 29 May 2018 19:21:22 +0000 (19:21 +0000)]
Update CodeView register names in a test that was missed in r333421.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333453
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Konstantin Zhuravlyov [Tue, 29 May 2018 19:09:13 +0000 (19:09 +0000)]
AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as
it is set by CP
Differential Revision: https://reviews.llvm.org/D47392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333451
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Florian Hahn [Tue, 29 May 2018 18:34:42 +0000 (18:34 +0000)]
[TableGen] Use explicit constructor for InstMemo
This should fix a few buildbot failures with old
GCC versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333448
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Eli Friedman [Tue, 29 May 2018 18:17:16 +0000 (18:17 +0000)]
[ARM] Enable SETCCCARRY lowering for Thumb1.
We've had Thumb1 support for ARMISD::SUBE for a while now, so this just
works. Reduces codesize a bit for 64-bit integer comparisons.
Differential Revision: https://reviews.llvm.org/D47387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333445
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Matt Arsenault [Tue, 29 May 2018 18:06:50 +0000 (18:06 +0000)]
IRBuilder: Add overload for intrinsics without args
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333443
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Matt Arsenault [Tue, 29 May 2018 17:42:50 +0000 (17:42 +0000)]
AMDGPU: Pass function directly instead of MachineFunction
These functions just query the underlying IR function,
so pass it directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333442
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Matt Arsenault [Tue, 29 May 2018 17:42:38 +0000 (17:42 +0000)]
AMDGPU: Add nuw to add off of kernarg ptr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333441
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Matt Arsenault [Tue, 29 May 2018 17:42:26 +0000 (17:42 +0000)]
DAG: Remove redundant version of getRegisterTypeForCallingConv
There seems to be no real reason to have these separate copies.
The existing implementations just copy each other for x86.
For Mips there is a subtle difference, which is just a bug
since it changes based on the context where which one was called.
Dropping this version, all tests pass. If I try to merge them
to match the removed version, a test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333440
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Tom Stellard [Tue, 29 May 2018 17:41:59 +0000 (17:41 +0000)]
AMDGPU: Split R600 MCInst lowering into its own class
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D47307
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333439
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Florian Hahn [Tue, 29 May 2018 17:40:03 +0000 (17:40 +0000)]
[TableGen] Fix leaking of PhysRegInputs.
Instead of dynamically allocating the vector for PhysRegs, we can
allocate it on the stack and move it into InstructionMemo.
Reviewers: mcrosier, craig.topper, RKSimon, dsanders
Reviewed By: dsanders
Differential Revision: https://reviews.llvm.org/D47461
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333438
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Nicolai Haehnle [Tue, 29 May 2018 17:12:20 +0000 (17:12 +0000)]
TableGen: add some more helpful error messages
Summary: Change-Id: I6f3dacf675a4126134577616e259696bebdade3a
Reviewers: tra, simon_tatham, craig.topper, MartinO, arsenm
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D47429
Change-Id: I614de12a4c154c6d53c090f2f3e53ad2d09942c5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333436
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Florian Hahn [Tue, 29 May 2018 16:55:06 +0000 (16:55 +0000)]
[TableGen] Fix leaking synthesized registers.
By keeping track of unique_ptrs to the synthesized definitions in
CodeGenRegBank we avoid leaking them.
Reviewers: dsanders, kparzysz, stoklund
Reviewed By: dsanders
Differential Revision: https://reviews.llvm.org/D47462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333434
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Cameron McInally [Tue, 29 May 2018 16:49:32 +0000 (16:49 +0000)]
[StrictFP] Make getStrictFPOpcodeAction(...) more accessible
NFCI. This function will be reused in upcoming patches.
Differential Revision: https://reviews.llvm.org/D47380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333433
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Simon Pilgrim [Tue, 29 May 2018 16:36:27 +0000 (16:36 +0000)]
[X86][SSE] Regenerate sdiv combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333431
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Simon Pilgrim [Tue, 29 May 2018 16:35:38 +0000 (16:35 +0000)]
[X86][AVX] Regenerate vzeroall/vzeroupper cleanup tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333430
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Evandro Menezes [Tue, 29 May 2018 15:58:50 +0000 (15:58 +0000)]
[AArch64] Fix PR32384: bump up the number of stores per memset and memcpy
As suggested in https://bugs.llvm.org/show_bug.cgi?id=32384#c1, this change
makes the inlining of `memset()` and `memcpy()` more aggressive when
compiling for speed. The tuning remains the same when optimizing for size.
Patch by: Sebastian Pop <s.pop@samsung.com>
Evandro Menezes <e.menezes@samsung.com>
Differential revision: https://reviews.llvm.org/D45098
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333429
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Simon Atanasyan [Tue, 29 May 2018 15:58:06 +0000 (15:58 +0000)]
[mips] Process numeric register name in the .set assignment directive
Now LLVM assembler cannot process the following code and generates an
error. GNU tools support .set assignment directive with numeric register
name.
```
.set r4, 4
test.s:1:11: error: invalid token in expression
.set r4, $4
^
```
This patch teach assembler to handle such directives correctly.
Unfortunately a numeric register name cannot be represented as an
expression. That's why we have to maintain a separate `StringMap`
in the `MipsAsmParser` to keep mapping between aliases names and
register numbers.
Differential revision: https://reviews.llvm.org/D47464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333428
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Amara Emerson [Tue, 29 May 2018 15:34:22 +0000 (15:34 +0000)]
Revert "[AArch64] added FP16 vcvth intrinsic support"
This reverts commit r333410 due to bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333427
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Alexander Ivchenko [Tue, 29 May 2018 14:49:51 +0000 (14:49 +0000)]
[llvm-readobj] Support GNU_PROPERTY_X86_FEATURE_1_AND notes in .note.gnu.property
This patch allows parsing GNU_PROPERTY_X86_FEATURE_1_AND
notes in .note.gnu.property sections. These notes
indicate that the object file is built to support Intel CET.
patch by mike.dvoretsky
Differential Revision: https://reviews.llvm.org/D47473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333424
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Sander de Smalen [Tue, 29 May 2018 14:40:24 +0000 (14:40 +0000)]
[AArch64][SVE] Asm: Support for predicated LSL/LSR (vectors)
Reviewers: rengolin, huntergr, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333422
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Jonas Devlieghere [Tue, 29 May 2018 14:35:34 +0000 (14:35 +0000)]
[CodeView] Add prefix to CodeView registers.
Adds CVReg to CodeView register names to prevent a duplicate symbol with
CR3 defined in termios.h, as suggested by Zachary on the mailing list.
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123372.html
Differential revision: https://reviews.llvm.org/D47478
rdar://
39863705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333421
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Alexander Ivchenko [Tue, 29 May 2018 14:27:11 +0000 (14:27 +0000)]
[X86] Scalar mask and scalar move optimizations
1. Introduction of mask scalar TableGen patterns.
2. Introduction of new scalar move TableGen patterns
and refactoring of existing ones.
3. Folding of pattern created by introducing scalar
masking in Clang header files.
Patch by tkrupa
Differential Revision: https://reviews.llvm.org/D47012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333419
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Than McIntosh [Tue, 29 May 2018 13:52:24 +0000 (13:52 +0000)]
StackColoring: better handling of statically unreachable code
Summary:
Avoid assert/crash during liveness calculation in situations
where the incoming machine function has statically unreachable BBs.
Second attempt at submitting; this version of the change includes
a revised testcase.
Fixes PR37130.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47372
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333416
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Lei Huang [Tue, 29 May 2018 13:38:56 +0000 (13:38 +0000)]
[PowerPC] Fix the incorrect iterator inside peephole
Instruction selection can insert nodes into the underlying list after the root
node so iterating will thereby miss it. We should NOT assume that, the root node
is the last element in the DAG nodelist.
Patch by: steven.zhang (Qing Shan Zhang)
Differential Revision: https://reviews.llvm.org/D47437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333415
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Sander de Smalen [Tue, 29 May 2018 13:08:43 +0000 (13:08 +0000)]
[AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions.
This patch addresses the following variants:
- bitmask immediate, e.g. 'and z0.d, z0.d, #0x6'.
- unpredicated data vectors, e.g. 'and z0.d, z1.d, z2.d'.
- predicated data vectors, e.g. 'and z0.d, p0/m, z0.d, z1.d'.
And also several aliases, such as:
- ORN, alias of ORR.
- EON, alias of EOR.
- BIC, alias of AND (immediate variant)
- MOV, alias of ORR (if unpredicated and source register operands are the same)
Reviewers: rengolin, huntergr, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333414
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Luke Geeson [Tue, 29 May 2018 11:40:33 +0000 (11:40 +0000)]
[AArch64] added FP16 vcvth intrinsic support
Summary: Change-Id: I0df845749c7689dfc99150ba7c19c7d0dadbd705
Reviewers: javed.absar, SjoerdMeijer
Reviewed By: SjoerdMeijer
Subscribers: llvm-commits, SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333410
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Simon Atanasyan [Tue, 29 May 2018 11:33:54 +0000 (11:33 +0000)]
[mips] Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 / HI16 relocations
Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 and
R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI16 chains of
relocations for %lo(%neg(%gp_rel())) and %hi(%neg(%gp_rel()))
expressions in case of microMIPS.
Differential Revision: http://reviews.llvm.org/D47220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333409
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Sander de Smalen [Tue, 29 May 2018 10:39:49 +0000 (10:39 +0000)]
[AArch64][SVE] Asm: Support for ADD (immediate) instructions.
This patch adds addsub_imm8_opt_lsl_(i8|i16|i32|i64) operands
that are unsigned values in the range 0 to 255. For element widths of
16 bits or higher it may also be a signed multiple of 256 in the
range 0 to 65280.
Note: This also does some refactoring to reuse convenience function
getShiftedVal<shift>(), and now allows AArch64 scalar 'ADD #-4096' to be
accepted to be mapped to SUB #4096.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333408
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Simon Atanasyan [Tue, 29 May 2018 10:27:44 +0000 (10:27 +0000)]
[mips] Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations
Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations for %higher()
and %highest() expressions in case of microMIPS. These relocations do
exactly the same things as R_MIPS_HIGHER / R_MIPS_HIGHEST, but for
consistency it's better to write microMIPS variants.
Differential Revision: http://reviews.llvm.org/D47219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333407
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Luke Geeson [Tue, 29 May 2018 10:12:27 +0000 (10:12 +0000)]
Test Commit Access - Removed Whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333406
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Simon Dardis [Tue, 29 May 2018 09:56:19 +0000 (09:56 +0000)]
[mips] Correct the predicates for a number of instructions.
Previously, their listed predicates were overridden at the scope level.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333405
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Simon Atanasyan [Tue, 29 May 2018 09:51:33 +0000 (09:51 +0000)]
[mips] Cleanup the code to reduce diff with the upcoming patches. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333404
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Simon Atanasyan [Tue, 29 May 2018 09:51:28 +0000 (09:51 +0000)]
[mips] Escape else-after-return. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333403
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Simon Atanasyan [Tue, 29 May 2018 09:51:22 +0000 (09:51 +0000)]
[mips] Stop parsing a .set assignment if the first argument is not an identifier
Before this fix the following code triggers two error messages. The
second one is at least useless:
test.s:1:9: error: expected identifier after .set
.set 123, $a0
^
test-set.s:1:9: error: unexpected token, expected comma
.set 123, $a0
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333402
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Tim Renouf [Tue, 29 May 2018 08:15:37 +0000 (08:15 +0000)]
[AMDGPU] Fixed build warning
Summary:
V2: Use cast instead of extra if.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D47426
Change-Id: I6ac31da0306f79706960284a7ebd7b9c6237a83a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333397
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Serge Pavlov [Tue, 29 May 2018 07:05:41 +0000 (07:05 +0000)]
Reverted commits 333390, 333391 and 333394
Build of shared library LLVMDemangle.so fails due to dependency problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333395
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Serge Pavlov [Tue, 29 May 2018 06:48:57 +0000 (06:48 +0000)]
Added library LLVMSupport to dependencies of LLVMDemangle
After r333390 build of LLVMDemangle.so fails due to unresolved
reference `llvm::report_bad_alloc_error`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333394
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Craig Topper [Tue, 29 May 2018 06:22:45 +0000 (06:22 +0000)]
[X86] Disable a DAG combine to allow packed AVX512DQ instructions to be consistently used for i64->float/double conversions.
Summary: We already get this right if the i64 didn't come from a load.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333393
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