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Matthias Braun [Tue, 1 Aug 2017 22:20:49 +0000 (22:20 +0000)]
ARM: Do not use llc -march in tests.
`llc -march` is problematic because it only switches the target
architecture, but leaves the operating system unchanged. This
occasionally leads to indeterministic tests because the OS from
LLVM_DEFAULT_TARGET_TRIPLE is used.
However we can simply always use `llc -mtriple` instead. This changes
all the tests to do this to avoid people using -march when they copy and
paste parts of tests.
See also the discussion in https://reviews.llvm.org/D35287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309755
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Matthias Braun [Tue, 1 Aug 2017 22:20:41 +0000 (22:20 +0000)]
PowerPC: Do not use llc -march in tests.
`llc -march` is problematic because it only switches the target
architecture, but leaves the operating system unchanged. This
occasionally leads to indeterministic tests because the OS from
LLVM_DEFAULT_TARGET_TRIPLE is used.
However we can simply always use `llc -mtriple` instead. This changes
all the tests to do this to avoid people using -march when they copy and
paste parts of tests.
This patch:
- Removes -march if the .ll file already has a matching `target triple`
directive or -mtriple argument.
- In all other cases changes -march=ppc32/-march=ppc64 to
-mtriple=ppc32--/-mtriple=ppc64--
See also the discussion in https://reviews.llvm.org/D35287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309754
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Adrian Prantl [Tue, 1 Aug 2017 21:45:24 +0000 (21:45 +0000)]
Remove PrologEpilogInserter's usage of DBG_VALUE's offset field
In the last half-dozen commits to LLVM I removed code that became dead
after removing the offset parameter from llvm.dbg.value gradually
proceeding from IR towards the backend. Before I can move on to
DwarfDebug and friends there is one last side-called offset I need to
remove: This patch modifies PrologEpilogInserter's use of the
DBG_VALUE's offset argument to use a DIExpression instead. Because the
PrologEpilogInserter runs at the Machine level I had to play a little
trick with a named llvm.dbg.mir node to get the DIExpressions to print
in MIR dumps (which print the llvm::Module followed by the
MachineFunction dump).
I also had to add rudimentary DwarfExpression support to CodeView and
as a side-effect also fixed a bug (CodeViewDebug::collectVariableInfo
was supposed to give up on variables with complex DIExpressions, but
would fail to do so for fragments, which are also modeled as
DIExpressions).
With this last holdover removed we will have only one canonical way of
representing offsets to debug locations which will simplify the code
in DwarfDebug (and future versions of CodeViewDebug once it starts
handling more complex expressions) and make it easier to reason about.
This patch is NFC-ish: All test case changes are for assembler
comments and the binary output does not change.
rdar://problem/
33580047
Differential Revision: https://reviews.llvm.org/D36125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309751
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Haicheng Wu [Tue, 1 Aug 2017 21:26:45 +0000 (21:26 +0000)]
[AArch64] Fix a typo in isExtFreeImpl()
next => not
Differential Revision: https://reviews.llvm.org/D36104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309748
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Vedant Kumar [Tue, 1 Aug 2017 21:23:26 +0000 (21:23 +0000)]
[llvm-cov] Allow specifying distinct architectures for each loaded binary
The coverage tool needs to know which slice to look at when it's handed
a universal binary. Some projects need to look at aggregate coverage
reports for a variety of slices in different binaries: this patch adds
support for these kinds of projects to llvm-cov.
rdar://problem/
33579007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309747
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Eugene Zelenko [Tue, 1 Aug 2017 21:20:10 +0000 (21:20 +0000)]
[Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309746
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Martin Storsjo [Tue, 1 Aug 2017 21:13:54 +0000 (21:13 +0000)]
[AArch64] Rewrite stack frame handling for win64 vararg functions
The previous attempt, which made do with a single offset in
computeCalleeSaveRegisterPairs, wasn't quite enough. The previous
attempt only worked as long as CombineSPBump == true (since the
offset would be adjusted later in fixupCalleeSaveRestoreStackOffset).
Instead include the size for the fixed stack area used for win64
varargs in calculations in emitPrologue/emitEpilogue. The stack
consists of mainly three parts;
- AFI->getLocalStackSize()
- AFI->getCalleeSavedStackSize()
- FixedObject
Most of the places in the code which previously used the CSStackSize
now use PrologueSaveSize instead, which is the sum of the latter
two, while some cases which need exactly the middle one use
AFI->getCalleeSavedStackSize() explicitly instead of a local variable.
In addition to moving the offsetting into emitPrologue/emitEpilogue
(which fixes functions with CombineSPBump == false), also set the
frame pointer to point to the right location, where the frame pointer
and link register actually are stored. In addition to the prologue/epilogue,
this also requires changes to resolveFrameIndexReference.
Add tests for a function that keeps a frame pointer and another one
that uses a VLA.
Differential Revision: https://reviews.llvm.org/D35919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309744
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Matt Arsenault [Tue, 1 Aug 2017 20:49:41 +0000 (20:49 +0000)]
AMDGPU: Fix handling of div_scale with undef inputs
The src0 register must match src1 or src2, but if these
were undefined they could end up using different implicit_defed
virtual registers. Force these to use one undef vreg or pick the
defined other register.
Also fixes producing invalid nodes without the right number of
inputs when src2 is undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309743
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Nirav Dave [Tue, 1 Aug 2017 20:30:52 +0000 (20:30 +0000)]
[DAG] Factor out common expressions. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309740
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Chad Rosier [Tue, 1 Aug 2017 20:18:54 +0000 (20:18 +0000)]
[Value Tracking] Default argument to true and rename accordingly. NFC.
IMHO this is a bit more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309739
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Matt Arsenault [Tue, 1 Aug 2017 19:54:58 +0000 (19:54 +0000)]
AMDGPU: Add test for r308774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309733
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Matt Arsenault [Tue, 1 Aug 2017 19:54:18 +0000 (19:54 +0000)]
AMDGPU: Initial implementation of calls
Includes a hack to fix the type selected for
the GlobalAddress of the function, which will be
fixed by changing the default datalayout to use
generic pointers for 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309732
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Reid Kleckner [Tue, 1 Aug 2017 19:45:09 +0000 (19:45 +0000)]
[DebugInfo] Don't turn dbg.declare into DBG_VALUE for static allocas
Summary:
We already have information about static alloca stack locations in our
side table. Emitting instructions for them is inefficient, and it only
happens when the address of the alloca has been materialized within the
current block, which isn't often.
Reviewers: aprantl, probinson, dblaikie
Subscribers: jfb, dschuff, sbc100, jgravelle-google, hiraditya, llvm-commits, aheejin
Differential Revision: https://reviews.llvm.org/D36117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309729
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Chad Rosier [Tue, 1 Aug 2017 19:22:36 +0000 (19:22 +0000)]
[Value Tracking] Refactor and/or logic into helper. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309726
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Davide Italiano [Tue, 1 Aug 2017 19:07:20 +0000 (19:07 +0000)]
[AMDGPU] Put a function used only inside assert() under NDEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309723
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Jacques Pienaar [Tue, 1 Aug 2017 18:40:08 +0000 (18:40 +0000)]
[lanai] Add getIntImmCost in LanaiTargetTransformInfo.
Add simple int immediate cost function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309721
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Nirav Dave [Tue, 1 Aug 2017 18:19:56 +0000 (18:19 +0000)]
Pull out VectorNumElements value. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309719
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Simon Pilgrim [Tue, 1 Aug 2017 18:16:44 +0000 (18:16 +0000)]
[X86][SSE3] Add scheduler tests for MONITOR/MWAIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309718
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Nirav Dave [Tue, 1 Aug 2017 18:09:25 +0000 (18:09 +0000)]
Revert "[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector."
This reverts commit r309680 which appears to be raising an assertion
in the test-suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309717
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Kostya Serebryany [Tue, 1 Aug 2017 18:02:19 +0000 (18:02 +0000)]
[libFuzzer] temporarty remove pc-tables and disable test/fuzzer-printcovpcs.test until this can be fixed on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309716
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Simon Pilgrim [Tue, 1 Aug 2017 17:51:20 +0000 (17:51 +0000)]
[X86][SSE] Added missing vector logic intrinsic schedules
Improves atom scheduler test coverage (to make it easier to upgrade them for PR32431).
Merged SSE_VEC_BIT_ITINS_P + SSE_BIT_ITINS_P as we were interchanging between them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309715
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Sanjay Patel [Tue, 1 Aug 2017 17:24:54 +0000 (17:24 +0000)]
[CGP] use narrower types in memcmp expansion when possible
This only affects very small memcmp on x86 for now, but it
will become more important if we allow vector-sized load and
compares.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309711
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Nirav Dave [Tue, 1 Aug 2017 17:19:41 +0000 (17:19 +0000)]
[DAG] Convert extload check to equivalent type check. NFC.
Replace check with check that consuming store has the same type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309708
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Craig Topper [Tue, 1 Aug 2017 17:18:14 +0000 (17:18 +0000)]
[X86] Use BEXTR/BEXTRI for 64-bit 'and' with a large mask
Summary: The 64-bit 'and' with immediate instruction only supports a 32-bit immediate. So for larger constants we have to load the constant into a register first. If the immediate happens to be a mask we can use the BEXTRI instruction to perform the masking. We already do something similar using the BZHI instruction from the BMI2 instruction set.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309706
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Simon Pilgrim [Tue, 1 Aug 2017 16:47:48 +0000 (16:47 +0000)]
[X86][SSE] Added missing PACKSS/PACKUS intrinsic schedules
Improves atom scheduler test coverage (to make it easier to upgrade them for PR32431).
Checked on Agner that these actually match the UNPACK schedules, but better to include a separate class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309701
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Craig Topper [Tue, 1 Aug 2017 16:45:11 +0000 (16:45 +0000)]
[X86] Split bmi.ll into a bmi test and a bmi2 test.
This moves all the bmi2 specific intrinsics to a separate test file and adds a bmi1 only command line to the existing bmi test.
This will allow us to see the missed opportunity to use bextr to handle 64-bit 'and' with a large mask. This will be improved in an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309700
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Simon Pilgrim [Tue, 1 Aug 2017 16:18:25 +0000 (16:18 +0000)]
[X86][SSSE3] Added missing PHADDS/PHSUBS/PSIGN intrinsic schedules
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309699
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Nirav Dave [Tue, 1 Aug 2017 16:00:47 +0000 (16:00 +0000)]
[DAG] Move extload check in store merge. NFC.
Move candidate check from later check to initial candidate check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309698
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Manoj Gupta [Tue, 1 Aug 2017 15:39:12 +0000 (15:39 +0000)]
[X86] Fix a crash in FEntryInserter Pass.
Summary:
FEntryInserter pass unconditionally derefs the first Instruction
in the first Basic Block. The pass crashes when the first
BasicBlock is empty. Fix the crash by not dereferencing the basic
Block iterator. This fixes an issue observed when building Linux kernel
4.4 with clang.
Fixes PR33971.
Reviewers: hfinkel, niravd, dblaikie
Reviewed By: niravd
Subscribers: davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D35979
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309694
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Craig Topper [Tue, 1 Aug 2017 15:31:24 +0000 (15:31 +0000)]
[AVX-512] Don't use unmasked VMOVDQU8/16 for 8-bit or 16-bit element stores even when BWI instructions are supported. Always use VMOVDQA32/VMOVDQU32.
We were already using the 32 bit element opcode if BWI isn't enabled, but there's no reason to change opcode if we have BWI. We will still use the 8/16 opcodes for masked stores though.
This allows us to use the aligned opcode when we can which makes our test output more consistent between different modes. It also reduces the number of isel patterns we need.
This is a slight inconsistency with loads which default to 64 bit element opcodes. I'll probably rectify that in a future patch.
Differential Revision: https://reviews.llvm.org/D35978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309693
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Simon Pilgrim [Tue, 1 Aug 2017 15:31:24 +0000 (15:31 +0000)]
[X86][SSSE3] Fix typos in pabsw/pmulhrsw tests for load folding scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309692
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Simon Pilgrim [Tue, 1 Aug 2017 15:14:35 +0000 (15:14 +0000)]
[X86] Added missing cpu to fix generic scheduling model tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309691
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Craig Topper [Tue, 1 Aug 2017 15:10:25 +0000 (15:10 +0000)]
[InstCombine] Remove explicit check for impossible condition. Replace with assert
Summary:
As far as I can tell the earlier call getLimitedValue will guaranteed ShiftAmt is saturated to BitWidth-1 preventing it from ever being equal or greater than BitWidth.
At one point in the past the getLimitedValue call was only passed BitWidth not BitWidth - 1. This would have allowed the equality case to get here. And in fact this check was initially added as just BitWidth == ShiftAmt, but was changed shortly after to include > which should have never been possible.
Reviewers: spatel, majnemer, davide
Reviewed By: davide
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309690
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Daniel Sanders [Tue, 1 Aug 2017 14:55:34 +0000 (14:55 +0000)]
[globalisel][tablegen] Removed unnecessary typedef pointed out in post-commit review for r308599. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309687
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David Blaikie [Tue, 1 Aug 2017 14:50:50 +0000 (14:50 +0000)]
DebugInfo: Update flag description that'd been copypasted from another
Post-commit review feedback from Paul Robinson on r309630. Thanks Paul!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309685
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Tobias Grosser [Tue, 1 Aug 2017 14:40:55 +0000 (14:40 +0000)]
[PostDom] document the current handling of infinite loops and unreachables
Summary:
As we are in the process of changing the behavior of how the post-dominator tree
is computed, make sure we have some more test coverage in this area.
Current inconsistencies:
- Newly unreachable nodes are not added as new roots, in case the PDT is updated
but not rebuilt.
- Newly unreachable loops are not added to the CFG at all (neither when
building from scratch nor when updating the CFG). This is inconsistent with
the fact that unreachables are added to the PDT, but unreachable loops not.
On the other side, PDT relationships are not loosened at the moment in
cases where new unreachable loops are built.
This commit is providing additional test coverage for
https://reviews.llvm.org/D35851
Reviewers: dberlin, kuhar
Reviewed By: kuhar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309684
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Benjamin Kramer [Tue, 1 Aug 2017 14:38:08 +0000 (14:38 +0000)]
[DebugInfo] Use shrink_to_fit to simplify code. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309683
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Nirav Dave [Tue, 1 Aug 2017 13:45:35 +0000 (13:45 +0000)]
[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector.
Summary:
Allow SCALAR_TO_VECTOR of EXTRACT_VECTOR_ELT to reduce to
EXTRACT_SUBVECTOR of vector shuffle when output is smaller. Marginally
improves vector shuffle computations.
Reviewers: efriedma, RKSimon, spatel
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D35566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309680
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Strahinja Petrovic [Tue, 1 Aug 2017 13:42:45 +0000 (13:42 +0000)]
[Mips] Fix for BBIT octeon instruction
This patch enables control flow optimization for
variations of BBIT instruction. In this case
optimization removes unnecessary branch after
BBIT instruction.
Differential Revision: https://reviews.llvm.org/D35359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309679
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Krzysztof Parzyszek [Tue, 1 Aug 2017 13:12:53 +0000 (13:12 +0000)]
[Hexagon] Convert HVX vector constants of i1 to i8
Certain operations require vector of i1 values. However, for Hexagon
architecture compatibility, they need to be represented as vector of i8.
Patch by Suyog Sarda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309677
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Simon Pilgrim [Tue, 1 Aug 2017 13:12:15 +0000 (13:12 +0000)]
[X86] Regenerate big structure return test and check on x86_64 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309676
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Tom Stellard [Tue, 1 Aug 2017 12:38:33 +0000 (12:38 +0000)]
AMDGPU/GlobalISel: Add support for amdgpu_vs calling convention
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D35916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309675
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Tobias Grosser [Tue, 1 Aug 2017 11:01:28 +0000 (11:01 +0000)]
[PostDom] Fix typo in comment [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309673
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Max Kazantsev [Tue, 1 Aug 2017 10:13:29 +0000 (10:13 +0000)]
[NFC] Remove obsolete profiling data from eq_ne test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309670
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Andrew V. Tischenko [Tue, 1 Aug 2017 09:15:43 +0000 (09:15 +0000)]
Support itineraries in TargetSubtargetInfo::getSchedInfoStr - Now if the given instr does not have sched model then we try to calculate the latecy/throughput with help of itineraries.
Differential Revision https://reviews.llvm.org/D35997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309666
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Max Kazantsev [Tue, 1 Aug 2017 06:49:29 +0000 (06:49 +0000)]
[IRCE][NFC] Add another assert that AddRecExpr's step is not zero
One more assertion of this kind. It is a preparation step for generalizing
to the case of stride not equal to +1/-1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309663
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Chandler Carruth [Tue, 1 Aug 2017 06:40:11 +0000 (06:40 +0000)]
[PM] Add a comment clarifying what a particular predicate is doing.
This came up as a point of confusion while working on a fundamental
problem with the combination of CGSCC iteration and the inliner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309662
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Max Kazantsev [Tue, 1 Aug 2017 06:27:51 +0000 (06:27 +0000)]
[IRCE][NFC] Add assert that AddRecExpr's step is not zero
We should never return zero steps, ensure this fact by adding
a sanity check when we are analyzing the induction variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309661
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Petr Hosek [Tue, 1 Aug 2017 05:31:50 +0000 (05:31 +0000)]
Revert "[llvm][llvm-objcopy] Added support for outputting to binary in llvm-objcopy"
The change seems to be failing on bots which are using gcc and bfd.ld
as a host compiler and linker.
This reverts commit r309658.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309660
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Daniel Jasper [Tue, 1 Aug 2017 05:30:49 +0000 (05:30 +0000)]
Revert r309415: "[LVI] Constant-propagate a zero extension of the switch condition value through case edges"
This causes assertion failures in (a somewhat old version of) SpiderMonkey.
I have already forwarded reproduction instructions to the patch author.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309659
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Petr Hosek [Tue, 1 Aug 2017 05:18:30 +0000 (05:18 +0000)]
[llvm][llvm-objcopy] Added support for outputting to binary in llvm-objcopy
This change adds the "-O binary" flag which directs llvm-objcopy to
output the object file to the same format as GNU objcopy does when given
the flag "-O binary". This was done by splitting the Object class into
two subclasses ObjectELF and ObjectBianry which each output a different
format but relay on the same code to read in the Object in Object.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D34480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309658
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Davide Italiano [Tue, 1 Aug 2017 05:14:45 +0000 (05:14 +0000)]
[MetaRenamer] Leave `@main` alone.
To the best of my knowledge -metarenamer is used in two cases:
1) obfuscate names, when e.g. they contain informations that
can't be shared.
2) Improve clarity of the textual IR for testcases.
One of the usecases if getting the output of `opt` and passing it
to the lli interpreter to run the test. If metarenamer renames
@main, lli can't find an entry point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309657
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Craig Topper [Tue, 1 Aug 2017 04:18:34 +0000 (04:18 +0000)]
[MathExtras] Remove unnecessary cast of a constant 1 in a subtract.
Pretty sure this will automatically promoted to match the type of the other operand of the subtract. There's plenty of other similar code around here without this cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309653
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Hiroshi Inoue [Tue, 1 Aug 2017 03:32:15 +0000 (03:32 +0000)]
[StackColoring] Update AliasAnalysis information in stack coloring pass
Stack coloring pass need to maintain AliasAnalysis information when merging stack slots of different types.
Actually, there is a FIXME comment in StackColoring.cpp
// FIXME: In order to enable the use of TBAA when using AA in CodeGen,
// we'll also need to update the TBAA nodes in MMOs with values
// derived from the merged allocas.
But, TBAA has been already enabled in CodeGen without fixing this pass.
The incorrect TBAA metadata results in recent failures in bootstrap test on ppc64le (PR33928) by allowing unsafe instruction scheduling.
Although we observed the problem on ppc64le, this is a platform neutral issue.
This patch makes the stack coloring pass maintains AliasAnalysis information when merging multiple stack slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309651
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Kostya Serebryany [Tue, 1 Aug 2017 01:16:26 +0000 (01:16 +0000)]
[libFuzzer] implement more correct way of computing feature index for Inline8bitCounters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309647
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Kostya Serebryany [Tue, 1 Aug 2017 00:48:44 +0000 (00:48 +0000)]
[libFuzzer] enable -fsanitize-coverage=pc-table for all tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309646
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Alina Sbirlea [Tue, 1 Aug 2017 00:47:17 +0000 (00:47 +0000)]
Default MemoryLocation passed to getModRefInfo should be None (D35441)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309645
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Kostya Serebryany [Tue, 1 Aug 2017 00:44:05 +0000 (00:44 +0000)]
[sanitizer-coverage] relax an assertion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309644
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Petr Hosek [Tue, 1 Aug 2017 00:33:58 +0000 (00:33 +0000)]
Reland "[LLVM][llvm-objcopy] Added basic plumbing to get things started"
As discussed on llvm-dev I've implemented the first basic steps towards
llvm-objcopy/llvm-objtool (name pending).
This change adds the ability to copy (without modification) 64-bit
little endian ELF executables that have SHT_PROGBITS, SHT_NOBITS,
SHT_NULL and SHT_STRTAB sections.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D33964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309643
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Eli Friedman [Tue, 1 Aug 2017 00:28:40 +0000 (00:28 +0000)]
[ScheduleDAG] Don't schedule node with physical register interference
https://reviews.llvm.org/D31536 didn't really solve the problem it was
trying to solve; it got rid of the assertion failure, but we were still
scheduling the DAG incorrectly (mixing together instructions from
different calls), leading to a MachineVerifier failure.
In order to schedule the DAG correctly, we have to make sure we don't
schedule a node which should be blocked by an interference. Fix
ScheduleDAGRRList::PickNodeToScheduleBottomUp so it doesn't pick a node
like that.
The added call to FindAvailableNode() is the key change here; this makes
sure we don't try to schedule a call while we're in the middle of
scheduling a different call. I'm not sure this is the right approach; in
particular, I'm not sure how to prove we don't end up with an infinite
loop of repeatedly backtracking.
This also reverts the code change from D31536. It doesn't do anything
useful: we should never schedule an ADJCALLSTACKDOWN unless we've
already scheduled the corresponding ADJCALLSTACKUP.
Differential Revision: https://reviews.llvm.org/D33818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309642
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Alina Sbirlea [Tue, 1 Aug 2017 00:28:29 +0000 (00:28 +0000)]
Allow None as a MemoryLocation to getModRefInfo
Summary:
Adding part of the changes in D30369 (needed to make progress):
Current patch updates AliasAnalysis and MemoryLocation, but does _not_ clean up MemorySSA.
Original summary from D30369, by dberlin:
Currently, we have instructions which affect memory but have no memory
location. If you call, for example, MemoryLocation::get on a fence,
it asserts. This means things specifically have to avoid that. It
also means we end up with a copy of each API, one taking a memory
location, one not.
This starts to fix that.
We add MemoryLocation::getOrNone as a new call, and reimplement the
old asserting version in terms of it.
We make MemoryLocation optional in the (Instruction, MemoryLocation)
version of getModRefInfo, and kill the old one argument version in
favor of passing None (it had one caller). Now both can handle fences
because you can just use MemoryLocation::getOrNone on an instruction
and it will return a correct answer.
We use all this to clean up part of MemorySSA that had to handle this difference.
Note that literally every actual getModRefInfo interface we have could be made private and replaced with:
getModRefInfo(Instruction, Optional<MemoryLocation>)
and
getModRefInfo(Instruction, Optional<MemoryLocation>, Instruction, Optional<MemoryLocation>)
and delegating to the right ones, if we wanted to.
I have not attempted to do this yet.
Reviewers: dberlin, davide, dblaikie
Subscribers: sanjoy, hfinkel, chandlerc, llvm-commits
Differential Revision: https://reviews.llvm.org/D35441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309641
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Craig Topper [Mon, 31 Jul 2017 22:07:29 +0000 (22:07 +0000)]
[AVX-512] Add unmasked subvector inserts and extract to the execution domain tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309632
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David Blaikie [Mon, 31 Jul 2017 21:48:42 +0000 (21:48 +0000)]
DebugInfo: Put range base specifier entry functionality behind a flag
Chromium's gold build seems to have trouble with this (gold produces
errors) - not sure if it's gold that's not coping with the valid
representation, or a bug in the implementation in LLVM, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309630
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Craig Topper [Mon, 31 Jul 2017 21:20:06 +0000 (21:20 +0000)]
[AVX512] Add a common prefix to avx512-insert-extract.ll so we can reduce the number of check lines on some test cases.
This was pointed out during the review for
D313804.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309629
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Reid Kleckner [Mon, 31 Jul 2017 21:03:08 +0000 (21:03 +0000)]
[codeview] Ignore DBG_VALUEs when choosing a BB start source loc
When the first instruction of a basic block has no location (consider a
LEA materializing the address of an alloca for a call), we want to start
the line table for the block with the first valid source location in the
block. We need to ignore DBG_VALUE instructions during this scan to get
decent line tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309628
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Sanjay Patel [Mon, 31 Jul 2017 21:01:53 +0000 (21:01 +0000)]
[InstCombine] allow mask hoisting transform for vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309627
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Craig Topper [Mon, 31 Jul 2017 20:58:06 +0000 (20:58 +0000)]
[AVX-512] Use AVX512 as test check prefix instead of AVX3. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309625
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Adrian Prantl [Mon, 31 Jul 2017 20:48:52 +0000 (20:48 +0000)]
Debug Info: Also check the DWARF output in assembler-only test cases
This will prevent me from introducing a regression in my next commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309623
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Peter Collingbourne [Mon, 31 Jul 2017 20:43:07 +0000 (20:43 +0000)]
Update phi nodes in LowerTypeTests control flow simplification
D33925 added a control flow simplification for -O2 --lto-O0 builds that
manually splits blocks and reassigns conditional branches but does not
correctly update phi nodes. If the else case being branched to had
incoming phi nodes the control-flow simplification would leave phi nodes
in that BB with an unhandled predecessor.
Patch by Vlad Tsyrklevich!
Differential Revision: https://reviews.llvm.org/D36012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309621
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Kostya Serebryany [Mon, 31 Jul 2017 20:20:59 +0000 (20:20 +0000)]
[libFuzzer] implement __sanitizer_cov_pcs_init and add pc-table to build flags for one test (for now)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309615
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Konstantin Belochapka [Mon, 31 Jul 2017 20:11:49 +0000 (20:11 +0000)]
[X86][MMX] Added custom lowering action for MMX SELECT (PR30418)
Fix for pr30418 - error in backend: Cannot select: t17: x86mmx = select_cc t2, Constant:i64<0>, t7, t8, seteq:ch
Differential Revision: https://reviews.llvm.org/D34661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309614
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Sanjay Patel [Mon, 31 Jul 2017 20:02:04 +0000 (20:02 +0000)]
[InstCombine] add tests for mask hoisting; NFC
The scalar transforms exist with no test coverage. The vector equivalents are missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309612
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Kostya Serebryany [Mon, 31 Jul 2017 20:00:22 +0000 (20:00 +0000)]
[sanitizer-coverage] don't instrument available_externally functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309611
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Kostya Serebryany [Mon, 31 Jul 2017 19:49:45 +0000 (19:49 +0000)]
[sanitizer-coverage] ensure minimal alignment for coverage counters and guards
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309610
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Zachary Turner [Mon, 31 Jul 2017 19:36:08 +0000 (19:36 +0000)]
[lld/pdb] Add an empty globals stream.
We don't write any actual symbols to this stream yet, but for
now we just create the stream and hook it up to the appropriate
places and give it a valid header.
Differential Revision: https://reviews.llvm.org/D35290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309608
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Davide Italiano [Mon, 31 Jul 2017 19:14:19 +0000 (19:14 +0000)]
[SLPVectorizer] Unbreak the build with -Werror.
GCC was complaining about `&&` within `||` without explicit
parentheses. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309606
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Craig Topper [Mon, 31 Jul 2017 18:52:15 +0000 (18:52 +0000)]
[X86][InstCombine] Add some simplifications for BZHI intrinsics
This intrinsic clears the upper bits starting at a specified index. If the index is a constant we can do some simplifications.
This could be in InstSimplify, but we don't handle any target specific intrinsics there today.
Differential Revision: https://reviews.llvm.org/D36069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309604
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Craig Topper [Mon, 31 Jul 2017 18:52:13 +0000 (18:52 +0000)]
[X86][InstCombine] Add basic simplification support for BEXTR/BEXTRI intrinsics.
This patch adds simplification support for the BEXTR/BEXTRI intrinsics to match gcc. This only supports cases that fold to 0 or can be fully constant folded. Theoretically we could support converting to AND if the shift part is unused or to only a shift if the mask doesn't modify any bits after an equivalent shl. gcc doesn't do these transformations either.
I put this in InstCombine, but it could be done in InstSimplify. It would be the first target specific intrinsic in InstSimplify.
Differential Revision: https://reviews.llvm.org/D36063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309603
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Reid Kleckner [Mon, 31 Jul 2017 18:45:44 +0000 (18:45 +0000)]
[lit] Avoid copying llvm/utils/lit/tests/Inputs with lit site configs
Summary:
This is an alternative solution to running the lit test suite on bots
without polluting the source directory. Each input test suite gets an
auto-generated site config in the build directory that points back to
the test input source directory.
This adds some cmake comlexity, but now we don't need to remove and
re-copy the test input directory before every test.
Reviewers: delcypher, modocache
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D36026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309602
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Quentin Colombet [Mon, 31 Jul 2017 18:31:04 +0000 (18:31 +0000)]
[llc][NFC] Update message in assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309600
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Quentin Colombet [Mon, 31 Jul 2017 18:24:07 +0000 (18:24 +0000)]
[TargetPassConfig] Feature generic options to setup start/stop-after/before
This patch refactors the code used in llc such that all the users of the
addPassesToEmitFile API have access to a homogeneous way of handling
start/stop-after/before options right out of the box.
In particular, just invoking addPassesToEmitFile will set the proper
pipeline without additional effort (modulo parsing a .mir file if the
start-before/after options are used.
NFC.
Differential Revision: https://reviews.llvm.org/D30913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309599
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Sanjay Patel [Mon, 31 Jul 2017 18:08:24 +0000 (18:08 +0000)]
[CGP] use subtract or subtract-of-cmps for result of memcmp expansion
As noted in the code comment, transforming this in the other direction might require
a separate transform here in CGP given the block-at-a-time DAG constraint.
Besides that theoretical motivation, there are 2 practical motivations for the
subtract-of-cmps form:
1. The codegen for both x86 and PPC is better for this IR (though PPC could be better still).
There is discussion about canonicalizing IR to the select form
( http://lists.llvm.org/pipermail/llvm-dev/2017-July/114885.html ),
so we probably need to add DAG transforms for those patterns anyway, but this improves the
memcmp output without waiting for that step.
2. If we allow vector-sized chunks for the load and compare, x86 is better prepared to convert
that to optimal code when using subtract-of-cmps, so another prerequisite patch is avoided
if we choose to enable that.
Differential Revision: https://reviews.llvm.org/D34904
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309597
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Spyridoula Gravani [Mon, 31 Jul 2017 18:01:16 +0000 (18:01 +0000)]
[DWARF] Added verification check for tags in accelerator tables. This patch verifies that the atom tag is actually the same with the tag of the DIE that we retrieve from the table.
Differential Revision: https://reviews.llvm.org/D35963
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309596
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David Majnemer [Mon, 31 Jul 2017 17:47:07 +0000 (17:47 +0000)]
[IPSCCP] Guard a user of getInitializer with hasDefinitiveInitializer
We are not allowed to reason about an initializer value without first
consulting hasDefinitiveInitializer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309594
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Craig Topper [Mon, 31 Jul 2017 17:35:44 +0000 (17:35 +0000)]
[AVX-512] Remove patterns that select vmovdqu8/16 for unmasked loads. Prefer vmovdqa64/vmovdqu64 instead.
These were taking priority over the aligned load instructions since there is no vmovda8/16. I don't think there is really a difference between aligned and unaligned on newer cpus so I don't think it matters which instructions we use.
But with this change we reduce the size of the isel table a little and we allow the aligned information to pass through to the evex->vec pass and produce the same output has avx/avx2 in some cases.
I also generally dislike patterns rooted in a bitcast which these were.
Differential Revision: https://reviews.llvm.org/D35977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309589
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Simon Pilgrim [Mon, 31 Jul 2017 17:09:27 +0000 (17:09 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309584
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Simon Pilgrim [Mon, 31 Jul 2017 17:06:55 +0000 (17:06 +0000)]
Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309583
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Aditya Nandakumar [Mon, 31 Jul 2017 17:00:16 +0000 (17:00 +0000)]
[GISel]: Support Widening G_ICMP's destination operand.
Updated AArch64 to widen destination to s32.
https://reviews.llvm.org/D35737
Reviewed by Tim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309579
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Amaury Sechet [Mon, 31 Jul 2017 16:56:25 +0000 (16:56 +0000)]
Do not recombine FMA when that is not needed.
Summary: As per title. This creates useless recombines.
Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D33848
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309578
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Florian Hahn [Mon, 31 Jul 2017 16:44:28 +0000 (16:44 +0000)]
Exclude more unused functions from release build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309576
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Florian Hahn [Mon, 31 Jul 2017 16:29:00 +0000 (16:29 +0000)]
Extend ifndef to printDebugLoc.
GCC7 did not warn about that, but Clang does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309573
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Florian Hahn [Mon, 31 Jul 2017 16:11:43 +0000 (16:11 +0000)]
Extend ifdefs to more unused helper functions.
This fixes a buildbot failure with -Werror introduced by r309553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309572
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Benjamin Kramer [Mon, 31 Jul 2017 15:32:39 +0000 (15:32 +0000)]
[DebugInfo] Don't overwrite DWARFUnit fields if the CU DIE doesn't have them.
DIEs are lazily deserialized so it's possible that the DWO CU is created
before the DIE is parsed. DWO shares .debug_addr and .debug_ranges with the
object file so overwriting the offset with 0 will make the CU unusable.
No test case because I couldn't get clang to emit a non-zero range base.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309570
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Don Hinton [Mon, 31 Jul 2017 15:18:57 +0000 (15:18 +0000)]
[docker] Fix unmatched quote problem in here-document on older versions of bash
Summary:
When outputing usage, emit here-document directly instead of
saving in a variable first -- avoids problem with bash 3.2.57 where an
unmatched ' in the here-document results in the following error:
./build_docker_image.sh: line 135: unexpected EOF while looking for matching `''
bash --version
GNU bash, version 3.2.57(1)-release (x86_64-apple-darwin16)
Differential Revision: https://reviews.llvm.org/D36064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309568
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Alexey Bataev [Mon, 31 Jul 2017 14:36:05 +0000 (14:36 +0000)]
[SLP] Initial rework for min/max horizontal reduction vectorization, NFC.
Summary: All getReductionCost() functions are renamed to getArithmeticReductionCost() + added basic infrastructure to handle non-binary reduction operations.
Reviewers: spatel, mzolotukhin, Ayal, mkuper, gilr, hfinkel
Subscribers: RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D29402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309566
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Simon Pilgrim [Mon, 31 Jul 2017 14:23:28 +0000 (14:23 +0000)]
[X86] Extending a test cases for LEA factorization.
Submitted on the behalf of Jatin Bhateja
Differential Revision: https://reviews.llvm.org/D36048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309565
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Alexey Bataev [Mon, 31 Jul 2017 14:19:32 +0000 (14:19 +0000)]
[Cost] Rename getReductionCost() to getArithmeticReductionCost(), NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309563
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Simon Dardis [Mon, 31 Jul 2017 14:06:58 +0000 (14:06 +0000)]
[SelectionDAG][mips] Fix PR33883
PR33883 shows that calls to intrinsic functions should not have their vector
arguments or returns subject to ABI changes required by the target.
This resolves PR33883.
Thanks to Alex Crichton for reporting the issue!
Reviewers: zoran.jovanovic, atanasyan
Differential Revision: https://reviews.llvm.org/D35765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309561
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Ayal Zaks [Mon, 31 Jul 2017 13:21:42 +0000 (13:21 +0000)]
[LV] Avoid redundant operations manipulating masks
The Loop Vectorizer generates redundant operations when manipulating masks:
AND with true, OR with false, compare equal to true. Instead of relying on
a subsequent pass to clean them up, this patch avoids generating them.
Use null (no-mask) to represent all-one full masks, instead of a constant
all-one vector, following the convention of masked gathers and scatters.
Preparing for a follow-up VPlan patch in which these mask manipulating
operations are modeled using recipes.
Differential Revision: https://reviews.llvm.org/D35725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309558
91177308-0d34-0410-b5e6-
96231b3b80d8
Martin Storsjo [Mon, 31 Jul 2017 11:18:41 +0000 (11:18 +0000)]
[llvm-dlltool] Write correct weak externals
Previously, the created object files for the import library were broken.
Write the symbol table before the string table. Simplify the code by
using a separate variable Prefix instead of duplicating a few lines.
Also update the coff-weak-exports to actually check that the generated
weak symbols can be found as intended.
Differential Revision: https://reviews.llvm.org/D36065
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309555
91177308-0d34-0410-b5e6-
96231b3b80d8