OSDN Git Service
Kevin Enderby [Fri, 26 Aug 2016 19:34:07 +0000 (19:34 +0000)]
Next set of additional error checks for invalid Mach-O files for bad LC_SYMTAB’s.
This contains the missing checks for LC_SYMTAB load command fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279854
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Manman Ren [Fri, 26 Aug 2016 19:28:17 +0000 (19:28 +0000)]
Swift Calling Convetion: add support for AArch64.
It will just be the same as the regular calling convention.
rdar://
28029509
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279853
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Tim Northover [Fri, 26 Aug 2016 18:52:31 +0000 (18:52 +0000)]
AArch64: avoid assertion on illegal types in performFDivCombine.
In the code to detect fixed-point conversions and make use of AArch64's special
instructions, we weren't prepared for weird types. The fptosi direction got
fixed recently, but not the similar sitofp code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279852
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Sanjay Patel [Fri, 26 Aug 2016 18:28:46 +0000 (18:28 +0000)]
[InstCombine] add helper function for icmp (and (sh X, Y), C2), C1 ; NFC
Like other recent changes near here, the goal is to allow vector types for
all of these folds. Splitting things up makes it easier to incrementally
enhance the code and easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279851
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Chad Rosier [Fri, 26 Aug 2016 18:05:50 +0000 (18:05 +0000)]
[AArch64] Avoid materializing constant values when generating csel instructions.
Differential Revision: https://reviews.llvm.org/D23677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279849
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Davide Italiano [Fri, 26 Aug 2016 18:05:03 +0000 (18:05 +0000)]
[AsmParser] Placate a -Wmisleading-indentantion warning (GCC7).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279848
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Reid Kleckner [Fri, 26 Aug 2016 17:58:37 +0000 (17:58 +0000)]
[MC] Move .cv_loc management logic out of MCContext
MCContext already has many tasks, and separating CodeView out from it is
probably a good idea. The .cv_loc tracking was modelled on the DWARF
tracking which lived directly in MCContext.
Removes the inclusion of MCCodeView.h from MCContext.h, so now there are
only 10 build actions while I hack on CodeView support instead of 265.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279847
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Tim Northover [Fri, 26 Aug 2016 17:46:22 +0000 (17:46 +0000)]
GlobalISel: mark G_FPEXT legal from float to double.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279845
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Tim Northover [Fri, 26 Aug 2016 17:46:19 +0000 (17:46 +0000)]
GlobalISel: mark G_FCMP legal on float & double.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279844
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Tim Northover [Fri, 26 Aug 2016 17:46:17 +0000 (17:46 +0000)]
GlobalISel: simplify G_ICMP legalization regime.
It's unclear how the old
%res(32) = G_ICMP { s32, s32 } intpred(eq), %0, %1
is actually different from an s1 verison
%res(1) = G_ICMP { s1, s32 } intpred(eq), %0, %1
so we'll remove it for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279843
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Tim Northover [Fri, 26 Aug 2016 17:46:13 +0000 (17:46 +0000)]
GlobalISel: legalize sdiv and srem operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279842
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Tim Northover [Fri, 26 Aug 2016 17:46:06 +0000 (17:46 +0000)]
GlobalISel: legalize under-width divisions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279841
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Tim Northover [Fri, 26 Aug 2016 17:46:03 +0000 (17:46 +0000)]
GlobalISel: mark selects legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279840
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Tim Northover [Fri, 26 Aug 2016 17:45:58 +0000 (17:45 +0000)]
GlobalISel: mark float/int conversions legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279839
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Sanjay Patel [Fri, 26 Aug 2016 17:15:22 +0000 (17:15 +0000)]
[InstCombine] clean up foldICmpAndConstConst(); NFC
1. Early exit to reduce indent
2. Fix comments and variable names to match
3. Reformat comments / clang-format code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279837
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Krzysztof Parzyszek [Fri, 26 Aug 2016 16:50:57 +0000 (16:50 +0000)]
Missed a semicolon in r279835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279836
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Krzysztof Parzyszek [Fri, 26 Aug 2016 16:46:14 +0000 (16:46 +0000)]
Add some more detailed debugging information in RegisterCoalescer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279835
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Sanjay Patel [Fri, 26 Aug 2016 16:42:33 +0000 (16:42 +0000)]
[InstCombine] add helper function for folding of icmp (and X, C2), C; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279834
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Bob Haarman [Fri, 26 Aug 2016 16:34:27 +0000 (16:34 +0000)]
limit the number of instructions per block examined by dead store elimination
Summary: Dead store elimination gets very expensive when large numbers of instructions need to be analyzed. This patch limits the number of instructions analyzed per store to the value of the memdep-block-scan-limit parameter (which defaults to 100). This resulted in no observed difference in performance of the generated code, and no change in the statistics for the dead store elimination pass, but improved compilation time on some files by more than an order of magnitude.
Reviewers: dexonsmith, bruno, george.burgess.iv, dberlin, reames, davidxl
Subscribers: davide, chandlerc, dberlin, davidxl, eraman, tejohnson, mbodart, llvm-commits
Differential Revision: https://reviews.llvm.org/D15537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279833
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Saleem Abdulrasool [Fri, 26 Aug 2016 16:18:40 +0000 (16:18 +0000)]
FileCheck: Minor cleanup of the class Pattern
1. Add the "explicit" specifier to the single-argument constructor of Pattern
2. Reorder the fields to remove excessive padding (8 bytes).
Patch by Alexander Shaposhnikov!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279832
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Sanjay Patel [Fri, 26 Aug 2016 16:14:06 +0000 (16:14 +0000)]
[InstCombine] rename variables in foldICmpAndConstant(); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279831
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Bob Haarman [Fri, 26 Aug 2016 16:00:04 +0000 (16:00 +0000)]
test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279830
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Adam Nemet [Fri, 26 Aug 2016 15:58:34 +0000 (15:58 +0000)]
[LoopUnroll] Use OptimizationRemarkEmitter directly not via the analysis pass
We can't mark ORE (a function pass) preserved as required by the loop
passes because that is how we ensure that the required passes like
LazyBFI are all available any time ORE is used. See the new comments in
the patch.
Instead we use it directly just like the inliner does in D22694.
As expected there is some additional overhead after removing the caching
provided by analysis passes. The worst case, I measured was
LNT/CINT2006_ref/401.bzip2 which regresses by 12%. As before, this only
affects -Rpass-with-hotness and not default compilation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279829
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Sanjay Patel [Fri, 26 Aug 2016 15:53:01 +0000 (15:53 +0000)]
[InstCombine] rename variables in foldICmpDivConstant(); NFC
Removing the redundant 'CmpRHSV' local variable exposes a bug in the caller
foldICmpShrConstant() - it was sending in the div constant instead of the
cmp constant. But I have not been able to expose this in a regression test
yet - the affected folds all appear to be handled before we ever reach this
code. I'll keep trying to find a case as I make changes to allow vector folds
in both functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279828
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Davide Italiano [Fri, 26 Aug 2016 15:22:59 +0000 (15:22 +0000)]
[lib/LTO] Add an assertion to catch invalid opt levels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279823
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Chad Rosier [Fri, 26 Aug 2016 14:01:55 +0000 (14:01 +0000)]
[AArch64] Avoid materializing constant 1 by using csinc, rather than csel.
This is similar to what was done in r261675, but for CSINC rather than CSINV.
Differential Revision: https://reviews.llvm.org/D23892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279822
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Pablo Barrio [Fri, 26 Aug 2016 13:00:39 +0000 (13:00 +0000)]
Handle empty functions with debug info in load/store opt pass
Summary:
In fuctions that contained debug info but were empty otherwise,
the ARM load/store optimizer could abort. This was because
function MergeReturnIntoLDM handled the special case where a
Machine Basic BLock is empty by calling MBB.empty(). However, this
returns false in presence of debug info, although the function
should be considered empty in the eyes of the load/store optimizer.
This has been fixed by handling the case where searching through the
block finds only debug instructions.
Reviewers: rengolin, dexonsmith, llvm-commits, jmolloy
Subscribers: t.p.northover, aemerson, rengolin, samparker
Differential Revision: https://reviews.llvm.org/D23847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279820
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Simon Pilgrim [Fri, 26 Aug 2016 09:55:41 +0000 (09:55 +0000)]
[X86][SSE4A] The EXTRQ/INSERTQ bit extraction/insertion ops should be in the integer domain
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279811
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Eugene Leviant [Fri, 26 Aug 2016 08:14:54 +0000 (08:14 +0000)]
Implement getRandomBytes() function
This function allows getting arbitrary sized block of random bytes.
Primary motivation is support for --build-id=uuid in lld.
Differential revision: https://reviews.llvm.org/D23671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279807
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Craig Topper [Fri, 26 Aug 2016 07:08:00 +0000 (07:08 +0000)]
[X86][SSE] Add CMPSS/CMPSD intrinsic scalar load folding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279806
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Matt Arsenault [Fri, 26 Aug 2016 06:31:32 +0000 (06:31 +0000)]
Replace subregister uses when processing tied operands
This was for some reason skipping operands that are subregisters
instead of keeping the same subregister index.
v_movreld_b32 expects src0 to be the subregister of the tied
super register use/def.
e.g.
v_movreld_b32 v0, v9, <imp-def, tied3> v[0:3], <imp-use, tied2> v[0:3]
was being replaced with
v[4:7] = copy v[0:3]
v_movreld_b32 v0, v9, <imp-def, tied3> v[4:7], <imp-use, tied2> v[4:7],
which really writes to v[0:3]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279804
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Eric Christopher [Fri, 26 Aug 2016 02:00:21 +0000 (02:00 +0000)]
Fix singlton -> singleton typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279801
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Akira Hatanaka [Fri, 26 Aug 2016 00:22:12 +0000 (00:22 +0000)]
Fix the static_assert added in r279536.
The assertion doesn't always hold true as sizeof(SDNodeBits) isn't equal
to sizeof(uint16_t) for some targets. For example, sizeof(SDNodeBits)
evaluates to 1, not 2, for ARM's APCS targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279797
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Kostya Serebryany [Fri, 26 Aug 2016 00:18:16 +0000 (00:18 +0000)]
[libFuzzer] simplify a test to make it pass on the bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279796
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Kostya Serebryany [Thu, 25 Aug 2016 23:30:02 +0000 (23:30 +0000)]
[libFuzzer] make sure we have symbols on fuzzer tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279792
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Michael Kuperstein [Thu, 25 Aug 2016 22:48:11 +0000 (22:48 +0000)]
Revert r274613 because it breaks the test suite with AVX512
This reverts most of r274613 (AKA r274626) and its follow-ups (r276347, r277289),
due to miscompiles in the test suite. The FastISel change was left in, because
it apparently fixes an unrelated issue.
(Recommit of r279782 which was broken due to a bad merge.)
This fixes 4 out of the 5 test failures in PR29112.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279788
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Kostya Serebryany [Thu, 25 Aug 2016 22:35:08 +0000 (22:35 +0000)]
[libFizzer] rename -print_new_cov_pcs=1 into -print_pcs=1 and make it more useful: print PCs only after the initial corpus has been read and symbolize them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279787
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Michael Kuperstein [Thu, 25 Aug 2016 22:14:45 +0000 (22:14 +0000)]
Revert r279782 due to debug buildbot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279785
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David Blaikie [Thu, 25 Aug 2016 22:09:13 +0000 (22:09 +0000)]
Fix ArrayRef initializer_list Ctor Test
The InitializerList test had undefined behavior by creating a dangling pointer to the temporary initializer list. This patch removes the undefined behavior in the test by creating the initializer list directly.
Reviewers: mehdi_amini, dblaikie
Differential Revision: https://reviews.llvm.org/D23890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279783
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Michael Kuperstein [Thu, 25 Aug 2016 21:55:41 +0000 (21:55 +0000)]
Revert r274613 because it breaks the test suite with AVX512
This reverts most of r274613 and its follow-ups (r276347, r277289), due to
miscompiles in the test suite. The FastISel change was left in, because it
apparently fixes an unrelated issue.
This fixes 4 out of the 5 test failures in PR29112.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279782
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Tim Shen [Thu, 25 Aug 2016 21:03:46 +0000 (21:03 +0000)]
[MemCpy] Add comments for r279769
Differential Revision: https://reviews.llvm.org/D23846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279778
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Chris Bieneman [Thu, 25 Aug 2016 20:53:00 +0000 (20:53 +0000)]
cmake: Install CheckAtomic.cmake (needed by lldb)
Summary:
Install CheckAtomic.cmake along with other LLVM modules, therefore making it possible for other projects to use it. This file is needed for LLDB to be built standalone, and installing it was suggested in https://reviews.llvm.org/D23881.
Patch by: Michał Górny
Reviewers: krytarowski, zturner, eugenis, jyknight, labath, beanz
Subscribers: beanz, llvm-commits
Differential Revision: https://reviews.llvm.org/D23887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279777
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Chris Bieneman [Thu, 25 Aug 2016 20:49:51 +0000 (20:49 +0000)]
[CMake] Add support for exposing runtime targets
This patch adds support to the runtimes build for exposing sub-project targets through the high-level configuration. This will enable exposing the build, check and install targets for sub-project components (i.e. asan, check-asan, install-asan...).
This patch requires minor changes to the runtime projects to take advantage of it, and I'll phase those changes into Compiler-RT shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279776
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Tim Northover [Thu, 25 Aug 2016 20:41:30 +0000 (20:41 +0000)]
ARM: by default don't set the Thumb bit on MachO relocated values.
Its existence is largely historical, apparently we tried to make ARM object
files look maybe-almost-possibly runnable by putting our best guess at the
actual value into relocated locations. Of course, the real linker then comes
along and can completely change things.
But it should only be there for word-sized and movw/movt relocations. It can't
be encoded in branch relocations, and I've seen it mess up validity
calculations twice in the last couple of weeks so the default is clearly problematic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279773
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Hemant Kulkarni [Thu, 25 Aug 2016 19:41:08 +0000 (19:41 +0000)]
llvm-objdump: ELF: Handle code and data mix in all scenarios
Differential Revision: https://reviews.llvm.org/D23621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279770
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Tim Shen [Thu, 25 Aug 2016 19:27:26 +0000 (19:27 +0000)]
[MemCpy] Check for alias in performMemCpyToMemSetOptzn, instead of the identity of two operands
Summary:
This fixes pr29105. The reason is that lifetime marks creates new
aliasing pointers the original ones, but before this patch aliases
were not checked in performMemCpyToMemSetOptzn.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279769
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Michael Kuperstein [Thu, 25 Aug 2016 18:50:56 +0000 (18:50 +0000)]
Reuse an SDLoc throughout a function. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279767
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Tim Northover [Thu, 25 Aug 2016 17:37:44 +0000 (17:37 +0000)]
GlobalISel: add missing type to G_UADDE instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279762
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Tim Northover [Thu, 25 Aug 2016 17:37:41 +0000 (17:37 +0000)]
GlobalISel: mark overflow bit of overflow ops legal.
It's expected this will map to NZCV register class and be properly selectable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279761
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Tim Northover [Thu, 25 Aug 2016 17:37:39 +0000 (17:37 +0000)]
GlobalISel: mark simple ops legal even on types < 32-bit.
The 32-bit variants of these operations don't depend on the bits not being
operated on, so they also naturally model operations narrower than the actual
register width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279760
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Tim Northover [Thu, 25 Aug 2016 17:37:35 +0000 (17:37 +0000)]
GlobalISel: mark pointer constants as legal on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279759
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Tim Northover [Thu, 25 Aug 2016 17:37:32 +0000 (17:37 +0000)]
GlobalISel: perform multi-step legalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279758
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Tim Northover [Thu, 25 Aug 2016 17:37:25 +0000 (17:37 +0000)]
GlobalISel: mark small extends as legal on AArch64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279757
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Chris Bieneman [Thu, 25 Aug 2016 17:18:41 +0000 (17:18 +0000)]
Hooking up a check-all target for the runtimes projects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279756
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Michael Kuperstein [Thu, 25 Aug 2016 17:17:46 +0000 (17:17 +0000)]
[X86] 512-bit VPAVG requires AVX512BW
Fix VPAVG detection to require AVX512BW, not AVX512F for 512-bit widths,
and change associated asserts to assert in the right direction...
This fixes PR29111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279755
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Simon Pilgrim [Thu, 25 Aug 2016 17:02:00 +0000 (17:02 +0000)]
[X86][SSE] INSERTPS is only combined on v4f32 types. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279751
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Ron Lieberman [Thu, 25 Aug 2016 16:46:09 +0000 (16:46 +0000)]
[Hexagon] Remove extraneous debug output from HexagonCopyToCombine.cpp
BB# ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279750
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Wei Mi [Thu, 25 Aug 2016 16:17:18 +0000 (16:17 +0000)]
[UNROLL] Postpone ScalarEvolution::forgetLoop after TripCountSC is expanded
when unroll runtime iteration loop.
In llvm::UnrollRuntimeLoopRemainder, if the loop to be unrolled is the inner
loop inside a loop nest, the scalar evolution needs to be dropped for its
parent loop which is done by ScalarEvolution::forgetLoop. However, we can
postpone forgetLoop to the end of UnrollRuntimeLoopRemainder so TripCountSC
expansion can still reuse existing value.
Differential Revision: https://reviews.llvm.org/D23572
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279748
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Simon Pilgrim [Thu, 25 Aug 2016 15:45:27 +0000 (15:45 +0000)]
Fix line endings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279745
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Ron Lieberman [Thu, 25 Aug 2016 13:35:48 +0000 (13:35 +0000)]
[Hexagon] vector store print tracing.
Add vector store print tracing option for hexagon vector instructions.
https://reviews.llvm.org/D23870
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279739
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Simon Pilgrim [Thu, 25 Aug 2016 12:50:13 +0000 (12:50 +0000)]
[X86][AVX] Improved AVX512F/AVX512VL SubVectorBroadcast tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279736
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Simon Pilgrim [Thu, 25 Aug 2016 12:45:16 +0000 (12:45 +0000)]
[X86][AVX] Provide SubVectorBroadcast fallback if load fold fails (PR29133)
Fix for PR29133, matching the approach that was taken for AVX1 scalar broadcasts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279735
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Sebastian Pop [Thu, 25 Aug 2016 11:55:47 +0000 (11:55 +0000)]
GVN-hoist: fix hoistingFromAllPaths for loops (PR29034)
It is invalid to hoist stores or loads if they are not executed on all paths
from the hoisting point to the exit of the function. In the testcase, there are
paths in the loop that do not execute the stores or the loads, and so hoisting
them within the loop is unsafe.
The problem is that the current implementation of hoistingFromAllPaths is
incomplete: it walks all blocks dominated by the hoisting point, and does not
return false when the loop contains a path on which the hoisted ld/st is
not executed.
Differential Revision: https://reviews.llvm.org/D23843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279732
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Craig Topper [Thu, 25 Aug 2016 04:16:10 +0000 (04:16 +0000)]
[X86] Simplify getOperandBias as a bit. NFC
There's no reason for it to return a signed type. Just return the operand bias in each if instead of starting from 0 and adding in the 'if'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279720
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Craig Topper [Thu, 25 Aug 2016 04:16:08 +0000 (04:16 +0000)]
[X86] Fix indentation per coding standards. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279719
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Vitaly Buka [Thu, 25 Aug 2016 03:44:36 +0000 (03:44 +0000)]
Fixed comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279718
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Vitaly Buka [Thu, 25 Aug 2016 03:32:49 +0000 (03:32 +0000)]
[asan] Disable CreateSigAltStack from Unix/Signals.inc for asan builds
Summary: Asan fails to UnsetAlternateSignalStack if it set by Unix/Signals.inc
Reviewers: kcc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279717
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George Burgess IV [Thu, 25 Aug 2016 02:15:54 +0000 (02:15 +0000)]
Make buildbots happy.
"warning: extra ‘;’ [-Wpedantic]"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279703
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Kyle Butt [Thu, 25 Aug 2016 01:37:07 +0000 (01:37 +0000)]
TailDuplication: Don't pass MMI separately from MF. NFC
MMI must match the function passed, and MF has a handle on MMI. Use that instead
of accepting it as separate argument. No Functional Change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279701
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Kyle Butt [Thu, 25 Aug 2016 01:37:03 +0000 (01:37 +0000)]
TailDuplication: Save MF and reduce number of parameters. NFC
Save the function in the class, and then don't pass it around. This reduces the
number of parameters and makes calls to member functions simpler.
No Functional Change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279700
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George Burgess IV [Thu, 25 Aug 2016 01:29:55 +0000 (01:29 +0000)]
Update a comment.
r279696, which changed `LLVM_CONSTEXPR AliasAttr` to `const AliasAttr`,
made this comment make less sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279699
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Matthias Braun [Thu, 25 Aug 2016 01:27:13 +0000 (01:27 +0000)]
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of
running after register and simply describes that no vregs are used in
a machine function. With that we can simply compute the property and do
not need to dump/parse it in .mir files.
Differential Revision: http://reviews.llvm.org/D23850
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279698
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Kostya Serebryany [Thu, 25 Aug 2016 01:25:03 +0000 (01:25 +0000)]
[libFuzzer] simplify the code, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279697
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George Burgess IV [Thu, 25 Aug 2016 01:05:08 +0000 (01:05 +0000)]
Make some LLVM_CONSTEXPR variables const. NFC.
This patch changes LLVM_CONSTEXPR variable declarations to const
variable declarations, since LLVM_CONSTEXPR expands to nothing if the
current compiler doesn't support constexpr. In all of the changed
cases, it looks like the code intended the variable to be const instead
of sometimes-constexpr sometimes-not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279696
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Eugene Zelenko [Thu, 25 Aug 2016 00:45:04 +0000 (00:45 +0000)]
Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes.
Differential revision: https://reviews.llvm.org/D23861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279695
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Xinliang David Li [Thu, 25 Aug 2016 00:26:32 +0000 (00:26 +0000)]
[Profile] Propagate branch metadata properly in instcombine
Differential Revision: http://reviews.llvm.org/D23590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279693
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Kyle Butt [Thu, 25 Aug 2016 00:06:52 +0000 (00:06 +0000)]
Test: Add REQUIRES: asserts to test that now requires stats.
Test was modified in r279670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279690
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Kostya Serebryany [Wed, 24 Aug 2016 23:10:17 +0000 (23:10 +0000)]
[libFuzzer] make a test more deterministic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279686
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Sanjay Patel [Wed, 24 Aug 2016 23:03:36 +0000 (23:03 +0000)]
[InstCombine] move foldICmpDivConstConst() contents to foldICmpDivConstant(); NFCI
There was no logic in foldICmpDivConstant, so no need for a separate function.
The code is directly copy/pasted, so further cleanups to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279685
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Evgeny Stupachenko [Wed, 24 Aug 2016 23:01:33 +0000 (23:01 +0000)]
The patch improves ValueTracking on left shift with nsw flag.
Summary:
The patch fixes PR28946.
Reviewers: majnemer, sanjoy
Differential Revision: http://reviews.llvm.org/D23296
From: Li Huang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279684
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Heejin Ahn [Wed, 24 Aug 2016 22:53:00 +0000 (22:53 +0000)]
[WebAssembly] Change a comment line
Test for commit access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279683
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Matthias Braun [Wed, 24 Aug 2016 22:41:46 +0000 (22:41 +0000)]
MIRYamlMapping cleanup
Missed two lines got lost when cherry picking old commits to master.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279682
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Krzysztof Parzyszek [Wed, 24 Aug 2016 22:36:35 +0000 (22:36 +0000)]
[Hexagon] Check for block end when skipping debug instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279681
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Matthias Braun [Wed, 24 Aug 2016 22:34:06 +0000 (22:34 +0000)]
MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279680
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Matthias Braun [Wed, 24 Aug 2016 22:32:11 +0000 (22:32 +0000)]
Missed a test in my last commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279679
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Krzysztof Parzyszek [Wed, 24 Aug 2016 22:27:36 +0000 (22:27 +0000)]
[Hexagon] Change insertion of expand-condsets pass to avoid memory leaks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279678
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Sanjay Patel [Wed, 24 Aug 2016 22:22:06 +0000 (22:22 +0000)]
[InstCombine] use m_APInt to allow icmp eq/ne (shr X, C2), C folds for splat constant vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279677
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Matthias Braun [Wed, 24 Aug 2016 22:17:45 +0000 (22:17 +0000)]
MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it
tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there
is not need to change it or save/parse it in a .mir file.
Make the field const and move the initialization LiveIntervalAnalysis to the
MachineRegisterInfo constructor. Also cleanup some code and fix some
instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead
of TargetSubtargetInfo::enableSubRegLiveness().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279676
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Kyle Butt [Wed, 24 Aug 2016 21:34:27 +0000 (21:34 +0000)]
CodeGen: If Convert blocks that would form a diamond when tail-merged.
The following function currently relies on tail-merging for if
conversion to succeed. The common tail of cond_true and cond_false is
extracted, and this then forms a diamond pattern that can be
successfully if converted.
If this block does not get extracted, either because tail-merging is
disabled or the threshold is higher, we should still recognize this
pattern and if-convert it.
Fixed a regression in the original commit. Need to un-reverse branches after
reversing them, or other conversions go awry.
define i32 @t2(i32 %a, i32 %b) nounwind {
entry:
%tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp1434, label %bb17, label %bb.outer
bb.outer: ; preds = %cond_false, %entry
%b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ]
%a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ]
br label %bb
bb: ; preds = %cond_true, %bb.outer
%indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ]
%tmp. = sub i32 0, %b_addr.021.0.ph
%tmp.40 = mul i32 %indvar, %tmp.
%a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph
%tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph
br i1 %tmp3, label %cond_true, label %cond_false
cond_true: ; preds = %bb
%tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph
%tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph
%indvar.next = add i32 %indvar, 1
br i1 %tmp1437, label %bb17, label %bb
cond_false: ; preds = %bb
%tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0
%tmp14 = icmp eq i32 %a_addr.026.0, %tmp10
br i1 %tmp14, label %bb17, label %bb.outer
bb17: ; preds = %cond_false, %cond_true, %entry
%a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ]
ret i32 %a_addr.026.1
}
Without tail-merging or diamond-tail if conversion:
LBB1_1: @ %bb
@ =>This Inner Loop Header: Depth=1
cmp r0, r1
ble LBB1_3
@ BB#2: @ %cond_true
@ in Loop: Header=BB1_1 Depth=1
subs r0, r0, r1
cmp r1, r0
it ne
cmpne r0, r1
bgt LBB1_4
LBB1_3: @ %cond_false
@ in Loop: Header=BB1_1 Depth=1
subs r1, r1, r0
cmp r1, r0
bne LBB1_1
LBB1_4: @ %bb17
bx lr
With diamond-tail if conversion, but without tail-merging:
@ BB#0: @ %entry
cmp r0, r1
it eq
bxeq lr
LBB1_1: @ %bb
@ =>This Inner Loop Header: Depth=1
cmp r0, r1
ite le
suble r1, r1, r0
subgt r0, r0, r1
cmp r1, r0
bne LBB1_1
@ BB#2: @ %bb17
bx lr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279671
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Kyle Butt [Wed, 24 Aug 2016 21:34:24 +0000 (21:34 +0000)]
IfConversion: Rescan diamonds.
The cost of predicating a diamond is only the instructions that are not shared
between the two branches. Additionally If a predicate clobbering instruction
occurs in the shared portion of the branches (e.g. a cond move), it may still
be possible to if convert the sub-cfg. This change handles these two facts by
rescanning the non-shared portion of a diamond sub-cfg to recalculate both the
predication cost and whether both blocks are pred-clobbering.
Fixed 2 bugs before recommitting. Branch instructions must be compared and found
identical before diamond conversion. Also, predicate-clobbering instructions in
the shared prefix disqualifies a potential diamond conversion. Includes tests
for both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279670
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Tim Northover [Wed, 24 Aug 2016 21:21:29 +0000 (21:21 +0000)]
ARM: don't diagnose cbz/cbnz to Thumb functions.
A branch-distance to a Thumb function shouldn't be forced to be odd for
CBZ/CBNZ instructions because (assuming it's within range), it's going to be a
valid, even offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279665
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Changpeng Fang [Wed, 24 Aug 2016 20:35:23 +0000 (20:35 +0000)]
AMDGCN/SI: Implement readlane/readfirstlane intrinsics
Summary:
This patch implements readlane/readfirstlane intrinsics.
TODO: need to define a new register class to consider the case
that the source could be a vector register or M0.
Reviewed by:
arsenm and tstellarAMD
Differential Revision:
http://reviews.llvm.org/D22489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279660
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Rafael Espindola [Wed, 24 Aug 2016 19:02:29 +0000 (19:02 +0000)]
Use isTargetMachO instead of isTargetDarwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279655
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Simon Pilgrim [Wed, 24 Aug 2016 18:40:53 +0000 (18:40 +0000)]
[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support
These are no different in load behaviour to the existing ADD/SUB/MUL/DIV scalar ops but were missing from isNonFoldablePartialRegisterLoad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279652
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David Blaikie [Wed, 24 Aug 2016 18:29:49 +0000 (18:29 +0000)]
DebugInfo: Add flag to CU to disable emission of inline debug info into the skeleton CU
In cases where .dwo/.dwp files are guaranteed to be available, skipping
the extra online (in the .o file) inline info can save a substantial
amount of space - see the original r221306 for more details there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279650
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Matthew Simpson [Wed, 24 Aug 2016 18:23:17 +0000 (18:23 +0000)]
[LV] Unify vector and scalar maps
This patch unifies the data structures we use for mapping instructions from the
original loop to their corresponding instructions in the new loop. Previously,
we maintained two distinct maps for this purpose: WidenMap and ScalarIVMap.
WidenMap maintained the vector values each instruction from the old loop was
represented with, and ScalarIVMap maintained the scalar values each scalarized
induction variable was represented with. With this patch, all values created
for the new loop are maintained in VectorLoopValueMap.
The change allows for several simplifications. Previously, when an instruction
was scalarized, we had to insert the scalar values into vectors in order to
maintain the mapping in WidenMap. Then, if a user of the scalarized value was
also scalar, we had to extract the scalar values from the temporary vector we
created. We now aovid these unnecessary scalar-to-vector-to-scalar conversions.
If a scalarized value is used by a scalar instruction, the scalar value is used
directly. However, if the scalarized value is needed by a vector instruction,
we generate the needed insertelement instructions on-demand.
A common idiom in several locations in the code (including the scalarization
code), is to first get the vector values an instruction from the original loop
maps to, and then extract a particular scalar value. This patch adds
getScalarValue for this purpose along side getVectorValue as an interface into
VectorLoopValueMap. These functions work together to return the requested
values if they're available or to produce them if they're not.
The mapping has also be made less permissive. Entries can be added to
VectorLoopValue map with the new initVector and initScalar functions.
getVectorValue has been modified to return a constant reference to the mapped
entries.
There's no real functional change with this patch; however, in some cases we
will generate slightly different code. For example, instead of an insertelement
sequence following the definition of an instruction, it will now precede the
first use of that instruction. This can be seen in the test case changes.
Differential Revision: https://reviews.llvm.org/D23169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279649
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Evandro Menezes [Wed, 24 Aug 2016 18:17:30 +0000 (18:17 +0000)]
[AArch64] Adjust the feature set for Exynos M1.
Enable zero cycle zeroing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279648
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Sanjoy Das [Wed, 24 Aug 2016 18:10:21 +0000 (18:10 +0000)]
[SCCP] Don't delete side-effecting instructions
I'm not sure if the `!isa<CallInst>(Inst) &&
!isa<TerminatorInst>(Inst))` bit is correct either, but this fixes the
case we know is broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279647
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Simon Pilgrim [Wed, 24 Aug 2016 18:07:53 +0000 (18:07 +0000)]
[X86][SSE] Add support for combining VZEXT_MOVL target shuffles
Includes adding more general support for the pattern: VZEXT_MOVL(VZEXT_LOAD(ptr)) -> VZEXT_LOAD(ptr)
This has unearthed a couple of latent poor codegen issues (MINSS/MAXSS scalar load folding and MOVDDUP/BROADCAST load folding patterns), which will be fixed shortly.
Its also reduced a couple of tests so that they no longer reach the instruction threshold necessary to be combined to PSHUFB (see PR26183).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279646
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Krzysztof Parzyszek [Wed, 24 Aug 2016 17:17:39 +0000 (17:17 +0000)]
[Hexagon] Enable subregister liveness tracking
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279642
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