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Emil Velikov [Mon, 12 Aug 2013 02:48:48 +0000 (22:48 -0400)]
drm/nouveau/therm: Set the correct pwm_mode upon resume
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Tested-by: Martin Peres <martin.peres@labri.fr>
Tested-by: Dash Four <mr.dash.four@googlemail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Maarten Lankhorst [Wed, 7 Aug 2013 15:11:27 +0000 (17:11 +0200)]
drm/nouveau: require contiguous bo for framebuffer
This was already required before, but no check in the kernel was done
to enforce it.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Emil Velikov [Tue, 30 Jul 2013 00:01:10 +0000 (01:01 +0100)]
drm/nv50-/disp: use the number of dac, sor, pior rather than hardcoded values
The values are already stored on chipset specific basis in the ctor.
Make the most of them and simplify the code further by using a temporary
variable to avoid code duplication.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ilia Mirkin [Mon, 29 Jul 2013 23:05:16 +0000 (19:05 -0400)]
drm/nouveau: remove duplicate copy of nv44_graph_class
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ilia Mirkin [Mon, 29 Jul 2013 02:30:06 +0000 (22:30 -0400)]
drm/nouveau/vdec: implement support for VP3 engines
For NV98+, BSP/VP/PPP are all FUC-based engines. Hook them all up in the
same way as NVC0, but with a couple of different values. Also make sure
that the PPP engine is handled in the fifo/mc/vm.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ilia Mirkin [Sat, 27 Jul 2013 04:27:00 +0000 (00:27 -0400)]
drm/nouveau/core: get rid of math.h, replace log2i with order_base_2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Dave Airlie [Tue, 3 Sep 2013 23:01:02 +0000 (09:01 +1000)]
Merge tag 'drm/for-3.12-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v3.12-rc1
Only a couple of small patches this time around. These are mostly fixes
for minor bugs that showed up, but there is also some preparatory work
that will come in handy for future patches.
* tag 'drm/for-3.12-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/tegra: Parse device tree earlier
gpu: host1x: Sort drivers by probe order
gpu: host1x: Check for valid host1x pointer
gpu: host1x: returning success instead of -ENOMEM
gpu: host1x: fix an integer overflow check
drm/tegra: hdmi: Make sure clock is enabled before dumping registers
Thierry Reding [Fri, 30 Aug 2013 13:27:16 +0000 (15:27 +0200)]
drm/tegra: Parse device tree earlier
Parsing the device tree may cause probing to be deferred. Doing this as
early as possible prevents any other resources from being requested and
enabled, therefore reducing the need to cleanup on deferred probe while
at the same time not wasting precious CPU cycles determining if probing
needs to be deferred or not.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 3 Sep 2013 07:02:22 +0000 (09:02 +0200)]
gpu: host1x: Sort drivers by probe order
External driver declarations are sorted by probe order for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 3 Sep 2013 06:50:39 +0000 (08:50 +0200)]
gpu: host1x: Check for valid host1x pointer
Under rare circumstances it can happen that the host1x driver's .probe()
doesn't finish properly, in which case the device's driver-specific data
will not be set. Instead of crashing in such a situation, propagate the
error to callers of the host1x_get_drm_data() function.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Christian König [Sun, 25 Aug 2013 16:29:03 +0000 (18:29 +0200)]
drm/radeon: support render nodes
Enable support for drm render nodes for radeon by flagging the ioctls that
are safe and just needed for rendering.
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Martin Peres [Sun, 25 Aug 2013 16:29:02 +0000 (18:29 +0200)]
drm/nouveau: Support render nodes
Enable support for drm render nodes for nouveau by flagging the ioctls that
are safe and just needed for rendering.
Cc: Ben Skeggs <bskeggs@redhat.com>
Cc: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kristian Høgsberg [Sun, 25 Aug 2013 16:29:01 +0000 (18:29 +0200)]
drm/i915: Support render nodes
Enable support for drm render nodes for i915 by flagging the ioctls that
are safe and just needed for rendering.
v2: mark reg_read, set_caching and get_caching (ickle, danvet)
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
David Herrmann [Mon, 26 Aug 2013 13:16:49 +0000 (15:16 +0200)]
drm: fix DRM_IOCTL_MODE_GETFB handle-leak
DRM_IOCTL_MODE_GETFB is used to retrieve information about a given
framebuffer ID. It is a read-only helper and was thus declassified for
unprivileged access in:
commit
a14b1b42477c5ef089fcda88cbaae50d979eb8f9
Author: Mandeep Singh Baines <mandeep.baines@gmail.com>
Date: Fri Jan 20 12:11:16 2012 -0800
drm: remove master fd restriction on mode setting getters
However, alongside width, height and stride information,
DRM_IOCTL_MODE_GETFB also passes back a handle to the underlying buffer of
the framebuffer. This handle allows users to mmap() it and read or write
into it. Obviously, this should be restricted to DRM-Master.
With the current setup, *any* process with access to /dev/dri/card0 (which
means any process with access to hardware-accelerated rendering) can
access the current screen framebuffer and modify it ad libitum.
For backwards-compatibility reasons we want to keep the
DRM_IOCTL_MODE_GETFB call unprivileged. Besides, it provides quite useful
information regarding screen setup. So we simply test whether the caller
is the current DRM-Master and if not, we return 0 as handle, which is
always invalid. A following DRM_IOCTL_GEM_CLOSE on this handle will fail
with EINVAL, but we accept this. Users shouldn't test for errors during
GEM_CLOSE, anyway. And it is still better as a failing MODE_GETFB call.
v2: add capable(CAP_SYS_ADMIN) check for compatibility with i-g-t
Cc: <stable@vger.kernel.org>
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Rob Clark [Fri, 30 Aug 2013 17:02:15 +0000 (13:02 -0400)]
drm/msm: convert to drm_bridge
Drop the msm_connector base class, and special calls to base class
methods from the encoder, and use instead drm_bridge. This allows for a
cleaner division between the hdmi (and in future dsi) blocks, from the
mdp block.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Sean Paul [Wed, 14 Aug 2013 20:47:37 +0000 (16:47 -0400)]
drm: Add drm_bridge
This patch adds the notion of a drm_bridge. A bridge is a chained
device which hangs off an encoder. The drm driver using the bridge
should provide the association between encoder and bridge. Once a
bridge is associated with an encoder, it will participate in mode
set, and dpms (via the enable/disable hooks).
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 1 Sep 2013 23:52:55 +0000 (09:52 +1000)]
drm/nouveau: fix up 32-bit ioctls and device wake up.
Noticed by kbuild test robot.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 1 Sep 2013 23:47:56 +0000 (09:47 +1000)]
drm/tegra: fix up page flip flags.
This was one level away from where I'd grepped.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 1 Sep 2013 23:31:40 +0000 (09:31 +1000)]
Merge branch 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux into drm-next
Alex writes:
This is the radeon drm-next request. Big changes include:
- support for dpm on CIK parts
- support for ASPM on CIK parts
- support for berlin GPUs
- major ring handling cleanup
- remove the old 3D blit code for bo moves in favor of CP DMA or sDMA
- lots of bug fixes
[airlied: fix up a bunch of conflicts from drm_order removal]
* 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux: (898 commits)
drm/radeon/dpm: make sure dc performance level limits are valid (CI)
drm/radeon/dpm: make sure dc performance level limits are valid (BTC-SI) (v2)
drm/radeon: gcc fixes for extended dpm tables
drm/radeon: gcc fixes for kb/kv dpm
drm/radeon: gcc fixes for ci dpm
drm/radeon: gcc fixes for si dpm
drm/radeon: gcc fixes for ni dpm
drm/radeon: gcc fixes for trinity dpm
drm/radeon: gcc fixes for sumo dpm
drm/radeonn: gcc fixes for rv7xx/eg/btc dpm
drm/radeon: gcc fixes for rv6xx dpm
drm/radeon: gcc fixes for radeon_atombios.c
drm/radeon: enable UVD interrupts on CIK
drm/radeon: fix init ordering for r600+
drm/radeon/dpm: only need to reprogram uvd if uvd pg is enabled
drm/radeon: check the return value of uvd_v1_0_start in uvd_v1_0_init
drm/radeon: split out radeon_uvd_resume from uvd_v4_2_resume
radeon kms: fix uninitialised hotplug work usage in r100_irq_process()
drm/radeon/audio: set up the sads on DCE3.2 asics
drm/radeon: fix handling of variable sized arrays for router objects
...
Conflicts:
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_gem_dmabuf.c
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/radeon/cik.c
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/r600.c
Alex Deucher [Fri, 30 Aug 2013 20:24:33 +0000 (16:24 -0400)]
drm/radeon/dpm: make sure dc performance level limits are valid (CI)
Check to make sure the dc limits are valid before using them.
Some systems may not have a dc limits table. In that case just
use the ac limits. This fixes hangs on systems when the power
state is changed when on battery (dc) due to invalid performance
state parameters.
Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=68708
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 30 Aug 2013 20:18:35 +0000 (16:18 -0400)]
drm/radeon/dpm: make sure dc performance level limits are valid (BTC-SI) (v2)
Check to make sure the dc limits are valid before using them.
Some systems may not have a dc limits table. In that case just
use the ac limits. This fixes hangs on systems when the power
state is changed when on battery (dc) due to invalid performance
state parameters.
Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=68708
v2: fix up limits in dpm_init()
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Fri, 23 Aug 2013 19:28:42 +0000 (15:28 -0400)]
drm/radeon: gcc fixes for extended dpm tables
Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 20 Aug 2013 23:09:54 +0000 (19:09 -0400)]
drm/radeon: gcc fixes for kb/kv dpm
Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 20 Aug 2013 23:08:22 +0000 (19:08 -0400)]
drm/radeon: gcc fixes for ci dpm
Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 20 Aug 2013 23:06:54 +0000 (19:06 -0400)]
drm/radeon: gcc fixes for si dpm
Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 20 Aug 2013 23:04:02 +0000 (19:04 -0400)]
drm/radeon: gcc fixes for ni dpm
Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 20 Aug 2013 23:02:14 +0000 (19:02 -0400)]
drm/radeon: gcc fixes for trinity dpm
Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 20 Aug 2013 22:59:41 +0000 (18:59 -0400)]
drm/radeon: gcc fixes for sumo dpm
Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 20 Aug 2013 22:51:08 +0000 (18:51 -0400)]
drm/radeonn: gcc fixes for rv7xx/eg/btc dpm
Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 20 Aug 2013 22:47:07 +0000 (18:47 -0400)]
drm/radeon: gcc fixes for rv6xx dpm
Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 20 Aug 2013 22:40:46 +0000 (18:40 -0400)]
drm/radeon: gcc fixes for radeon_atombios.c
Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 30 Aug 2013 09:10:33 +0000 (11:10 +0200)]
drm/radeon: enable UVD interrupts on CIK
The same as on evergreen.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reported-by: FrankR Huang <FrankR.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Fri, 30 Aug 2013 12:58:20 +0000 (08:58 -0400)]
drm/radeon: fix init ordering for r600+
The vram scratch buffer needs to be initialized
before the mc is programmed otherwise we program
0 as the GPU address of the default GPU fault
page. In most cases we put vram at zero anyway and
reserve a page for the legacy vga buffer so in practice
this shouldn't cause any problems, but better to make
it correct.
Was changed in:
6fab3febf6d949b0a12b1e4e73db38e4a177a79e
Reported-by: FrankR Huang <FrankR.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Wed, 28 Aug 2013 22:46:01 +0000 (18:46 -0400)]
drm/radeon/dpm: only need to reprogram uvd if uvd pg is enabled
Avoid needless uvd reprogramming if uvd powergating is disabled.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Alex Deucher [Wed, 28 Aug 2013 22:24:00 +0000 (18:24 -0400)]
drm/radeon: check the return value of uvd_v1_0_start in uvd_v1_0_init
No need to try the ring tests if starting the UVD block failed.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Alex Deucher [Wed, 28 Aug 2013 22:12:59 +0000 (18:12 -0400)]
drm/radeon: split out radeon_uvd_resume from uvd_v4_2_resume
For powergating, we just need to re-init the registers, there
is no need to restore the uvd BOs. This just adds needless
work when powergating uvd for playback while the system is
on. We only need to restore the uvd BOs on an actual resume
from suspend or when the driver loads.
This fixes multi-stream UVD playback on KB systems.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Sergey Senozhatsky [Thu, 29 Aug 2013 09:29:35 +0000 (12:29 +0300)]
radeon kms: fix uninitialised hotplug work usage in r100_irq_process()
Commit
a01c34f72e7cd2624570818f579b5ab464f93de2 (radeon kms: do not
flush uninitialized hotplug work) moved work initialisation phase to
the last step of radeon_irq_kms_init(). Meelis Roos reported that this
causes problems on his machine because drm_irq_install() uses hotplug
work on r100.
hotplug work flushed in radeon_irq_kms_fini(), with two possible cases:
-- radeon_irq_kms_fini() call after successful radeon_irq_kms_init()
-- radeon_irq_kms_fini() call after unsuccessful (or not called at all)
radeon_irq_kms_init()
The latter one causes flush work on uninitialised hotplug work. Move
work initialisation before drm_irq_install(), but keep existing agreement
to flush hotplug work in radeon_irq_kms_fini() only for `irq.installed'
(successful radeon_irq_kms_init()) case.
WARNING: CPU: 0 PID: 243 at kernel/workqueue.c:1378 __queue_work+0x132/0x16d()
Call Trace:
[<
c12319b3>] ? dump_stack+0xa/0x13
[<
c1022600>] ? warn_slowpath_common+0x75/0x8a
[<
c1031010>] ? __queue_work+0x132/0x16d
[<
c1031010>] ? __queue_work+0x132/0x16d
[<
c102269e>] ? warn_slowpath_null+0x1b/0x1f
[<
c1031010>] ? __queue_work+0x132/0x16d
[<
c103107b>] ? queue_work_on+0x30/0x40
[<
f8aed3f3>] ? r100_irq_process+0x16d/0x1e6 [radeon]
[<
f8ae77cf>] ? radeon_driver_irq_preinstall_kms+0xc2/0xc5 [radeon]
[<
f8974d77>] ? drm_irq_install+0xb2/0x1ac [drm]
[<
f897604d>] ? drm_vblank_init+0x196/0x1d2 [drm]
[<
f8ae78d3>] ? radeon_irq_kms_init+0x33/0xc6 [radeon]
[<
f8aef35a>] ? r100_startup+0x1a3/0x1d6 [radeon]
[<
f8ad77c8>] ? radeon_ttm_init+0x26e/0x287 [radeon]
[<
f8aef752>] ? r100_init+0x2b3/0x309 [radeon]
[<
c118082e>] ? vga_client_register+0x39/0x40
[<
f8ac535f>] ? radeon_device_init+0x54b/0x61b [radeon]
[<
f8ac40fd>] ? cail_mc_write+0x13/0x13 [radeon]
[<
f8ac6864>] ? radeon_driver_load_kms+0x82/0xda [radeon]
[<
f8978bbd>] ? drm_get_pci_dev+0x136/0x22d [drm]
[<
f8ac409b>] ? radeon_pci_probe+0x6c/0x86 [radeon]
[<
c112acf6>] ? pci_device_probe+0x4c/0x83
[<
c11846c7>] ? driver_probe_device+0x80/0x184
[<
c112a848>] ? pci_match_id+0x18/0x36
[<
c1184837>] ? __driver_attach+0x44/0x5f
[<
c11833f4>] ? bus_for_each_dev+0x50/0x5a
[<
c118433e>] ? driver_attach+0x14/0x16
[<
c11847f3>] ? __device_attach+0x28/0x28
[<
c1184045>] ? bus_add_driver+0xd6/0x1bf
[<
c1184c22>] ? driver_register+0x78/0xcf
[<
f8ba8000>] ? 0xf8ba7fff
[<
c10003bf>] ? do_one_initcall+0x8b/0x121
[<
c101e668>] ? change_page_attr_clear+0x2e/0x33
[<
f8ba8000>] ? 0xf8ba7fff
[<
c101e689>] ? set_memory_ro+0x1c/0x20
[<
c104de94>] ? set_page_attributes+0x11/0x12
[<
c104f6e1>] ? load_module+0x12fa/0x17e8
[<
c107483b>] ? map_vm_area+0x22/0x31
[<
c104fc36>] ? SyS_init_module+0x67/0x7d
[<
c1234245>] ? sysenter_do_call+0x12/0x26
Reported-by: Meelis Roos <mroos@linux.ee>
Tested-by: Meelis Roos <mroos@linux.ee>
Signed-off-by: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Thu, 29 Aug 2013 14:51:04 +0000 (10:51 -0400)]
drm/radeon/audio: set up the sads on DCE3.2 asics
This sets up the short audio descriptors properly on
DCE3.2 asics for hdmi audio.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 27 Aug 2013 16:36:01 +0000 (12:36 -0400)]
drm/radeon: fix handling of variable sized arrays for router objects
The table has the following format:
typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
{
UCHAR ucNumberOfSrc;
USHORT usSrcObjectID[1];
UCHAR ucNumberOfDst;
USHORT usDstObjectID[1];
}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
usSrcObjectID[] and usDstObjectID[] are variably sized, so we
can't access them directly. Use pointers and update the offset
appropriately when accessing the Dst members.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Mon, 26 Aug 2013 21:52:12 +0000 (17:52 -0400)]
drm/radeon: fix resume on some rs4xx boards (v2)
Setting MC_MISC_CNTL.GART_INDEX_REG_EN causes hangs on
some boards on resume. The systems seem to work fine
without touching this bit so leave it as is.
v2: read-modify-write the GART_INDEX_REG_EN bit.
I suspect the problem is that we are losing the other
settings in the register.
fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=52952
Reported-by: Ondrej Zary <linux@rainbow-software.org>
Tested-by: Daniel Tobias <dan.g.tob@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Mon, 10 Jun 2013 19:51:21 +0000 (15:51 -0400)]
drm/radeon: add berlin pci ids
This adds the pci ids for the berlin GPU core.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Mon, 10 Jun 2013 19:18:26 +0000 (15:18 -0400)]
drm/radeon: fill in gpu_init for berlin GPU cores
This fills in the GPU specific details for berlin
GPU cores so that the driver will work with them.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Mon, 26 Aug 2013 13:46:51 +0000 (09:46 -0400)]
drm/radeon/dpm: ungate blocks in dpm disable for kb/kv
These blocks need to be ungated for the other parts of
the driver properly initialize them (e.g., after a gpu
reset, etc.).
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 26 Aug 2013 13:43:24 +0000 (09:43 -0400)]
drm/radeon/dpm: track uvd gated state for ci
Track the current uvd gated state on CI to avoid unnecessary
state changes when uvd is active.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 23 Aug 2013 15:06:12 +0000 (11:06 -0400)]
drm/radeon: enable uvd dpm on CI
UVD dpm dynamically adjusts the uvd clocks on
demand.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 21 Aug 2013 18:44:15 +0000 (14:44 -0400)]
drm/radeon: disable the GRPH block when we disable the crtc
Since we aren't using it when the crtc is disabled, turn it off
to save power. The GRPH block is the part of the display
controller that controls the primary graphics plane (size,
address, etc.).
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 21 Aug 2013 17:48:12 +0000 (13:48 -0400)]
drm/radeon: atombios hw i2c fixes
These fixes make writes work properly. Previously
only reads worked. Note that this feature is off
by default.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 20 Aug 2013 18:59:01 +0000 (14:59 -0400)]
drm/radeon: fix LCD record parsing
If the LCD table contains an EDID record, properly account
for the edid size when walking through the records.
This should fix error messages about unknown LCD records.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Mon, 19 Aug 2013 23:06:19 +0000 (19:06 -0400)]
drm/radeon: check firmware overrides for mclk/sclk ss
Check the overrides in the firmware info table before
enabling spread spectrum on the engine or memory clocks.
Some boards may have valid spread spectrum tables, but
shouldn't necessarily have it enabled.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 19 Aug 2013 15:39:27 +0000 (11:39 -0400)]
drm/radeon: update line buffer allocation for dce8
We need to allocate line buffer to each display when
setting up the watermarks. Failure to do so can lead
to a blank screen. This fixes blank screen problems
on dce8 asics.
Based on an initial fix from:
Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Mon, 19 Aug 2013 15:15:43 +0000 (11:15 -0400)]
drm/radeon: update line buffer allocation for dce6
We need to allocate line buffer to each display when
setting up the watermarks. Failure to do so can lead
to a blank screen. This fixes blank screen problems
on dce6 asics.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=64850
Based on an initial fix from:
Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Mon, 19 Aug 2013 15:06:50 +0000 (11:06 -0400)]
drm/radeon: update line buffer allocation for dce4.1/5
We need to allocate line buffer to each display when
setting up the watermarks. Failure to do so can lead
to a blank screen. This fixes blank screen problems
on dce4.1/5 asics.
Based on an initial fix from:
Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Tom Stellard [Fri, 16 Aug 2013 21:47:39 +0000 (17:47 -0400)]
drm/radeon/si: Add support for CP DMA to CS checker for compute v2
Also add a new RADEON_INFO query to check that CP DMA packets are
supported on the compute ring.
CP DMA has been supported since the 3.8 kernel, but due to an oversight
we forgot to teach the CS checker that the CP DMA packet was legal for
the compute ring on Southern Islands GPUs.
This patch fixes a bug where the radeon driver will incorrectly reject a legal
CP DMA packet from user space. I would like to have the patch
backported to stable so that we don't have to require Mesa users to use a
bleeding edge kernel in order to take advantage of this feature which
is already present in the stable kernels (3.8 and newer).
v2:
- Don't bump kms version, so this patch can be backported to stable
kernels.
Cc: stable@vger.kernel.org
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 14 Aug 2013 22:58:43 +0000 (18:58 -0400)]
drm/radeon: enable mgcg on CIK
Now that the CP is no longer reset and cg is properly
disabled in when appropriate in the dpm code we can
now enable mgcg (medium grained clockgating).
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 14 Aug 2013 23:55:46 +0000 (19:55 -0400)]
drm/radeon: handle cg in KB/KV dpm code
Clockgating needs to be disabled around certain parts
of dpm setup otherwise the smc gets into a bad state
and dpm doesn't work properly.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 14 Aug 2013 17:55:53 +0000 (13:55 -0400)]
drm/radeon: handle cg in CI dpm code
Clockgating needs to be disabled around certain parts
of dpm setup otherwise the smc gets into a bad state
and dpm doesn't work properly.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 22 Aug 2013 15:57:46 +0000 (11:57 -0400)]
drm/radeon/cik: properly set up the clearstate buffer for pg (v2)
The format of the clearstate buffer used for pg (powergating)
changed between NI and SI. This formats it properly for what
the hardware expects on SI+.
v2: fix addresses
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 12 Aug 2013 21:25:26 +0000 (17:25 -0400)]
drm/radeon: fixes for gfx clockgating on CIK
Clockgating requires signalling between the CP and the
RLC to work properly. Resetting the CP block in the
CP resume code messed up the internal coordination
between the blocks. Removing the reset allows gfx
clockgating to work properly. However, when gfx clock
gating is enabled, there is a strange interaction with
dpm which causes the chip to stay in the high performance
level all the time, so leave gfx clockgating disabled
for now.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 9 Aug 2013 15:18:39 +0000 (11:18 -0400)]
drm/radeon: restructure cg/pg on cik (v2)
- use new cg/pg flags for finer grained clock and
powergating control
- restructure the cg/pg code so it can be called from
other components such as dpm
v2: fix build breakage from rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 13 Aug 2013 17:18:37 +0000 (13:18 -0400)]
drm/radeon/si: enable DMA pg by default
Enable DMA powergating by default. The DMA engines
will be powergated when not in use.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 13 Aug 2013 16:48:06 +0000 (12:48 -0400)]
drm/radeon/si: properly set up the clearstate buffer for pg (v2)
The format of the clearstate buffer used for pg (powergating)
changed between NI and SI. This formats it properly for what
the hardware expects on SI.
v2: fix addresses
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 14 Aug 2013 22:53:56 +0000 (18:53 -0400)]
drm/radeon: enable mgcg on SI
Now that the CP is no longer reset and cg is properly
disabled in when appropriate in the dpm code we can
now enable mgcg (medium grained clockgating).
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 14 Aug 2013 21:24:08 +0000 (17:24 -0400)]
drm/radeon: handle cg in SI dpm code
Clockgating needs to be disabled around certain parts
of dpm setup otherwise the smc gets into a bad state
and dpm doesn't work properly.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 15 Aug 2013 20:20:26 +0000 (16:20 -0400)]
drm/radeon: fixes for gfx clockgating on SI
Clockgating requires signalling between the CP and the
RLC to work properly. Resetting the CP block in the
CP resume code messed up the internal coordination
between the blocks. Removing the reset allows gfx
clockgating to work properly. However, when gfx clock
gating is enabled, there is a strange interaction with
dpm which causes the chip to stay in the high performance
level all the time, so leave gfx clockgating disabled
for now.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 8 Aug 2013 23:34:07 +0000 (19:34 -0400)]
drm/radeon/si: restructure cg code (v3)
Resturcture clockgating code so that it can be
enabled/disabled from other components such as
dpm.
v2: make function static
v3: add fine grained cg controls
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 8 Aug 2013 22:00:10 +0000 (18:00 -0400)]
drm/radeon: use new cg/pg flags for SI
Allows us finer grained control over clock and
powergating on SI.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 8 Aug 2013 20:31:25 +0000 (16:31 -0400)]
drm/radeon: add cg and pg flags
This commits adds flags for supported clockgating and
powergating features. This allows us to more easily
track which features are supported on a particular
asic and to enable/disable features for debugging.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 15 Aug 2013 16:03:37 +0000 (12:03 -0400)]
drm/radeon: set speaker allocation for DCE3.2
This updates the audio driver to the speaker allocation
block from the EDID. A similar change was just implemented
for DCE4-8.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 15 Aug 2013 13:34:07 +0000 (09:34 -0400)]
drm/radeon: set speaker allocation for DCE4/5 (v2)
This updates the audio driver to the speaker allocation
block from the EDID. A similar change was just implemented
for DCE6/8.
v2: remove unused variables
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Rafał Miłecki <zajec5@gmail.com>
Rafał Miłecki [Thu, 15 Aug 2013 09:16:30 +0000 (11:16 +0200)]
drm/radeon: set speakers allocation earlier
Do it before enabling audio channels (in AFMT_AUDIO_PACKET_CONTROL2
register).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2013 20:51:33 +0000 (16:51 -0400)]
drm/radeon: add audio support for DCE6/8 GPUs (v12)
Similar to DCE4/5, but supports multiple audio pins
which can be assigned per afmt block.
v2: rework the driver to handle more than one audio
pin.
v3: try different dto reg
v4: properly program dto
v5 (ck): change dto programming order
v6: program speaker allocation block
v7: rebase
v8: rebase on Rafał's changes
v9: integrated Rafał's comments, update to latest
drm_edid_to_speaker_allocation API
v10: add missing line break in error message
v11: add back audio enabled messages
v12: fix copy paste typo in r600_audio_enable
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Rafał Miłecki <zajec5@gmail.com>
Rafał Miłecki [Thu, 1 Aug 2013 15:29:16 +0000 (17:29 +0200)]
drm/radeon: use loop for initializing AFMT blocks
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2013 19:55:32 +0000 (15:55 -0400)]
drm/edid: add a helper function to extract the speaker allocation data block (v3)
This adds a helper function to extract the speaker allocation
data block from the EDID. This data block describes what speakers
are present on the display device.
v2: update per Ville Syrjälä's comments
v3: fix copy/paste typo in memory allocation
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Rafał Miłecki <zajec5@gmail.com>
Christian König [Tue, 13 Aug 2013 09:56:54 +0000 (11:56 +0200)]
drm/radeon: separate DMA code
Similar to separating the UVD code, just put the DMA
functions into separate files.
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 13 Aug 2013 09:56:53 +0000 (11:56 +0200)]
drm/radeon: separate UVD code v3
Our different hardware blocks are actually completely
separated, so it doesn't make much sense any more to
structure the code by pure chipset generations.
Start restructuring the code by separating our the UVD block.
v2: updated commit message
v3: rebased and restructurized start/stop functions for kv dpm.
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 13 Aug 2013 09:56:52 +0000 (11:56 +0200)]
drm/radeon: remove special handling for the DMA ring
Now that we have callbacks for [rw]ptr handling we can
remove the special handling for the DMA rings and use
the callbacks instead.
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 13 Aug 2013 09:56:51 +0000 (11:56 +0200)]
drm/radeon: rework UVD writeback & [rw]ptr handling
The hardware just doesn't support this correctly.
Disable it before we accidentally write anywhere we shouldn't.
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 13 Aug 2013 09:56:50 +0000 (11:56 +0200)]
drm/radeon: rework ring function handling
Give the ring functions a separate structure and let the asic
structure point to the ring specific functions. This simplifies
the code and allows us to make changes at only one point.
No change in functionality.
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 7 Aug 2013 23:34:53 +0000 (19:34 -0400)]
drm/radeon: fix endian bugs in hw i2c atom routines
Need to swap the data fetched over i2c properly. This
is the same fix as the endian fix for aux channel
transactions.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Mon, 12 Aug 2013 15:35:02 +0000 (11:35 -0400)]
drm/radeon/dpm: adjust the vblank time checks for eg, ni, si
According to the internal teams, we never hit the limit for
mclk switching on these asics, so we can disable the check.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 12 Aug 2013 15:24:05 +0000 (11:24 -0400)]
drm/radeon/dpm: add reclocking quirk for ASUS K70AF
The LCD has a relatively short vblank time (216us), but
the card is able to reclock memory fine in that time.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reported-by: normalrawr@gmail.com
Alex Deucher [Fri, 9 Aug 2013 14:05:24 +0000 (10:05 -0400)]
drm/radeon/dpm: implement UVD powergating for CI
Disable the UVD block when not in use to save power.
The block is not actually powergated on CI, but we
switch between UVD DPM (where the uvd clocks are
adjusted on demand) and clocks off.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 9 Aug 2013 14:02:40 +0000 (10:02 -0400)]
drm/radeon/dpm: implement UVD powergating for KB/KV
Powergate the UVD block when not in use to save power.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 6 Aug 2013 15:39:38 +0000 (11:39 -0400)]
drm/radeon: restructure UVD code to handle UVD PG (v2)
When we PG (powergate) UVD, we need to re-initialize it
before we can use it again.
v2: rebase on UVD stop fixes
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2013 22:13:23 +0000 (18:13 -0400)]
drm/radeon/dpm: add new callback for powergating UVD (v4)
Starting on CIK, multi-media blocks like UVD no longer
have special power state. Rather they have their own
DPM implementation which adjusts their clocks dynamically
when active. When they are not active, the blocks are
powergated to save power.
v2: add missing pm locks
v3: rebase on uvd state selection rework
v4: fix inverted logic typo noticed by Christian
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 18 Jul 2013 20:48:46 +0000 (16:48 -0400)]
drm/radeon/dpm: implement force performance level for KB/KV
Allows you to force the selected performance level via sysfs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 18 Jul 2013 20:39:53 +0000 (16:39 -0400)]
drm/radeon/dpm: add debugfs support for KB/KV
This allows you to look at the current DPM state via
debugfs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 15 Jul 2013 22:24:31 +0000 (18:24 -0400)]
drm/radeon/dpm: implement vblank_too_short callback for CI
Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 15 Jul 2013 22:14:24 +0000 (18:14 -0400)]
drm/radeon/dpm: implement force performance level for CI
Allows you to force the selected performance level via sysfs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 15 Jul 2013 21:34:33 +0000 (17:34 -0400)]
drm/radeon/dpm: add debugfs support for CI
This allows you to look at the current DPM state via debugfs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 14 Aug 2013 05:03:41 +0000 (01:03 -0400)]
drm/radeon: add dpm support for CI dGPUs (v2)
This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching
Set radeon.dpm=1 to enable.
v2: remove unused radeon_atombios.c changes,
make missing smc ucode non-fatal
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 14 Aug 2013 05:01:40 +0000 (01:01 -0400)]
drm/radeon/kms: add dpm support for KB/KV
This adds dpm support for KB/KV asics. This includes:
- dynamic engine clock scaling
- dynamic voltage scaling
- power containment
- shader power scaling
Set radeon.dpm=1 to enable.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 19 Jul 2013 16:42:08 +0000 (12:42 -0400)]
drm/radeon/dpm: add helper to fetch the vrefresh of the current mode
Needed for DPM on CI.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 15 May 2013 21:25:03 +0000 (17:25 -0400)]
drm/radeon/dpm: add a helper to encode pcie lane setting
convert from number of lanes to register setting.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 15 May 2013 19:53:57 +0000 (15:53 -0400)]
drm/radeon/dpm: add vce clocks to radeon_ps
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 14 May 2013 21:44:31 +0000 (17:44 -0400)]
drm/radeon: add r600_get_pcie_lane_support helper
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 9 May 2013 21:34:45 +0000 (17:34 -0400)]
drm/radeon: parse the acp clock voltage deps table
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 9 May 2013 21:27:49 +0000 (17:27 -0400)]
drm/radeon: parse the samu clock voltage deps table
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 9 May 2013 21:21:56 +0000 (17:21 -0400)]
drm/radeon/dpm: clean up the extended table error pathes
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 9 May 2013 21:14:11 +0000 (17:14 -0400)]
drm/radeon: parse the uvd clock voltage deps table
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>