Merge remote-tracking branch 'mesa/19.3' into q-x86

docs: add sha256sum for 19.3.5

Signed-off-by: Eric Engestrom <eric@engestrom.ch>

VERSION: bump version to 19.3.5

Signed-off-by: Eric Engestrom <eric@engestrom.ch>

docs: add release notes for 19.3.5

Signed-off-by: Eric Engestrom <eric@engestrom.ch>

gitlab-ci: update template to fix container build issues

Signed-off-by: Eric Engestrom <eric@engestrom.ch>

anv: Parse VkPhysicalDeviceFeatures2 in CreateDevice

The client may enable robustBufferAccess2 via either
pCreateInfo->pEnabledFeatures or via a chained-in
VkPhysicalDeviceFeatures2 struct.  We need to parse both.

Fixes: 022e5c7e5a5 "anv: Implement VK_KHR_get_physical_device_properties2"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
(cherry picked from commit 35ca2ad22e20ad3bc3301ee1e9157b8c351d959e)

.pick_status.json: Update to 0103f02acb10dcdea23461ba214307a6827a7772

bin/gen_release_notes.py: fix commit list command

Fixes: 86079447da1e00d49db0 ("scripts: Add a gen_release_notes.py script")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4069>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4069>
(cherry picked from commit d7a70fbb2305604ce75b1a0dbcd03e2ebe71f92a)

iris: Don't skip fast depth clears if the color changed

We depend on BLORP to convert the clear color and write it into the
clear color buffer for us.  However, we weren't bothering to call blorp
in the case where the state is ISL_AUX_STATE_CLEAR.  This leads to the
clear color not getting properly updated if we have back-to-back clears
with different clear colors.  Technically, we could go out of our way to
set the clear color directly from iris in this case but this is a case
we're unlikely to see in the wild so let's not bother.  This matches
what we already do for color surfaces.

Cc: mesa-stable@lists.freedesktop.org
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4073>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4073>
(cherry picked from commit 9d07d598423e4015bbc7beb7a2fdc4c657d5e0cf)

isl: Set 3DSTATE_DEPTH_BUFFER::Depth correctly for 3D surfaces

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
(cherry picked from commit 9f5f4269a66eebfcaa3ae5cd7bdf91d88a7fc69c)

Revert "spirv: Use a simpler and more correct implementaiton of tanh()"

This reverts commit da1c49171d0df185545cfbbd600e287f7c6160fa.

The reduced formula has precision problems on fp16 around 0.  Bring
back the old formula, but make sure to keep the clamping.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4054>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4054>
(cherry picked from commit 9f9432d56c055b9704a76cad44da88d5e12f825c)

Revert "glsl: Use a simpler formula for tanh"

This reverts commit 9807f502eb7a023be619a14119388b2a43271b0e.

The simplified formula doesn't pass the tanh dEQP tests when we lower
to fp16 math.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4054>
(cherry picked from commit 986e92f0ea803caf014adc40e900bc774af71da3)

Revert "mesa: check for z=0 in _mesa_Vertex3dv()"

This reverts commit f04d7439a0ad6e13ff2912ff824553b6bcf511a4.

It no longer helps performance and the current vbo implementation is
faster anyway.

The app that hit this was a CAD program called Spazio3D. It made pretty
terrible use of the OpenGL API and we sent them some tips for improvements.
I'm assuming they've fixed this by now.

Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
(cherry picked from commit df3891e74a72d275aceba91adc94a9e7dc9aa029)

Revert "glx: convert glx_config_create_list to one big calloc"

This reverts commit 35fc7bdf0e6ad6547e39099e7060a3d89539b56d.

Unfortunately mentioned commit introduced a memory leak because
`driwindowsMapConfigs` and `createDriMode` functions allocate
small memory portions for each element:
 21,576 (232 direct, 21,344 indirect) bytes in 1 blocks are definitely lost in loss record 1,411 of 1,414
    at 0x483A7F3: malloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so)
    by 0x5D4AA09: createDriMode (dri_common.c:291)
    by 0x5D4ABF5: driConvertConfigs (dri_common.c:310)
    by 0x5D58414: dri3_create_screen (dri3_glx.c:945)
    by 0x5D39829: AllocAndFetchScreenConfigs (glxext.c:815)
    by 0x5D39C57: __glXInitialize (glxext.c:941)
    by 0x5D3290A: GetGLXPrivScreenConfig (glxcmds.c:174)
    by 0x5D34F38: glXQueryExtensionsString (glxcmds.c:1307)
    by 0x4F83038: glXQueryExtensionsString (in /usr/local/lib/libGL.so.1.7.0)
    by 0x4F2EA6B: ??? (in /usr/lib/x86_64-linux-gnu/libwaffle-1.so.0.6.0)
    by 0x4F2A0D7: waffle_display_connect (in /usr/lib/x86_64-linux-gnu/libwaffle-1.so.0.6.0)
    by 0x498F42A: wfl_checked_display_connect (piglit-util-waffle.h:74)

There is one more thing which disallow us to easily fix it are different element sizes
for instance: `glx_config_create_list` allocates memory just for `glx_config`,
`driwindowsMapConfigs` for `driwindows_config` and
`createDriMode` for `__GLXDRIconfigPrivate`.
Yes it is possible but size of such fix
will be more big and complex than original one.
So it make sense only if the malloc overhead
really is a big problem there.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3406>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3406>
(cherry picked from commit 311c82e1923f63070b198881d90c1098f4ff7a08)

intel/gen12+: Disable mid thread preemption.

Fixes a GPU hang in Car Chase.

Cc: mesa-stable@lists.freedesktop.org
v2: Add comment explaining why (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035>
(cherry picked from commit 5f13996262a6d72ca5b5c235647d5257ae961b66)

intel/device: bdw_gt1 actually has 6 eus per subslice

Found by inspection, I'm not aware of any bugs caused by this typo.

According to Lionel, it seems we only use this to generate masks
of available EUs for perfromance queries, and it's only used when we
can't query the fused parts of the GPU through DRM_IOCTL_I915_QUERY.
So this patch should help for the corner case where the Kernel is too
old to support the query ioctl.

v2: improve commit message, cc stable (Lionel).

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
(cherry picked from commit aa78801f0a6cfeaf3d16b4333239c0b862f73c10)

mesa/st: fix formats required for EXT_texture_norm16

Earlier commit did not take in to account that lists required for
rendering and texturing are parsed separately. This commit simply
removes formats added to the other list.

Fixes: de4eb9a3bb9 ("mesa/st: toggle EXT_texture_norm16 based on format support")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3961>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3961>
(cherry picked from commit fbd61b3fb66bcc3eb0f65da2c869046c24c35dc8)

intel/compiler: Restrict cs_threads to 64

Our current GPGPU_WALKER code only supports up to 64 threads.

On HSW we could use up to 70 and TGL up to 112, but only if the walker
is adjusted so the width does not exceed 64. Work to support this is
in progress.

Previous to this change, we might try to downgrade to SIMD8 if the
SIMD16 shader spilled. Since HSW and TGL have the max number of
threads above 64, we would then try to emit an invalid GPGPU walker
command.

Fixes: 932045061b5 ("i965/cs: Emit compute shader code and upload programs")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
(cherry picked from commit cf12faef614ab7cd9996410f1d161558a3853936)

ac/llvm: flush denorms for nir_op_fmed3 on GFX8 and older gens

The hardware doesn't flush denorms, exactly like fmin/fmax, so
we have to do it manually. This doesn't fix anything known.

Fixes: d6a07732c9c ("ac: use llvm.amdgcn.fmed3 intrinsic for nir_op_fmed3")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3962>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3962>
(cherry picked from commit 9e5d2a73c5fc12841b62758a035b2bdb191b3f86)

ac/llvm: fix 16-bit fmed3 on GFX8 and older gens

16-bit med3 is only supported on GFX9+.

Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.mid3.f16.*.

Fixes: d6a07732c9c ("ac: use llvm.amdgcn.fmed3 intrinsic for nir_op_fmed3")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3962>
(cherry picked from commit 30ac733680c3dfbfd1300c5498dd1b0c0a680905)

ac/llvm: fix 64-bit fmed3

Lower 64-bit fmed3 because LLVM doesn't expose an intrinsic.

Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.mid3.f64.*.

Fixes: d6a07732c9c ("ac: use llvm.amdgcn.fmed3 intrinsic for nir_op_fmed3")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3962>
(cherry picked from commit 50b8c2527464dbe18a01ab6412de4465cebf2225)

mesa: Flush vertices before changing the OpenGL state.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3958>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3958>
(cherry picked from commit 636656bcd7801c703ebcf9bd4c65197e4e6cbee8)

gallivm/tgsi: fix stream id regression

This broke TGSI GS shaders with llvmpipe, it wasn't looking at the
right immediates and it should be cast to an integer type.

Fixes: 163d5fde0669 (gallium/swr: Enable GL_ARB_gpu_shader5: multiple streams)

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Acked-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3949>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3949>
(cherry picked from commit 954cf8e86b6e0d52c04098604d2daa4305bf6f70)

mesa/st: toggle EXT_texture_norm16 based on format support

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2556
Fixes: 7f467d4f738 ("mesa: GL_EXT_texture_norm16 extension plumbing")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
(cherry picked from commit de4eb9a3bb9fb073a5bf5cc157918bfa0f62b394)

egl: Fix A2RGB10 platform_{device,surfaceless} PBuffer configs.

The __DRI_IMAGE_FORMAT_* part wants to be handled for the *101010
type formats as well. Factor out a common function for that task.
That again makes the piglit egl_ext_device_base test work again
for hardware drivers.

v2: Factor out a common function for that task.
v3: dri2_pbuffer_visuals -> dri2_pbuffer_visuals

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Fixes: 9acb94b6236 "egl: Enable 10bpc EGLConfigs for platform_{device,surfaceless}"
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3790>
(cherry picked from commit d32c458de76c9e0cc08c9ee1a7de23c3fca69298)

i965: toggle on EXT_texture_norm16

Fixes: 7f467d4f738 ("mesa: GL_EXT_texture_norm16 extension plumbing")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
(cherry picked from commit 200a83a98394ce292fd1cdbd6e9166502379b5c9)

mesa: introduce boolean toggle for EXT_texture_norm16

Fixes: 7f467d4f738 ("mesa: GL_EXT_texture_norm16 extension plumbing")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
(cherry picked from commit dc531869a918dc75ffc09b38851b750ba62673f8)

.pick_status.json: Update to 74e4cda64b9d114321216eefe536f80644b0f0fd

.pick_status.json: Mark 9fea90ad5170dd64376d22a14ac88c392813c96c as denominated

.pick_status.json: Mark b9773631d3e79e2310ed0eb274b4dd9426205066 as denominated

.pick_status.json: Mark ddd767387f336ed1578f171a2af4ca33c564d7f3 as denominated

.pick_status.json: Mark 34fd894e42ae1ec9d35bf9c4f05364b03dd4a223 as denominated

.pick_status.json: Mark 5ea23ba659adc05ff75ca7a4c9d1bd01db889ddd as denominated

.pick_status.json: Mark dba71de5c63617677fe44558f995d35fad643413 as denominated

.pick_status.json: Update to 74e4cda64b9d114321216eefe536f80644b0f0fd

v3d: Sync on last CS when non-compute stage uses resource written by CS

When a resource is written by a compute shader and then used by a
non-compute stage we sync on last compute job to guarantee that the
resource has been completely written when the next stage reads resources.

In the other cases how flushes are done guarantee the serialization of
the writes and reads.

To reproduce the failure the following tests should be executed in batch
as last test don't fail when run isolated:

KHR-GLES31.core.shader_image_load_store.basic-allFormats-load-fs
KHR-GLES31.core.shader_image_load_store.basic-allFormats-loadStoreComputeStage
KHR-GLES31.core.shader_image_load_store.basic-allTargets-load-cs
KHR-GLES31.core.shader_image_load_store.advanced-sync-vertexArray

v2: Use fence dep instead of bo_wait (Eric Anholt)
v3: Rename struct names (Iago Toral)
    Document why is not needed on graphics->compute case. (Iago Toral)
    Follow same code pattern of the other update of in_sync_bcl.
v4: Fixed comments style. (Iago Toral)

Fixes KHR-GLES31.core.shader_image_load_store.advanced-sync-vertexArray

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
CC: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2700>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2700>
(cherry picked from commit 01496e3d1ea0370af03e6645dbd2b864c2ace94c)

.pick_status.json: Update to 01496e3d1ea0370af03e6645dbd2b864c2ace94c

Merge remote-tracking branch 'mesa/19.3' into q-x86

spirv: Remove outdated SPIR-V decoration warnings

spirv_to_nir warns if it encounters XFB decorations and errors if
it encounters a Stream decoration with value other than 0, despite
the fact that these decorations are in fact handled correctly.

Fixes dEQP-VK.transform_feedback.simple.query_1_*
Fixes: cd4a14be06 "spirv: Handle XFB variable decorations"

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3910>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3910>
(cherry picked from commit 5f3cbbd958d14924dded0e0a0908127f6bfa006d)

util: promote u_debug_memory.c to src/util

When os_memory_debug.h was promoted to src/util, this source-file on
which it depends on when the debug-flag is set on windows was left
out. So let's move this also.

It doesn't seem there's any way of triggering this issue right now, but
it seems better to correct this to avoid this from biting us in the ass
in the future.

Fixes: 88c4680b5a5 ("util: promote u_memory to src/util")
Reviewed-by: Dylan Baker <dylan@pnwbakers>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3844>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3844>
(cherry picked from commit 2e3318b151abddd456077ec0eed13f95245ce344)

.pick_status.json: Update to e4baff90812d799d586296fcad992ddcc553c359

i965: Do not generate D16 B5G6R5_UNORM configs on gen < 8

We don't support MESA_FORMAT_Z_UNORM16 before Gen8, see
intel_screen_init_surface_formats.

As a consequence disables B5G6R5_UNORM configs with depth
on gen < 6.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2275
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3206>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3206>
(cherry picked from commit 5bfd363be4c957c1f7b5c1f3069346f2bce2cd5a)

intel/fs: Correctly handle multiply of fsign with a source modifier

The other source of the multiply will be interpreted as a uint32_t in an
XOR instruction.  Any source modifiers with either not be interpreted at
all or will be misinterpreted due to the differing types.

If the other operand of the multiplication has a source modifier, just
emit an extra move to resolve the source modifiers.

The negation source modifier problem is difficult to reproduce due to an
algebraic optimization that changes (-a*b) to -(a*b).  However, changes
in MR !1359 push the negations back down.

On Gen7+ it might be possible to do slightly better for an abs() source
modifier by using BFI2 as a glorified copysign().

On Gen8+ it might be possible to do slightly better for a neg() source
modifier by emitting (~a ^ b).

There were no shader-db changes on any Intel platform, so I think we can
deal with that problem when it arises.

See also piglit!224.

Fixes: 06d2c116415 ("intel/fs: Add a scale factor to emit_fsign")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3780>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3780>
(cherry picked from commit 273b8cd1ca286e2f43b4a464a391fdcaac49f077)

st/vdpau: Only call is_video_format_supported hook if needed

Namely only if *is_supported is true, otherwise the hook result can't
affect it.

Avoids

../src/gallium/state_trackers/vdpau/vdpau_private.h:138: FormatYCBCRToPipe: Assertion `0' failed.

with assertions enabled.

Fixes: 5d5b414a7b84 "st/vdpau: fix chroma_format handling in
                     VideoSurfaceQueryGetPutBitsYCbCrCapabilities"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3848>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3848>
(cherry picked from commit 7e6010106fb3c4eb5436de869183e857243c1006)

mesa: fix immediate mode with tessellation and varying patch vertices

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3861>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3861>
(cherry picked from commit 2e05a280b6b6d334388e3824bd82472ccbf33252)

intel/gen12: Take into account opcode when decoding SWSB

The interpretation of the fields is different depending whether the
instruction is a SEND/MATH or not.

This fixes the disassembly output for non-SEND/MATH instructions that
have both in-order and out-of-order dependencies.  Their dependencies
were wrongly represented as `@A $B` when the correct would be `@A
$B.dst`.

Fixes: 6154cdf924f ("intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.")
Fixes: 83612c01271 ("intel/disasm/gen12: Disassemble software scoreboard information.")
Acked-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
(cherry picked from commit 79788b8f7f07460af8467931501380e47b485e36)

.pick_status.json: Update to 8291d728dc997e87b4d2e4e451692643a1dba881

zink: confused compilation macro usage for zink in target helpers.

Fixes: 8d46e35d16e ("zink: introduce opengl over vulkan")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3831>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3831>
(cherry picked from commit 692093fbdc93343dbe500128fdd23167d73036d9)

egl: Implement getImage/putImage on pbuffer swrast.

This change adds getImage/putImage callbacks to the swrast pbuffer
loader extension.
This fixes a recent crash with Weston as well as a crashing
test with classic swrast without an official gitlab issue.

v2: Determine bytes per pixel differently and fix non X11 builds.
v3: Plug memory leak and fix crash on out of bounds access.
    (Daniel Stone)
v4: Follow the code structure of the wayland get/put image
    implementation - hopefully being more obvious.
    Handle 64 bits formats.
    Use BufferSize directly.
    (Emil Velikov)
v5: Change pixel size computation.
    (Eric Engestrom)

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2219
Fixes: d6edccee8da "egl: add EGL_platform_device support"
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3711>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3711>
(cherry picked from commit c7617d8908a970124321ce731b43d5996c3c5775)

intel/fs/gen12: Fixup/simplify SWSB annotations of SIMD32 scratch writes.

Found by inspection.  Existing code was trying to avoid assuming that
an SBID had been assigned to the virtual instruction, but
synchronizing the header setup with respect to the previous SIMD16
SEND by using SYNC.ALLRD doesn't really seem possible unless the SEND
instruction had been assigned an SBID.  Assert-fail instead if no SBID
has been allocated.

Fixes: 15e3a0d9d264becc "intel/eu/gen12: Set SWSB annotations in hand-crafted assembly."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 4e4e8d793f050eac84f2a850ab2e5c24c4c459ac)

radeonsi: don't wait for shader compilation to finish when destroying a context

This was a hack for glsl_types deinitialization and it predates the proper
fix, which was the addition of glsl_type_singleton_decref.

This fixes a crash when the context is destroyed via the atexit handler.

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3800>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3800>
(cherry picked from commit 7e2b4bf256610cc016202893d7b4b4ef60b25b53)

.pick_status.json: Update to bee5c9b0dc13dbae0ccf124124eaccebf7f2a435

gallium/swr: simplify environmental variabled expansion code

There were 2 versions of code doing the same thing.
Since std::regexp are locale-sensitive better is to leave old
good way to do this.

Fixes: https://gitlab.freedesktop.org/mesa/mesa/issues/2520
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3761>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3761>
(cherry picked from commit 689817c9dfde9a0852f2b2489cb0fa93ffbcb215)

glsl: fix gl_nir_set_uniform_initializers() for image arrays

The if was incorrectly checking for an image type on what could
be an array of images. Here we change it to use the type stored
in uniform storage which has already been stripped of arrays,
this is what the above code for samplers does also.

Fixes: 2bf91733fcb5 ("nir/linker: Set the uniform initial values")

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757>
(cherry picked from commit 676869e1d4bb1660430fcdb99443238a7de50eb8)

.pick_status.json: Update to 946eacbafb47c8b94d47e7c9d2a8b02fff5a22fa

iris: fix aux buf map failure in 32bits app on Android

Cc: mesa-stable@lists.freedesktop.org
Reported-by: Zhifang Long <zhifang.long@intel.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3784>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3784>
(cherry picked from commit fdd20be324eabab7da1ba67cf7e379398d771186)

radeonsi: make si_fence_server_signal flush pipe without work

glSignalSemaphoreEXT sometime doesn't signal the semaphore, it is
because radeonsi doesn't flush if gl context doesn't have pending
work. Fix the porblem by always submit ib.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3779>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3779>
(cherry picked from commit 0660cbf4262891e6380faf0d99217b2d27873051)

.pick_status.json: Update to 2a98cf3b2ecea43cea148df7f77d2abadfd1c9db

docs: Add SHA256 sum for 19.3.4

VERSION: bump version for 19.3.4

docs: Add release notes for 19.3.4

nir: do not use De Morgan's Law rules for flt and fge

In presence of NaNs, "!(flt(a, b) && flt(c, d))" is NOT EQUAL
to "fge(a, b) || fge(c, d)". These optimizations are unsafe for
apps that rely on NaN behaviour.

pipeline-db (GFX9/LLVM):
Totals from affected shaders:
SGPRS: 3176 -> 3136 (-1.26 %)
VGPRS: 2188 -> 2144 (-2.01 %)
Spilled SGPRs: 227 -> 169 (-25.55 %)
Code Size: 150572 -> 151800 (0.82 %) bytes
Max Waves: 307 -> 310 (0.98 %)

pipeline-db (GFX9/ACO):
Totals from affected shaders:
SGPRS: 18744 -> 18744 (0.00 %)
VGPRS: 15576 -> 15580 (0.03 %)
Spilled SGPRs: 164 -> 164 (0.00 %)
Code Size: 1573012 -> 1576492 (0.22 %) bytes
Max Waves: 1534 -> 1532 (-0.13 %)

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2127
Fixes: d1ed4ffe0b7 ("nir: Use De Morgan's Law on logic compounded comparisons")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3696>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3696>
(cherry picked from commit 8e7728077435c5c5ad8c328761277f8ff3b32112)

Revert "gallium: Fix big-endian addressing of non-bitmask array formats."

This reverts the functional part of commit
d17ff2f7f1864c81c1e00d04baf20f953c6d276a, leaving the unit test for
mesa/pipe agreement on what's an array.

The issue is that the util_channel_desc.shift values on array formats are
not used for bit addressing in memory, they're bit addressing within a
word treating a pixel of the format as a native type, as seen by
llvmpipe's use of the values to do shifts (see
lp_build_unpack_arith_rgba_aos() for example).  This means the values are
nonsensical for 3-byte RGB, but then llvmpipe doesn't expose those formats
so it works out.

I still want to clean up our big-endian format handling at some point, but
let's fix the s390x regression first, sort out our format unit tests in
CI, then be able to refactor with confidence.

Fixes: d17ff2f7f186 ("gallium: Fix big-endian addressing of non-bitmask array formats.")
Closes: #2472
Acked-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3721>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3721>
(cherry picked from commit 1886dbfe7362baa221009371434f158b97183164)

radeonsi: fix the DCC MSAA bug workaround

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3646>
(cherry picked from commit fbb27eebc8cab1a5d70ea67a37de8d18f20a88f0)

svga: fix size of format_conversion_table[]

Since we are now using sparse matrix for format_conversion_table,
we have to make sure we have last entry in table which gives the
sense of required size of format_conversion_table

Fixes: 84db6ba7 ("svga: Drop unsupported formats from the format table")

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit 470e73e7f86b4530cf789a779f43674ecec91881)

.pick_status.json: Update to 23037627359e739c42b194dec54875aefbb9d00b

Vulkan overlay: use the corresponding image index for each swapchain

pImageIndices should be a pointer to the current image index
otherwise every swapchain but the first one could have a wrong image index

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3741>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3741>
(cherry picked from commit 7283c33b981f975361e3bfa62a339c88f2642cbb)

freedreno/ir3: put the conversion back for half const to the right place.

The previous commit leads to match immed values unexpectedly.

This makes constlen for each shader including bvert wrong.
Also fixes atan2 for mediump deqp tests.

Fixes: cbd1f47433b ("freedreno/ir3: convert back to 32-bit values for half constant registers.")

v2: Move conversion up above fabs/fneg modifier handling as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
(cherry picked from commit 260bd32b58a55ac0d9870497caef3a4602e19d47)

.pick_status.json: Update to 689817c9dfde9a0852f2b2489cb0fa93ffbcb215

Vulkan Overlay: Don't try to change the image layout to present twice

The render pass already does the transition.
The pipeline barrier is still needed to transfer the queue family ownership.

Fixes: 320b0f66c274 ("vulkan/overlay: bounce image back to present layout")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3740>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3740>
(cherry picked from commit f239bb8020df4176ca539bafff327ab5c8da2c2e)

Correctly wait in the fragment stage until all semaphores are signaled

This fixes two issues:
- a crash if the application uses more than one semaphore for presenting because the driver expects one stage per semaphore
- the swapchain image could be not ready yet if the semaphores aren't signaled, #946 is possible related

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3718>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3718>
(cherry picked from commit 1c79afd94620925cb9e0903f24f91c3ab9ecfcb4)

svga: Fix banded DMA upload

A previous commit ("winsys/svga: Limit the maximum DMA hardware buffer
size") made banded DMA transfer kick in when transfering gnome-shell
window contents under gnome-shell / wayland. This uncovered a bug where
we assumed that banded DMA transfers always occur to the top (y=0) of the
surface.
Fix this by taking the destination y offset into account.

Cc: 19.2 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Fixes: 287c94ea498 ("Squashed commit of the following:")
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3733>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3733>
(cherry picked from commit 451cf228d53ba8f51beb3dcf04370e126fb7ccb6)

intel: Load the driver even if I915_PARAM_REVISION is not found.

This param is only available starting on kernel 4.1. Use a default
value of 0 if it is not found instead.

v2: Update commit message (Lionel)

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Mark Janes <mark.a.janes@intel.com>
Fixes: 96e1c945f2b ("i965: Move device info initialization to common
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3727>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3727>
(cherry picked from commit 4aa7af9e9a4c19e10afaf4a3c756e62cf4d352c3)

swr: Fix GCC 4.9 checks.

Fixes: f0a22956be48 ("swr/rast: _mm*_undefined_* implementations for gcc<4.9")
Fixes: e21fc2c62527 ("swr/rast: non-regex knob fallback code for gcc < 4.9")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
(cherry picked from commit deb2bbf57ec1d0660dd85b7080bf5ebeb10e8768)

.pick_status.json: Update to d8bae10bfe0f487dcaec721743cd51441bcc12f5

radeonsi: stop using the VM_ALWAYS_VALID flag

Allocation all the bo as ALWAYS_VALID means they must all fit in memory
(vram + gtt) at each command submission.
This causes some trouble when the total allocated memory is greater than
the available memory.

Possible solutions:
- being able to tag/untag a bo as ALWAYS_VALID: would require kernel changes
- disable VM_ALWAYS_VALID when memory usage is more than a percentage of the
  available memory
- disable VM_ALWAYS_VALID entirely

v1 of this patch implemented option 2. v2 (this version) implements option 3.

Related issues:
 - https://gitlab.freedesktop.org/drm/amd/issues/607
 - https://gitlab.freedesktop.org/mesa/mesa/issues/1257

It also helps with some piglit tests (-t maxsize -t "max[_-].*size" -t maxuniformblocksize):
instead of crashing the machine, the tests fail cleanly.

(cherry-pick from ab54624d0d52d88da7fb7f4df61f33f600a1dfd7)

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3709>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3709>

mesa: allow bit queries for EXT_disjoint_timer_query

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2090
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3707>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3707>

mapi: add GetInteger64vEXT with EXT_disjoint_timer_query

From EXT_disjoint_timer_query spec:

   "Interaction: This extension adds GetInteger64vEXT if
    OpenGL ES 3.0 is not supported"

See https://github.com/KhronosGroup/OpenGL-Registry/issues/326.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2090
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3707>

intel/fs: Don't count integer instructions as being possibly coissue

Integer instructions don't coissue.  Before e64be391dd0
("intel/compiler: generalize the combine constants pass"), this pass
only looked at float sources.  There's no shader-db data in that commit,
so I collected some.  The results are not good:

    Haswell
    total instructions in shared programs: 11898805 -> 11908127 (0.08%)
    instructions in affected programs: 1218680 -> 1228002 (0.76%)
    helped: 2
    HURT: 5171
    helped stats (abs) min: 12 max: 111 x̄: 61.50 x̃: 61
    helped stats (rel) min: 1.59% max: 9.20% x̄: 5.40% x̃: 5.40%
    HURT stats (abs)   min: 1 max: 311 x̄: 1.83 x̃: 1
    HURT stats (rel)   min: 0.02% max: 9.91% x̄: 1.05% x̃: 0.70%
    95% mean confidence interval for instructions value: 1.55 2.05
    95% mean confidence interval for instructions %-change: 1.02% 1.08%
    Instructions are HURT.

    total cycles in shared programs: 221664974 -> 221404750 (-0.12%)
    cycles in affected programs: 120012620 -> 119752396 (-0.22%)
    helped: 3464
    HURT: 3159
    helped stats (abs) min: 1 max: 428160 x̄: 314.55 x̃: 16
    helped stats (rel) min: <.01% max: 57.33% x̄: 3.40% x̃: 1.28%
    HURT stats (abs)   min: 1 max: 87846 x̄: 262.54 x̃: 14
    HURT stats (rel)   min: <.01% max: 85.57% x̄: 3.01% x̃: 0.77%
    95% mean confidence interval for cycles value: -224.23 145.65
    95% mean confidence interval for cycles %-change: -0.50% -0.19%
    Inconclusive result (value mean confidence interval includes 0).

    total spills in shared programs: 9804 -> 10047 (2.48%)
    spills in affected programs: 6869 -> 7112 (3.54%)
    helped: 2
    HURT: 41

    total fills in shared programs: 19863 -> 20319 (2.30%)
    fills in affected programs: 17428 -> 17884 (2.62%)
    helped: 2
    HURT: 41

    LOST:   20
    GAINED: 13

This also prevents regressions in "intel/fs: Promote integer constants
after lowering integer multiplication" (note: that patch will probably
not be committed).  When the passes are reorderd, code like

    mul(8)      acc0<1>D    g9<8,8,1>D  -2078209981D    { align1 1Q };

gets turned into

    mov(1)      g23<1>D     2078209981D                 { align1 WE_all 1N };
    ...
    mul(8)      acc0<1>D    g13<8,8,1>D  -g23<0,1,0>D   { align1 1Q compacted };

It's not 100% clear why, but these produce different results.  Note that
-2078209981 & 0x0ffff = 0x0843, and -(2078209981 & 0x0ffff) =
0xffff0843.  It seems like the upper 16-bits of the negation should be
ignored.

Fixes: e64be391dd0 ("intel/compiler: generalize the combine constants pass")
Cc: Iago Toral Quiroga <itoral@igalia.com>
Suggested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
The shaders with spills or fills hurt are the usual suspects.  A couple
compute shaders in Dirt Showdown and a compute shader in Bioshock
Infinite.  On Haswell, a compute shader (that appears twice in
shader-db) from Aztec Ruins was also hurt for spill and fills.

Haswell
total instructions in shared programs: 11573934 -> 11568335 (-0.05%)
instructions in affected programs: 828623 -> 823024 (-0.68%)
helped: 2825
HURT: 6
helped stats (abs) min: 1 max: 134 x̄: 2.16 x̃: 1
helped stats (rel) min: 0.02% max: 9.05% x̄: 0.84% x̃: 0.61%
HURT stats (abs)   min: 1 max: 216 x̄: 81.83 x̃: 56
HURT stats (rel)   min: 0.16% max: 8.65% x̄: 4.21% x̃: 4.68%
95% mean confidence interval for instructions value: -2.31 -1.64
95% mean confidence interval for instructions %-change: -0.85% -0.80%
Instructions are helped.

total cycles in shared programs: 187573593 -> 187004633 (-0.30%)
cycles in affected programs: 82816107 -> 82247147 (-0.69%)
helped: 2186
HURT: 1741
helped stats (abs) min: 1 max: 35230 x̄: 326.96 x̃: 16
helped stats (rel) min: <.01% max: 46.11% x̄: 3.11% x̃: 0.90%
HURT stats (abs)   min: 1 max: 6138 x̄: 83.73 x̃: 16
HURT stats (rel)   min: <.01% max: 104.11% x̄: 2.73% x̃: 0.75%
95% mean confidence interval for cycles value: -197.13 -92.64
95% mean confidence interval for cycles %-change: -0.72% -0.33%
Cycles are helped.

total spills in shared programs: 7870 -> 7743 (-1.61%)
spills in affected programs: 2260 -> 2133 (-5.62%)
helped: 31
HURT: 5

total fills in shared programs: 6320 -> 6263 (-0.90%)
fills in affected programs: 3547 -> 3490 (-1.61%)
helped: 31
HURT: 6

LOST:   9
GAINED: 9

Ivybridge
total instructions in shared programs: 11863372 -> 11859793 (-0.03%)
instructions in affected programs: 757183 -> 753604 (-0.47%)
helped: 2236
HURT: 3
helped stats (abs) min: 1 max: 81 x̄: 1.86 x̃: 1
helped stats (rel) min: 0.03% max: 5.26% x̄: 0.74% x̃: 0.48%
HURT stats (abs)   min: 11 max: 301 x̄: 192.33 x̃: 265
HURT stats (rel)   min: 1.55% max: 10.51% x̄: 6.89% x̃: 8.62%
95% mean confidence interval for instructions value: -2.01 -1.18
95% mean confidence interval for instructions %-change: -0.77% -0.70%
Instructions are helped.

total cycles in shared programs: 178377378 -> 177946087 (-0.24%)
cycles in affected programs: 76261390 -> 75830099 (-0.57%)
helped: 1635
HURT: 1395
helped stats (abs) min: 1 max: 34796 x̄: 333.53 x̃: 16
helped stats (rel) min: <.01% max: 47.15% x̄: 2.82% x̃: 0.64%
HURT stats (abs)   min: 1 max: 4315 x̄: 81.74 x̃: 18
HURT stats (rel)   min: <.01% max: 49.98% x̄: 1.99% x̃: 0.53%
95% mean confidence interval for cycles value: -197.06 -87.62
95% mean confidence interval for cycles %-change: -0.78% -0.43%
Cycles are helped.

total spills in shared programs: 4188 -> 4182 (-0.14%)
spills in affected programs: 1557 -> 1551 (-0.39%)
helped: 30
HURT: 3

total fills in shared programs: 5056 -> 5245 (3.74%)
fills in affected programs: 2708 -> 2897 (6.98%)
helped: 30
HURT: 3

LOST:   5
GAINED: 1

No shader-db changes on any other Intel platform.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544>
(cherry picked from commit 59488cbbaca1268841fe5ba42d0a1202b33be23b)

radv: Do not set SX DISABLE bits for RB+ with unused surfaces.

The extra bits in CB_SHADER_MASK break dual source blending in
SkQP on a Stoney device. However:

- As far as I can tell, some other dual source blend tests are passing
  before and after the change.
- A hacked around skqp passes on my Vega desktop and Raven laptop
- Getting Skqp to give any useful info or to run it outside of Android
  on ChromeOS is proving difficult.

I have confirmed 3 strategies that seem to work:
- The old radv behavior of setting CB_SHADER_MASK to 0xF
- AMDVLK: CB_SHADER_MASK = 0xFF, and the 3 RB+ regs
  are 0.
- radeonsi: CB_SHADER_MASK = 0xFF, but does not set DISABLE
  bits in SX_BLEND_OPT_CONTROL for CB 1-7.

Let us use the radeonsi solution as that solution also seems like the correct
thing to do for holes. I have tested on my Raven laptop that setting the high
surfaces to not disabled and downconvert to 32_R does not imply a performance
penalty.

Fixes: e9316fdfd48 "radv: fix setting CB_SHADER_MASK for dual source blending"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670>
(cherry picked from commit 65a6dc5139fddd5e01eaedcc57fc67e0a6a28c94)

st/mesa: Handle the rest renderbuffer formats from OSMesa

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2189
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/989
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2036
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>
(cherry picked from commit d83abf1d378be059b4f41a6a44a9bf24c7394084)

i965: Do not set front_buffer_dirty if there is no front buffer

Otherwise there will be a warning:
 "libEGL warning: FIXME: egl/x11 doesn't support front buffer rendering."

Happens with EGL_KHR_surfaceless_context:

 eglMakeCurrent(egl_display, EGL_NO_SURFACE, EGL_NO_SURFACE, egl_context)
 eglMakeCurrent(egl_display, egl_surface, egl_surface, egl_context)
 glFlush() // Here will be a warning

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1525
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3628>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3628>
(cherry picked from commit 36126b6211f1ac2da0aa94411608b2320553dbb6)

.pick_status.json: Mark ca6a22305b275b49fbc88b8f4cba2fefb24c2a5d as backported

.pick_status.json: Update to 7eaf21cb6f67adbe0e79b80b4feb8c816a98a720

winsys/amdgpu: Close KMS handles for other DRM file descriptions

When a BO or amdgpu_screen_winsys is destroyed.

Should fix leaking such BOs in other DRM file descriptions.

v2:
* Pass the correct file descriptor to drmIoctl (Pierre-Eric
  Pelloux-Prayer)
* Use _mesa_hash_table_remove
v3:
* Close handles in amdgpu_winsys_unref as well
v4:
* Adapt to amdgpu_winsys::sws_list_lock.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2270
Fixes: 11a3679e3aba "winsys/amdgpu: Make KMS handles valid for original
                     DRM file descriptor"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(Cherry picked from commit ca6a22305b275b49fbc88b8f4cba2fefb24c2a5d)

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>

winsys/amdgpu: Re-use amdgpu_screen_winsys when possible

Namely, if os_same_file_description determined that the DRM file
descriptor references the same file description.

v2:
* Adapt to amdgpu_winsys::sws_list_lock.
v3:
* Fix comparison of amdgpu_screen_winsys file descriptions, see
  https://gitlab.freedesktop.org/mesa/mesa/issues/2413 .
* Lock amdgpu_winsys::sws_list_lock for traversing the sws_list in
  amdgpu_winsys_create.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(Cherry picked from commit 9f2bed49d476a15af0df270307f9051d810ea0ab)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>

util: Add os_same_file_description helper

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
(Cherry picked from commit f76cbc7901f7d500f5a4f74aedfd29970d1efd00)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>

winsys/amdgpu: Only re-export KMS handles for different DRM FDs

When the amdgpu_screen_winsys uses the same FD as the amdgpu_winsys
(which is always the case for the first amdgpu_screen_winsys), we can
just use bo->u.real.kms_handle.

v2:
* Also only create the kms_handles hash table if the
  amdgpu_screen_winsys fd is different from the amdgpu_winsys one.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
(Cherry picked from commit c6468f66c7a47f0e16df2f1200db33eef6d2d1f4)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>

winsys/amdgpu: Keep track of retrieved KMS handles using hash tables

The assumption being that KMS handles are only retrieved for relatively
few BOs, so hash tables should be efficient both in terms of performance
and memory consumption.

We use the address of struct amdgpu_winsys_bo as the key and its
kms_handle field (the KMS handle valid for the DRM file descriptor
passed to amdgpu_device_initialize) as the hash value.

v2:
* Add comment above amdgpu_screen_winsys::kms_handles (Pierre-Eric
  Pelloux-Prayer)
v3:
* Protect kms_handles hash table with amdgpu_winsys::sws_list_lock
  mutex.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
(Cherry picked from commit 24075ac60fcc09dad173cb792e8f186c6379c086)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>

winsys/amdgpu: Keep a list of amdgpu_screen_winsyses in amdgpu_winsys

v2:
* Add dedicated mutex for the list.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
(Cherry picked from commit f4010a6da9720b1593ca34faf0d8722ca85ed6c2)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>

etnaviv: Destroy rsc->pending_ctx set in etna_resource_destroy()

Destroy rsc->pending_ctx set in etna_resource_destroy(), otherwise
the memory is allocated, never free'd, and becomes unreachable. This
fixes a memory leak.

Fixes: 9e672e4d20fb ("etnaviv: keep references to pending resources")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3633>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3633>
(cherry picked from commit c32bd325e7688c781b7e5de58a2d0534c82f00a0)

clover: Use explicit conversion from llvm::StringRef to std::string

Fixes build after llvm 777180a32b61070a10dd330b4f038bf24e916af1
("[ADT] Make StringRef's std::string conversion operator explicit")

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit 0ccda2ebff83816cecf4dcb48f367a0d5c8f5fb1)

.pick_status.json: Update to 9afdcd64f2c96f3fcc1a28912987f2e8066aa995

panfrost: Fix the damage box clamping logic

When the rendering are is not covering the whole FBO, and the biggest
damage rect is empty, we can have damage.max{x,y} > damage.min{x,y},
which leads to invalid reload boxes.

Fixes: 65ae86b85422 ("panfrost: Add support for KHR_partial_update()")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
(cherry picked from commit b550b7ef3b8d12f533b67b1a03159a127a3ff34a)

anv/blorp: Use the correct size for vkCmdCopyBufferToImage

Now that we're using an uncompressed format for the buffer, we have to
scale down the dimensions we pass into BLORP when doing buffer->image
copies.

Fixes: dd92179a72 "anv: Canonicalize buffer formats for image/buffer..."
Closes: #2452
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3664>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3664>
(cherry picked from commit d7fe9af6202413aa4e6f0f53d89577ed8ea80027)

intel/fs: Write the address register with NoMask for MOV_INDIRECT

This fixes a hang in the following Vulkan CTS test on TGL-LP:

    dEQP-VK.descriptor_indexing.storage_buffer_dynamic_in_loop

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
(cherry picked from commit f93dfb509cbf9474befae9919dd8c135bbd67093)

genxml: Add a new 3DSTATE_SF field on gen12

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
(cherry picked from commit 9da9abf8a7a605cc9b79bd4240ff715b79ac774a)

anv,iris: Set 3DSTATE_SF::DerefBlockSize to per-poly on Gen12+

According to the BSpec, this should prevent hangs when using shaders
with large URB entries.  A more precise fix can be done but it requires
re-arranging URB setup.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
(cherry picked from commit e1bdb127b6875df602bd736465d597725f326621)

.pick_status.json: Update to b550b7ef3b8d12f533b67b1a03159a127a3ff34a

bin/pick-ui: Add a new maintainer script for picking patches

In the long term the goal of this script is to nearly completely
automate the process of picking stable nominations, in a well tested
way.

In the short term the goal is to provide a better, faster UI to interact
with stable nominations.