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1 /*

4 *

5 * Permission is hereby granted, free of charge, to any person obtaining a

6 * copy of this software and associated documentation files (the

7 * "Software"), to deal in the Software without restriction, including

8 * without limitation the rights to use, copy, modify, merge, publish,

9 * distribute, sub license, and/or sell copies of the Software, and to

10 * permit persons to whom the Software is furnished to do so, subject to

11 * the following conditions:

12 *

13 * The above copyright notice and this permission notice (including the

14 * next paragraph) shall be included in all copies or substantial portions

15 * of the Software.

16 *

17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

24 *

25 */

27 #ifndef _I915_DRM_H_

28 #define _I915_DRM_H_

30 /* Please note that modifications to all structs defined here are

31 * subject to backwards-compatibility constraints.

32 */

34 #include "drm.h"

36 /* Each region is a minimum of 16k, and there are at most 255 of them.

37 */

38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use

39 * of chars for next/prev indices */

40 #define I915_LOG_MIN_TEX_REGION_SIZE 14

42 typedef struct _drm_i915_init {

43 enum {

44 I915_INIT_DMA = 0x01,

45 I915_CLEANUP_DMA = 0x02,

46 I915_RESUME_DMA = 0x03,

48 /* Since this struct isn't versioned, just used a new

49 * 'func' code to indicate the presence of dri2 sarea

50 * info. */

51 I915_INIT_DMA2 = 0x04

52 } func;

53 unsigned int mmio_offset;

54 int sarea_priv_offset;

55 unsigned int ring_start;

56 unsigned int ring_end;

57 unsigned int ring_size;

58 unsigned int front_offset;

59 unsigned int back_offset;

60 unsigned int depth_offset;

61 unsigned int w;

62 unsigned int h;

63 unsigned int pitch;

64 unsigned int pitch_bits;

65 unsigned int back_pitch;

66 unsigned int depth_pitch;

67 unsigned int cpp;

68 unsigned int chipset;

69 unsigned int sarea_handle;

70 } drm_i915_init_t;

72 typedef struct drm_i915_sarea {

73 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];

74 int last_upload; /* last time texture was uploaded */

75 int last_enqueue; /* last time a buffer was enqueued */

76 int last_dispatch; /* age of the most recently dispatched buffer */

77 int ctxOwner; /* last context to upload state */

78 int texAge;

79 int pf_enabled; /* is pageflipping allowed? */

80 int pf_active;

81 int pf_current_page; /* which buffer is being displayed? */

82 int perf_boxes; /* performance boxes to be displayed */

83 int width, height; /* screen size in pixels */

85 drm_handle_t front_handle;

86 int front_offset;

87 int front_size;

89 drm_handle_t back_handle;

90 int back_offset;

91 int back_size;

93 drm_handle_t depth_handle;

94 int depth_offset;

95 int depth_size;

97 drm_handle_t tex_handle;

98 int tex_offset;

99 int tex_size;

100 int log_tex_granularity;

101 int pitch;

102 int rotation; /* 0, 90, 180 or 270 */

103 int rotated_offset;

104 int rotated_size;

105 int rotated_pitch;

106 int virtualX, virtualY;

107

108 unsigned int front_tiled;

109 unsigned int back_tiled;

110 unsigned int depth_tiled;

111 unsigned int rotated_tiled;

112 unsigned int rotated2_tiled;

113

114 int planeA_x;

115 int planeA_y;

116 int planeA_w;

117 int planeA_h;

118 int planeB_x;

119 int planeB_y;

120 int planeB_w;

121 int planeB_h;

122

123 /* Triple buffering */

124 drm_handle_t third_handle;

125 int third_offset;

126 int third_size;

127 unsigned int third_tiled;

128

129 /* buffer object handles for the static buffers. May change

130 * over the lifetime of the client, though it doesn't in our current

131 * implementation.

132 */

133 unsigned int front_bo_handle;

134 unsigned int back_bo_handle;

135 unsigned int third_bo_handle;

136 unsigned int depth_bo_handle;

137 } drm_i915_sarea_t;

138

139 /* Driver specific fence types and classes.

140 */

141

142 /* The only fence class we support */

143 #define DRM_I915_FENCE_CLASS_ACCEL 0

144 /* Fence type that guarantees read-write flush */

145 #define DRM_I915_FENCE_TYPE_RW 2

146 /* MI_FLUSH programmed just before the fence */

147 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000

148

149 /* Flags for perf_boxes

150 */

151 #define I915_BOX_RING_EMPTY 0x1

152 #define I915_BOX_FLIP 0x2

153 #define I915_BOX_WAIT 0x4

154 #define I915_BOX_TEXTURE_LOAD 0x8

155 #define I915_BOX_LOST_CONTEXT 0x10

156

157 /* I915 specific ioctls

158 * The device specific ioctl range is 0x40 to 0x79.

159 */

160 #define DRM_I915_INIT 0x00

161 #define DRM_I915_FLUSH 0x01

162 #define DRM_I915_FLIP 0x02

163 #define DRM_I915_BATCHBUFFER 0x03

164 #define DRM_I915_IRQ_EMIT 0x04

165 #define DRM_I915_IRQ_WAIT 0x05

166 #define DRM_I915_GETPARAM 0x06

167 #define DRM_I915_SETPARAM 0x07

168 #define DRM_I915_ALLOC 0x08

169 #define DRM_I915_FREE 0x09

170 #define DRM_I915_INIT_HEAP 0x0a

171 #define DRM_I915_CMDBUFFER 0x0b

172 #define DRM_I915_DESTROY_HEAP 0x0c

173 #define DRM_I915_SET_VBLANK_PIPE 0x0d

174 #define DRM_I915_GET_VBLANK_PIPE 0x0e

175 #define DRM_I915_VBLANK_SWAP 0x0f

176 #define DRM_I915_MMIO 0x10

177 #define DRM_I915_HWS_ADDR 0x11

178 #define DRM_I915_EXECBUFFER 0x12

179

180 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)

181 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)

182 #define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)

183 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)

184 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)

185 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)

186 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)

187 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)

188 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)

189 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)

190 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)

191 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)

192 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)

193 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)

194 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)

195 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)

196 #define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)

197 #define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)

198

199 /* Asynchronous page flipping:

200 */

201 typedef struct drm_i915_flip {

202 /*

203 * This is really talking about planes, and we could rename it

204 * except for the fact that some of the duplicated i915_drm.h files

205 * out there check for HAVE_I915_FLIP and so might pick up this

206 * version.

207 */

208 int pipes;

209 } drm_i915_flip_t;

210

211 /* Allow drivers to submit batchbuffers directly to hardware, relying

212 * on the security mechanisms provided by hardware.

213 */

214 typedef struct drm_i915_batchbuffer {

215 int start; /* agp offset */

216 int used; /* nr bytes in use */

217 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */

218 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */

219 int num_cliprects; /* mulitpass with multiple cliprects? */

220 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */

221 } drm_i915_batchbuffer_t;

222

223 /* As above, but pass a pointer to userspace buffer which can be

224 * validated by the kernel prior to sending to hardware.

225 */

226 typedef struct _drm_i915_cmdbuffer {

227 char __user *buf; /* pointer to userspace command buffer */

228 int sz; /* nr bytes in buf */

229 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */

230 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */

231 int num_cliprects; /* mulitpass with multiple cliprects? */

232 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */

233 } drm_i915_cmdbuffer_t;

234

235 /* Userspace can request & wait on irq's:

236 */

237 typedef struct drm_i915_irq_emit {

238 int __user *irq_seq;

239 } drm_i915_irq_emit_t;

240

241 typedef struct drm_i915_irq_wait {

242 int irq_seq;

243 } drm_i915_irq_wait_t;

244

245 /* Ioctl to query kernel params:

246 */

247 #define I915_PARAM_IRQ_ACTIVE 1

248 #define I915_PARAM_ALLOW_BATCHBUFFER 2

249 #define I915_PARAM_LAST_DISPATCH 3

250 #define I915_PARAM_CHIPSET_ID 4

251

252 typedef struct drm_i915_getparam {

253 int param;

254 int __user *value;

255 } drm_i915_getparam_t;

256

257 /* Ioctl to set kernel params:

258 */

259 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1

260 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2

261 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3

262

263 typedef struct drm_i915_setparam {

264 int param;

265 int value;

266 } drm_i915_setparam_t;

267

268 /* A memory manager for regions of shared memory:

269 */

270 #define I915_MEM_REGION_AGP 1

271

272 typedef struct drm_i915_mem_alloc {

273 int region;

274 int alignment;

275 int size;

276 int __user *region_offset; /* offset from start of fb or agp */

277 } drm_i915_mem_alloc_t;

278

279 typedef struct drm_i915_mem_free {

280 int region;

281 int region_offset;

282 } drm_i915_mem_free_t;

283

284 typedef struct drm_i915_mem_init_heap {

285 int region;

286 int size;

287 int start;

288 } drm_i915_mem_init_heap_t;

289

290 /* Allow memory manager to be torn down and re-initialized (eg on

291 * rotate):

292 */

293 typedef struct drm_i915_mem_destroy_heap {

294 int region;

295 } drm_i915_mem_destroy_heap_t;

296

297 /* Allow X server to configure which pipes to monitor for vblank signals

298 */

299 #define DRM_I915_VBLANK_PIPE_A 1

300 #define DRM_I915_VBLANK_PIPE_B 2

301

302 typedef struct drm_i915_vblank_pipe {

303 int pipe;

304 } drm_i915_vblank_pipe_t;

305

306 /* Schedule buffer swap at given vertical blank:

307 */

308 typedef struct drm_i915_vblank_swap {

309 drm_drawable_t drawable;

310 enum drm_vblank_seq_type seqtype;

311 unsigned int sequence;

312 } drm_i915_vblank_swap_t;

313

314 #define I915_MMIO_READ 0

315 #define I915_MMIO_WRITE 1

316

317 #define I915_MMIO_MAY_READ 0x1

318 #define I915_MMIO_MAY_WRITE 0x2

319

320 #define MMIO_REGS_IA_PRIMATIVES_COUNT 0

321 #define MMIO_REGS_IA_VERTICES_COUNT 1

322 #define MMIO_REGS_VS_INVOCATION_COUNT 2

323 #define MMIO_REGS_GS_PRIMITIVES_COUNT 3

324 #define MMIO_REGS_GS_INVOCATION_COUNT 4

325 #define MMIO_REGS_CL_PRIMITIVES_COUNT 5

326 #define MMIO_REGS_CL_INVOCATION_COUNT 6

327 #define MMIO_REGS_PS_INVOCATION_COUNT 7

328 #define MMIO_REGS_PS_DEPTH_COUNT 8

329

330 typedef struct drm_i915_mmio_entry {

331 unsigned int flag;

332 unsigned int offset;

333 unsigned int size;

334 } drm_i915_mmio_entry_t;

335

336 typedef struct drm_i915_mmio {

337 unsigned int read_write:1;

338 unsigned int reg:31;

339 void __user *data;

340 } drm_i915_mmio_t;

341

342 typedef struct drm_i915_hws_addr {

343 uint64_t addr;

344 } drm_i915_hws_addr_t;

345

346 /*

347 * Relocation header is 4 uint32_ts

348 * 0 - 32 bit reloc count

349 * 1 - 32-bit relocation type

350 * 2-3 - 64-bit user buffer handle ptr for another list of relocs.

351 */

352 #define I915_RELOC_HEADER 4

353

354 /*

355 * type 0 relocation has 4-uint32_t stride

356 * 0 - offset into buffer

357 * 1 - delta to add in

358 * 2 - buffer handle

359 * 3 - reserved (for optimisations later).

360 */

361 #define I915_RELOC_TYPE_0 0

362 #define I915_RELOC0_STRIDE 4

363

364 struct drm_i915_op_arg {

365 uint64_t next;

366 uint64_t reloc_ptr;

367 int handled;

368 union {

369 struct drm_bo_op_req req;

370 struct drm_bo_arg_rep rep;

371 } d;

372

373 };

374

375 struct drm_i915_execbuffer {

376 uint64_t ops_list;

377 uint32_t num_buffers;

378 struct drm_i915_batchbuffer batch;

379 drm_context_t context; /* for lockless use in the future */

380 struct drm_fence_arg fence_arg;

381 };

382

383 #endif /* _I915_DRM_H_ */