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1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-

2 */

3 /*

4 *

7 *

8 * Permission is hereby granted, free of charge, to any person obtaining a

9 * copy of this software and associated documentation files (the

10 * "Software"), to deal in the Software without restriction, including

11 * without limitation the rights to use, copy, modify, merge, publish,

12 * distribute, sub license, and/or sell copies of the Software, and to

13 * permit persons to whom the Software is furnished to do so, subject to

14 * the following conditions:

15 *

16 * The above copyright notice and this permission notice (including the

17 * next paragraph) shall be included in all copies or substantial portions

18 * of the Software.

19 *

20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

27 *

28 */

29

30 #ifndef _I915_DRV_H_

31 #define _I915_DRV_H_

32

33 /* General customization:

34 */

35

36 #include "intel_bios.h"

37

38 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."

39

40 #define DRIVER_NAME "i915"

41 #define DRIVER_DESC "Intel Graphics"

42 #define DRIVER_DATE "20080730"

43

44 #if defined(__linux__)

45 #define I915_HAVE_BUFFER

46 #endif

47

48 /* Interface history:

49 *

50 * 1.1: Original.

51 * 1.2: Add Power Management

52 * 1.3: Add vblank support

53 * 1.4: Fix cmdbuffer path, add heap destroy

54 * 1.5: Add vblank pipe configuration

55 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank

56 * - Support vertical blank on secondary display pipe

57 * 1.8: New ioctl for ARB_Occlusion_Query

58 * 1.9: Usable page flipping and triple buffering

59 * 1.10: Plane/pipe disentangling

60 * 1.11: TTM superioctl

61 * 1.12: TTM relocation optimization

62 */

63 #define DRIVER_MAJOR 1

64 #if defined(I915_HAVE_BUFFER)

65 #define DRIVER_MINOR 13

66 #else

67 #define DRIVER_MINOR 6

68 #endif

69 #define DRIVER_PATCHLEVEL 0

70

71 enum pipe {

72 PIPE_A = 0,

73 PIPE_B,

74 };

75

76 #ifdef I915_HAVE_BUFFER

77 #define I915_MAX_VALIDATE_BUFFERS 4096

78 struct drm_i915_validate_buffer;

79 #endif

80

81 #define WATCH_COHERENCY 0

82 #define WATCH_BUF 0

83 #define WATCH_EXEC 0

84 #define WATCH_LRU 0

85 #define WATCH_RELOC 0

86 #define WATCH_INACTIVE 0

87 #define WATCH_PWRITE 0

88

89 struct drm_i915_ring_buffer {

90 int tail_mask;

91 unsigned long Size;

92 u8 *virtual_start;

93 int head;

94 int tail;

95 int space;

96 drm_local_map_t map;

97 struct drm_gem_object *ring_obj;

98 };

99

100 struct mem_block {

101 struct mem_block *next;

102 struct mem_block *prev;

103 int start;

104 int size;

105 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */

106 };

107

108 struct drm_i915_vbl_swap {

109 struct list_head head;

110 drm_drawable_t drw_id;

111 unsigned int plane;

112 unsigned int sequence;

113 int flip;

114 struct drm_minor *minor;

115 };

116

117

118 #ifdef __linux__

119 struct opregion_header;

120 struct opregion_acpi;

121 struct opregion_swsci;

122 struct opregion_asle;

123

124 struct intel_opregion {

125 struct opregion_header *header;

126 struct opregion_acpi *acpi;

127 struct opregion_swsci *swsci;

128 struct opregion_asle *asle;

129

130 int enabled;

131 };

132 #endif

133

134 struct drm_i915_master_private {

135 drm_local_map_t *sarea;

136 struct drm_i915_sarea *sarea_priv;

137 };

138

139 struct drm_i915_private {

140 struct drm_device *dev;

141

142 drm_local_map_t *mmio_map;

143

144 unsigned long mmiobase;

145 unsigned long mmiolen;

146

147 struct drm_i915_ring_buffer ring;

148

149 struct drm_dma_handle *status_page_dmah;

150 void *hw_status_page;

151 dma_addr_t dma_status_page;

152 uint32_t counter;

153 uint32_t status_gfx_addr;

154 drm_local_map_t hws_map;

155 struct drm_gem_object *hws_obj;

156

157 unsigned int cpp;

158

159 wait_queue_head_t irq_queue;

160 atomic_t irq_received;

161

162 int tex_lru_log_granularity;

163 int allow_batchbuffer;

164 struct mem_block *agp_heap;

165 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;

166 int vblank_pipe;

167 DRM_SPINTYPE user_irq_lock;

168 int user_irq_refcount;

169 int fence_irq_on;

170 uint32_t irq_mask_reg;

171 int irq_enabled;

172 struct workqueue_struct *wq;

173

174 bool cursor_needs_physical;

175

176 struct drm_mm vram;

177

178 #ifdef I915_HAVE_BUFFER

179 void *agp_iomap;

180 unsigned int max_validate_buffers;

181 struct mutex cmdbuf_mutex;

182 u32 stolen_base;

183 struct drm_i915_validate_buffer *val_bufs;

184 #endif

185

186 DRM_SPINTYPE swaps_lock;

187 struct drm_i915_vbl_swap vbl_swaps;

188 unsigned int swaps_pending;

189

190 /* LVDS info */

191 int backlight_duty_cycle; /* restore backlight to this value */

192 bool panel_wants_dither;

193 struct drm_display_mode *panel_fixed_mode;

194 struct drm_display_mode *vbt_mode; /* if any */

195

196 #if defined(I915_HAVE_BUFFER) && defined(DRI2)

197 /* DRI2 sarea */

198 struct drm_gem_object *sarea_object;

199 struct drm_bo_kmap_obj sarea_kmap;

200 #endif

201

202 /* Feature bits from the VBIOS */

203 int int_tv_support:1;

204 int lvds_dither:1;

205 int lvds_vbt:1;

206 int int_crt_support:1;

207

208 struct work_struct user_interrupt_task;

209

210 #ifdef __linux__

211 struct intel_opregion opregion;

212 #endif

213

214 /* Register state */

215 u8 saveLBB;

216 u32 saveDSPACNTR;

217 u32 saveDSPBCNTR;

218 u32 saveDSPARB;

219 u32 savePIPEACONF;

220 u32 savePIPEBCONF;

221 u32 savePIPEASRC;

222 u32 savePIPEBSRC;

223 u32 saveFPA0;

224 u32 saveFPA1;

225 u32 saveDPLL_A;

226 u32 saveDPLL_A_MD;

227 u32 saveHTOTAL_A;

228 u32 saveHBLANK_A;

229 u32 saveHSYNC_A;

230 u32 saveVTOTAL_A;

231 u32 saveVBLANK_A;

232 u32 saveVSYNC_A;

233 u32 saveBCLRPAT_A;

234 u32 savePIPEASTAT;

235 u32 saveDSPASTRIDE;

236 u32 saveDSPASIZE;

237 u32 saveDSPAPOS;

238 u32 saveDSPAADDR;

239 u32 saveDSPASURF;

240 u32 saveDSPATILEOFF;

241 u32 savePFIT_PGM_RATIOS;

242 u32 saveBLC_PWM_CTL;

243 u32 saveBLC_PWM_CTL2;

244 u32 saveFPB0;

245 u32 saveFPB1;

246 u32 saveDPLL_B;

247 u32 saveDPLL_B_MD;

248 u32 saveHTOTAL_B;

249 u32 saveHBLANK_B;

250 u32 saveHSYNC_B;

251 u32 saveVTOTAL_B;

252 u32 saveVBLANK_B;

253 u32 saveVSYNC_B;

254 u32 saveBCLRPAT_B;

255 u32 savePIPEBSTAT;

256 u32 saveDSPBSTRIDE;

257 u32 saveDSPBSIZE;

258 u32 saveDSPBPOS;

259 u32 saveDSPBADDR;

260 u32 saveDSPBSURF;

261 u32 saveDSPBTILEOFF;

262 u32 saveVGA0;

263 u32 saveVGA1;

264 u32 saveVGA_PD;

265 u32 saveVGACNTRL;

266 u32 saveADPA;

267 u32 saveLVDS;

268 u32 savePP_ON_DELAYS;

269 u32 savePP_OFF_DELAYS;

270 u32 saveDVOA;

271 u32 saveDVOB;

272 u32 saveDVOC;

273 u32 savePP_ON;

274 u32 savePP_OFF;

275 u32 savePP_CONTROL;

276 u32 savePP_DIVISOR;

277 u32 savePFIT_CONTROL;

278 u32 save_palette_a[256];

279 u32 save_palette_b[256];

280 u32 saveFBC_CFB_BASE;

281 u32 saveFBC_LL_BASE;

282 u32 saveFBC_CONTROL;

283 u32 saveFBC_CONTROL2;

284 u32 saveIER;

285 u32 saveIIR;

286 u32 saveIMR;

287 u32 saveCACHE_MODE_0;

288 u32 saveD_STATE;

289 u32 saveCG_2D_DIS;

290 u32 saveMI_ARB_STATE;

291 u32 saveSWF0[16];

292 u32 saveSWF1[16];

293 u32 saveSWF2[3];

294 u8 saveMSR;

295 u8 saveSR[8];

296 u8 saveGR[25];

297 u8 saveAR_INDEX;

298 u8 saveAR[21];

299 u8 saveDACMASK;

300 u8 saveDACDATA[256*3]; /* 256 3-byte colors */

301 u8 saveCR[37];

302

303 struct {

304 struct drm_mm gtt_space;

305

306 /**

307 * List of objects currently involved in rendering from the

308 * ringbuffer.

309 *

310 * A reference is held on the buffer while on this list.

311 */

312 struct list_head active_list;

313

314 /**

315 * List of objects which are not in the ringbuffer but which

316 * still have a write_domain which needs to be flushed before

317 * unbinding.

318 *

319 * A reference is held on the buffer while on this list.

320 */

321 struct list_head flushing_list;

322

323 /**

324 * LRU list of objects which are not in the ringbuffer and

325 * are ready to unbind, but are still in the GTT.

326 *

327 * A reference is not held on the buffer while on this list,

328 * as merely being GTT-bound shouldn't prevent its being

329 * freed, and we'll pull it off the list in the free path.

330 */

331 struct list_head inactive_list;

332

333 /**

334 * List of breadcrumbs associated with GPU requests currently

335 * outstanding.

336 */

337 struct list_head request_list;

338

339 /**

340 * We leave the user IRQ off as much as possible,

341 * but this means that requests will finish and never

342 * be retired once the system goes idle. Set a timer to

343 * fire periodically while the ring is running. When it

344 * fires, go retire requests.

345 */

346 struct delayed_work retire_work;

347

348 uint32_t next_gem_seqno;

349

350 /**

351 * Waiting sequence number, if any

352 */

353 uint32_t waiting_gem_seqno;

354

355 /**

356 * Last seq seen at irq time

357 */

358 uint32_t irq_gem_seqno;

359

360 /**

361 * Flag if the X Server, and thus DRM, is not currently in

362 * control of the device.

363 *

364 * This is set between LeaveVT and EnterVT. It needs to be

365 * replaced with a semaphore. It also needs to be

366 * transitioned away from for kernel modesetting.

367 */

368 int suspended;

369

370 /**

371 * Flag if the hardware appears to be wedged.

372 *

373 * This is set when attempts to idle the device timeout.

374 * It prevents command submission from occuring and makes

375 * every pending request fail

376 */

377 int wedged;

378

379 /** Bit 6 swizzling required for X tiling */

380 uint32_t bit_6_swizzle_x;

381 /** Bit 6 swizzling required for Y tiling */

382 uint32_t bit_6_swizzle_y;

383 } mm;

384 };

385

386 struct drm_i915_file_private {

387 struct {

388 uint32_t last_gem_seqno;

389 uint32_t last_gem_throttle_seqno;

390 } mm;

391 };

392

393 enum intel_chip_family {

394 CHIP_I8XX = 0x01,

395 CHIP_I9XX = 0x02,

396 CHIP_I915 = 0x04,

397 CHIP_I965 = 0x08,

398 };

399

400 /** driver private structure attached to each drm_gem_object */

401 struct drm_i915_gem_object {

402 struct drm_gem_object *obj;

403

404 /** Current space allocated to this object in the GTT, if any. */

405 struct drm_mm_node *gtt_space;

406

407 /** This object's place on the active/flushing/inactive lists */

408 struct list_head list;

409

410 /**

411 * This is set if the object is on the active or flushing lists

412 * (has pending rendering), and is not set if it's on inactive (ready

413 * to be unbound).

414 */

415 int active;

416

417 /**

418 * This is set if the object has been written to since last bound

419 * to the GTT

420 */

421 int dirty;

422

423 /** AGP memory structure for our GTT binding. */

424 DRM_AGP_MEM *agp_mem;

425

426 struct page **page_list;

427

428 /**

429 * Current offset of the object in GTT space.

430 *

431 * This is the same as gtt_space->start

432 */

433 uint32_t gtt_offset;

434

435 /** Boolean whether this object has a valid gtt offset. */

436 int gtt_bound;

437

438 /** How many users have pinned this object in GTT space */

439 int pin_count;

440

441 /** Breadcrumb of last rendering to the buffer. */

442 uint32_t last_rendering_seqno;

443

444 /** Current tiling mode for the object. */

445 uint32_t tiling_mode;

446

447 /**

448 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when

449 * GEM_DOMAIN_CPU is not in the object's read domain.

450 */

451 uint8_t *page_cpu_valid;

452 };

453

454 /**

455 * Request queue structure.

456 *

457 * The request queue allows us to note sequence numbers that have been emitted

458 * and may be associated with active buffers to be retired.

459 *

460 * By keeping this list, we can avoid having to do questionable

461 * sequence-number comparisons on buffer last_rendering_seqnos, and associate

462 * an emission time with seqnos for tracking how far ahead of the GPU we are.

463 */

464 struct drm_i915_gem_request {

465 /** GEM sequence number associated with this request. */

466 uint32_t seqno;

467

468 /** Time at which this request was emitted, in jiffies. */

469 unsigned long emitted_jiffies;

470

471 /** Cache domains that were flushed at the start of the request. */

472 uint32_t flush_domains;

473

474 struct list_head list;

475 };

476

477 extern struct drm_ioctl_desc i915_ioctls[];

478 extern int i915_max_ioctl;

479

480 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);

481 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);

482 /* i915_dma.c */

483 extern void i915_kernel_lost_context(struct drm_device * dev);

484 extern int i915_driver_load(struct drm_device *, unsigned long flags);

485 extern int i915_driver_unload(struct drm_device *dev);

486 extern void i915_driver_lastclose(struct drm_device * dev);

487 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);

488 extern void i915_driver_preclose(struct drm_device *dev,

489 struct drm_file *file_priv);

490 extern void i915_driver_postclose(struct drm_device *dev,

491 struct drm_file *file_priv);

492 extern int i915_driver_device_is_agp(struct drm_device * dev);

493 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,

494 unsigned long arg);

495 extern void i915_emit_breadcrumb(struct drm_device *dev);

496 extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync);

497 extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush);

498 extern int i915_driver_firstopen(struct drm_device *dev);

499 extern int i915_do_cleanup_pageflip(struct drm_device *dev);

500 extern int i915_dma_cleanup(struct drm_device *dev);

501 extern int i915_dispatch_batchbuffer(struct drm_device * dev,

502 drm_i915_batchbuffer_t * batch);

503 extern int i915_quiescent(struct drm_device *dev);

504

505 int i915_emit_box(struct drm_device * dev,

506 struct drm_clip_rect __user * boxes,

507 int i, int DR1, int DR4);

508

509 /* i915_irq.c */

510 extern int i915_irq_emit(struct drm_device *dev, void *data,

511 struct drm_file *file_priv);

512 extern int i915_irq_wait(struct drm_device *dev, void *data,

513 struct drm_file *file_priv);

514

515 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);

516 extern void i915_driver_irq_preinstall(struct drm_device * dev);

517 extern int i915_driver_irq_postinstall(struct drm_device * dev);

518 extern void i915_driver_irq_uninstall(struct drm_device * dev);

519 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,

520 struct drm_file *file_priv);

521 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,

522 struct drm_file *file_priv);

523 extern int i915_emit_irq(struct drm_device * dev);

524 extern void i915_enable_interrupt (struct drm_device *dev);

525 extern int i915_wait_irq(struct drm_device * dev, int irq_nr);

526 extern int i915_enable_vblank(struct drm_device *dev, int crtc);

527 extern void i915_disable_vblank(struct drm_device *dev, int crtc);

528 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);

529 extern int i915_vblank_swap(struct drm_device *dev, void *data,

530 struct drm_file *file_priv);

531 extern void i915_user_irq_on(struct drm_device *dev);

532 extern void i915_user_irq_off(struct drm_device *dev);

533

534 /* i915_mem.c */

535 extern int i915_mem_alloc(struct drm_device *dev, void *data,

536 struct drm_file *file_priv);

537 extern int i915_mem_free(struct drm_device *dev, void *data,

538 struct drm_file *file_priv);

539 extern int i915_mem_init_heap(struct drm_device *dev, void *data,

540 struct drm_file *file_priv);

541 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,

542 struct drm_file *file_priv);

543 extern void i915_mem_takedown(struct mem_block **heap);

544 extern void i915_mem_release(struct drm_device * dev,

545 struct drm_file *file_priv,

546 struct mem_block *heap);

547

548 /* i915_suspend.c */

549 extern int i915_save_state(struct drm_device *dev);

550 extern int i915_restore_state(struct drm_device *dev);

551

552 #ifdef I915_HAVE_BUFFER

553 /* i915_gem.c */

554 int i915_gem_init_ioctl(struct drm_device *dev, void *data,

555 struct drm_file *file_priv);

556 int i915_gem_create_ioctl(struct drm_device *dev, void *data,

557 struct drm_file *file_priv);

558 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,

559 struct drm_file *file_priv);

560 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,

561 struct drm_file *file_priv);

562 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,

563 struct drm_file *file_priv);

564 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,

565 struct drm_file *file_priv);

566 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,

567 struct drm_file *file_priv);

568 int i915_gem_execbuffer(struct drm_device *dev, void *data,

569 struct drm_file *file_priv);

570 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,

571 struct drm_file *file_priv);

572 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,

573 struct drm_file *file_priv);

574 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,

575 struct drm_file *file_priv);

576 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,

577 struct drm_file *file_priv);

578 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,

579 struct drm_file *file_priv);

580 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,

581 struct drm_file *file_priv);

582 int i915_gem_set_tiling(struct drm_device *dev, void *data,

583 struct drm_file *file_priv);

584 int i915_gem_get_tiling(struct drm_device *dev, void *data,

585 struct drm_file *file_priv);

586 void i915_gem_load(struct drm_device *dev);

587 int i915_gem_proc_init(struct drm_minor *minor);

588 void i915_gem_proc_cleanup(struct drm_minor *minor);

589 int i915_gem_init_object(struct drm_gem_object *obj);

590 void i915_gem_free_object(struct drm_gem_object *obj);

591 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);

592 void i915_gem_object_unpin(struct drm_gem_object *obj);

593 void i915_gem_lastclose(struct drm_device *dev);

594 uint32_t i915_get_gem_seqno(struct drm_device *dev);

595 void i915_gem_retire_requests(struct drm_device *dev);

596 int i915_gem_init_ringbuffer(struct drm_device *dev);

597 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);

598 int i915_gem_do_init(struct drm_device *dev, unsigned long start,

599 unsigned long end);

600 int i915_gem_object_set_domain(struct drm_gem_object *obj,

601 uint32_t read_domains,

602 uint32_t write_domain);

603 void i915_gem_retire_work_handler(struct work_struct *work);

604 void i915_gem_clflush_object(struct drm_gem_object *obj);

605 #endif

606

607 extern unsigned int i915_fbpercrtc;

608

609 /* i915_gem_tiling.c */

610 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);

611

612 /* i915_gem_debug.c */

613 void i915_gem_dump_object(struct drm_gem_object *obj, int len,

614 const char *where, uint32_t mark);

615 #if WATCH_INACTIVE

616 void i915_verify_inactive(struct drm_device *dev, char *file, int line);

617 #else

618 #define i915_verify_inactive(dev,file,line)

619 #endif

620 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);

621 void i915_gem_dump_object(struct drm_gem_object *obj, int len,

622 const char *where, uint32_t mark);

623 void i915_dump_lru(struct drm_device *dev, const char *where);

624

625 #ifdef __linux__

626 /* i915_opregion.c */

627 extern int intel_opregion_init(struct drm_device *dev);

628 extern void intel_opregion_free(struct drm_device *dev);

629 extern void opregion_asle_intr(struct drm_device *dev);

630 extern void opregion_enable_asle(struct drm_device *dev);

631 #endif

632

633 #ifdef __linux__

634 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)

635 extern void intel_init_chipset_flush_compat(struct drm_device *dev);

636 extern void intel_fini_chipset_flush_compat(struct drm_device *dev);

637 #endif

638 #endif

639

640

641 /* modesetting */

642 extern void intel_modeset_init(struct drm_device *dev);

643 extern void intel_modeset_cleanup(struct drm_device *dev);

644

645

646 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))

647 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))

648 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))

649 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))

650 #define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg))

651 #define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val))

652

653 #if defined(__FreeBSD__)

654 typedef boolean_t bool;

655 #endif

656

657 #define I915_VERBOSE 0

658 #define I915_RING_VALIDATE 0

659

660 #define PRIMARY_RINGBUFFER_SIZE (128*1024)

661

662 #define PRIMARY_RINGBUFFER_SIZE (128*1024)

663

664 #define RING_LOCALS unsigned int outring, ringmask, outcount; \

665 volatile char *virt;

666

667 #if I915_RING_VALIDATE

668 void i915_ring_validate(struct drm_device *dev, const char *func, int line);

669 #define I915_RING_DO_VALIDATE(dev) i915_ring_validate(dev, __FUNCTION__, __LINE__)

670 #else

671 #define I915_RING_DO_VALIDATE(dev)

672 #endif

673

674 #define BEGIN_LP_RING(n) do { \

675 if (I915_VERBOSE) \

676 DRM_DEBUG("BEGIN_LP_RING(%d)\n", \

677 (n)); \

678 I915_RING_DO_VALIDATE(dev); \

679 if (dev_priv->ring.space < (n)*4) \

680 i915_wait_ring(dev, (n)*4, __FUNCTION__); \

681 outcount = 0; \

682 outring = dev_priv->ring.tail; \

683 ringmask = dev_priv->ring.tail_mask; \

684 virt = dev_priv->ring.virtual_start; \

685 } while (0)

686

687 #define OUT_RING(n) do { \

688 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \

689 *(volatile unsigned int *)(virt + outring) = (n); \

690 outcount++; \

691 outring += 4; \

692 outring &= ringmask; \

693 } while (0)

694

695 #define ADVANCE_LP_RING() do { \

696 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \

697 I915_RING_DO_VALIDATE(dev); \

698 dev_priv->ring.tail = outring; \

699 dev_priv->ring.space -= outcount * 4; \

700 I915_WRITE(PRB0_TAIL, outring); \

701 } while(0)

702

703 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);

704

705 #define BREADCRUMB_BITS 31

706 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)

707

708 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])

709 /**

710 * Reads a dword out of the status page, which is written to from the command

711 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or

712 * MI_STORE_DATA_IMM.

713 *

714 * The following dwords have a reserved meaning:

715 * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.

716 * 4: ring 0 head pointer

717 * 5: ring 1 head pointer (915-class)

718 * 6: ring 2 head pointer (915-class)

719 *

720 * The area from dword 0x10 to 0x3ff is available for driver usage.

721 */

722 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])

723 #define I915_GEM_HWS_INDEX 0x10

724

725 /* MCH MMIO space */

726 /** 915-945 and GM965 MCH register controlling DRAM channel access */

727 #define DCC 0x200

728 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)

729 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)

730 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)

731 #define DCC_ADDRESSING_MODE_MASK (3 << 0)

732 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)

733

734 /** 965 MCH register controlling DRAM channel configuration */

735 #define CHDECMISC 0x111

736 #define CHDECMISC_FLEXMEMORY (1 << 1)

737

738 /*

739 * The Bridge device's PCI config space has information about the

740 * fb aperture size and the amount of pre-reserved memory.

741 */

742 #define INTEL_GMCH_CTRL 0x52

743 #define INTEL_GMCH_ENABLED 0x4

744 #define INTEL_GMCH_MEM_MASK 0x1

745 #define INTEL_GMCH_MEM_64M 0x1

746 #define INTEL_GMCH_MEM_128M 0

747

748 #define INTEL_855_GMCH_GMS_MASK (0x7 << 4)

749 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)

750 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)

751 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)

752 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)

753 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)

754 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)

755

756 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)

757 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)

758

759 /* PCI config space */

760

761 #define HPLLCC 0xc0 /* 855 only */

762 #define GC_CLOCK_CONTROL_MASK (3 << 0)

763 #define GC_CLOCK_133_200 (0 << 0)

764 #define GC_CLOCK_100_200 (1 << 0)

765 #define GC_CLOCK_100_133 (2 << 0)

766 #define GC_CLOCK_166_250 (3 << 0)

767 #define GCFGC 0xf0 /* 915+ only */

768 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)

769 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)

770 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)

771 #define GC_DISPLAY_CLOCK_MASK (7 << 4)

772 #define LBB 0xf4

773

774 /* VGA stuff */

775

776 #define VGA_ST01_MDA 0x3ba

777 #define VGA_ST01_CGA 0x3da

778

779 #define VGA_MSR_WRITE 0x3c2

780 #define VGA_MSR_READ 0x3cc

781 #define VGA_MSR_MEM_EN (1<<1)

782 #define VGA_MSR_CGA_MODE (1<<0)

783

784 #define VGA_SR_INDEX 0x3c4

785 #define VGA_SR_DATA 0x3c5

786

787 #define VGA_AR_INDEX 0x3c0

788 #define VGA_AR_VID_EN (1<<5)

789 #define VGA_AR_DATA_WRITE 0x3c0

790 #define VGA_AR_DATA_READ 0x3c1

791

792 #define VGA_GR_INDEX 0x3ce

793 #define VGA_GR_DATA 0x3cf

794 /* GR05 */

795 #define VGA_GR_MEM_READ_MODE_SHIFT 3

796 #define VGA_GR_MEM_READ_MODE_PLANE 1

797 /* GR06 */

798 #define VGA_GR_MEM_MODE_MASK 0xc

799 #define VGA_GR_MEM_MODE_SHIFT 2

800 #define VGA_GR_MEM_A0000_AFFFF 0

801 #define VGA_GR_MEM_A0000_BFFFF 1

802 #define VGA_GR_MEM_B0000_B7FFF 2

803 #define VGA_GR_MEM_B0000_BFFFF 3

804

805 #define VGA_DACMASK 0x3c6

806 #define VGA_DACRX 0x3c7

807 #define VGA_DACWX 0x3c8

808 #define VGA_DACDATA 0x3c9

809

810 #define VGA_CR_INDEX_MDA 0x3b4

811 #define VGA_CR_DATA_MDA 0x3b5

812 #define VGA_CR_INDEX_CGA 0x3d4

813 #define VGA_CR_DATA_CGA 0x3d5

814

815 /*

816 * Memory interface instructions used by the kernel

817 */

818 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))

819

820 #define MI_NOOP MI_INSTR(0, 0)

821 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)

822 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)

823 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)

824 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)

825 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)

826 #define MI_FLUSH MI_INSTR(0x04, 0)

827 #define MI_READ_FLUSH (1 << 0)

828 #define MI_EXE_FLUSH (1 << 1)

829 #define MI_NO_WRITE_FLUSH (1 << 2)

830 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */

831 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */

832 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)

833 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)

834 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)

835 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)

836 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */

837 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)

838 #define MI_STORE_DWORD_INDEX_SHIFT 2

839 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)

840 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)

841 #define MI_BATCH_NON_SECURE (1)

842 #define MI_BATCH_NON_SECURE_I965 (1<<8)

843 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)

844

845 /*

846 * 3D instructions used by the kernel

847 */

848 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))

849

850 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))

851 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))

852 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))

853 #define SC_UPDATE_SCISSOR (0x1<<1)

854 #define SC_ENABLE_MASK (0x1<<0)

855 #define SC_ENABLE (0x1<<0)

856 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))

857 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))

858 #define SCI_YMIN_MASK (0xffff<<16)

859 #define SCI_XMIN_MASK (0xffff<<0)

860 #define SCI_YMAX_MASK (0xffff<<16)

861 #define SCI_XMAX_MASK (0xffff<<0)

862 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))

863 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)

864 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)

865 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))

866 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)

867 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)

868 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)

869 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))

870 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)

871 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)

872 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)

873 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)

874 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)

875 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)

876 #define BLT_DEPTH_8 (0<<24)

877 #define BLT_DEPTH_16_565 (1<<24)

878 #define BLT_DEPTH_16_1555 (2<<24)

879 #define BLT_DEPTH_32 (3<<24)

880 #define BLT_ROP_GXCOPY (0xcc<<16)

881 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */

882 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */

883 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)

884 #define ASYNC_FLIP (1<<22)

885 #define DISPLAY_PLANE_A (0<<20)

886 #define DISPLAY_PLANE_B (1<<20)

887

888 /*

889 * Instruction and interrupt control regs

890 */

891

892 #define PRB0_TAIL 0x02030

893 #define PRB0_HEAD 0x02034

894 #define PRB0_START 0x02038

895 #define PRB0_CTL 0x0203c

896 #define TAIL_ADDR 0x001FFFF8

897 #define HEAD_WRAP_COUNT 0xFFE00000

898 #define HEAD_WRAP_ONE 0x00200000

899 #define HEAD_ADDR 0x001FFFFC

900 #define RING_NR_PAGES 0x001FF000

901 #define RING_REPORT_MASK 0x00000006

902 #define RING_REPORT_64K 0x00000002

903 #define RING_REPORT_128K 0x00000004

904 #define RING_NO_REPORT 0x00000000

905 #define RING_VALID_MASK 0x00000001

906 #define RING_VALID 0x00000001

907 #define RING_INVALID 0x00000000

908 #define PRB1_TAIL 0x02040 /* 915+ only */

909 #define PRB1_HEAD 0x02044 /* 915+ only */

910 #define PRB1_START 0x02048 /* 915+ only */

911 #define PRB1_CTL 0x0204c /* 915+ only */

912 #define ACTHD_I965 0x02074

913 #define HWS_PGA 0x02080

914 #define HWS_ADDRESS_MASK 0xfffff000

915 #define HWS_START_ADDRESS_SHIFT 4

916 #define IPEIR 0x02088

917 #define NOPID 0x02094

918 #define HWSTAM 0x02098

919 #define SCPD0 0x0209c /* 915+ only */

920 #define IER 0x020a0

921 #define IIR 0x020a4

922 #define IMR 0x020a8

923 #define ISR 0x020ac

924 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)

925 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)

926 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)

927 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)

928 #define I915_HWB_OOM_INTERRUPT (1<<13)

929 #define I915_SYNC_STATUS_INTERRUPT (1<<12)

930 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)

931 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)

932 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)

933 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)

934 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)

935 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)

936 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)

937 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)

938 #define I915_DEBUG_INTERRUPT (1<<2)

939 #define I915_USER_INTERRUPT (1<<1)

940 #define I915_ASLE_INTERRUPT (1<<0)

941 #define EIR 0x020b0

942 #define EMR 0x020b4

943 #define ESR 0x020b8

944 #define INSTPM 0x020c0

945 #define ACTHD 0x020c8

946 #define FW_BLC 0x020d8

947 #define FW_BLC_SELF 0x020e0 /* 915+ only */

948 #define MI_ARB_STATE 0x020e4 /* 915+ only */

949 #define CACHE_MODE_0 0x02120 /* 915+ only */

950 #define CM0_MASK_SHIFT 16

951 #define CM0_IZ_OPT_DISABLE (1<<6)

952 #define CM0_ZR_OPT_DISABLE (1<<5)

953 #define CM0_DEPTH_EVICT_DISABLE (1<<4)

954 #define CM0_COLOR_EVICT_DISABLE (1<<3)

955 #define CM0_DEPTH_WRITE_DISABLE (1<<1)

956 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)

957 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */

958

959 /*

960 * Framebuffer compression (915+ only)

961 */

962

963 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */

964 #define FBC_LL_BASE 0x03204 /* 4k page aligned */

965 #define FBC_CONTROL 0x03208

966 #define FBC_CTL_EN (1<<31)

967 #define FBC_CTL_PERIODIC (1<<30)

968 #define FBC_CTL_INTERVAL_SHIFT (16)

969 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)

970 #define FBC_CTL_STRIDE_SHIFT (5)

971 #define FBC_CTL_FENCENO (1<<0)

972 #define FBC_COMMAND 0x0320c

973 #define FBC_CMD_COMPRESS (1<<0)

974 #define FBC_STATUS 0x03210

975 #define FBC_STAT_COMPRESSING (1<<31)

976 #define FBC_STAT_COMPRESSED (1<<30)

977 #define FBC_STAT_MODIFIED (1<<29)

978 #define FBC_STAT_CURRENT_LINE (1<<0)

979 #define FBC_CONTROL2 0x03214

980 #define FBC_CTL_FENCE_DBL (0<<4)

981 #define FBC_CTL_IDLE_IMM (0<<2)

982 #define FBC_CTL_IDLE_FULL (1<<2)

983 #define FBC_CTL_IDLE_LINE (2<<2)

984 #define FBC_CTL_IDLE_DEBUG (3<<2)

985 #define FBC_CTL_CPU_FENCE (1<<1)

986 #define FBC_CTL_PLANEA (0<<0)

987 #define FBC_CTL_PLANEB (1<<0)

988 #define FBC_FENCE_OFF 0x0321b

989

990 #define FBC_LL_SIZE (1536)

991

992 /*

993 * GPIO regs

994 */

995 #define GPIOA 0x5010

996 #define GPIOB 0x5014

997 #define GPIOC 0x5018

998 #define GPIOD 0x501c

999 #define GPIOE 0x5020

1000 #define GPIOF 0x5024

1001 #define GPIOG 0x5028

1002 #define GPIOH 0x502c

1003 # define GPIO_CLOCK_DIR_MASK (1 << 0)

1004 # define GPIO_CLOCK_DIR_IN (0 << 1)

1005 # define GPIO_CLOCK_DIR_OUT (1 << 1)

1006 # define GPIO_CLOCK_VAL_MASK (1 << 2)

1007 # define GPIO_CLOCK_VAL_OUT (1 << 3)

1008 # define GPIO_CLOCK_VAL_IN (1 << 4)

1009 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)

1010 # define GPIO_DATA_DIR_MASK (1 << 8)

1011 # define GPIO_DATA_DIR_IN (0 << 9)

1012 # define GPIO_DATA_DIR_OUT (1 << 9)

1013 # define GPIO_DATA_VAL_MASK (1 << 10)

1014 # define GPIO_DATA_VAL_OUT (1 << 11)

1015 # define GPIO_DATA_VAL_IN (1 << 12)

1016 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)

1017

1018 /*

1019 * Clock control & power management

1020 */

1021

1022 #define VGA0 0x6000

1023 #define VGA1 0x6004

1024 #define VGA_PD 0x6010

1025 #define VGA0_PD_P2_DIV_4 (1 << 7)

1026 #define VGA0_PD_P1_DIV_2 (1 << 5)

1027 #define VGA0_PD_P1_SHIFT 0

1028 #define VGA0_PD_P1_MASK (0x1f << 0)

1029 #define VGA1_PD_P2_DIV_4 (1 << 15)

1030 #define VGA1_PD_P1_DIV_2 (1 << 13)

1031 #define VGA1_PD_P1_SHIFT 8

1032 #define VGA1_PD_P1_MASK (0x1f << 8)

1033 #define DPLL_A 0x06014

1034 #define DPLL_B 0x06018

1035 #define DPLL_VCO_ENABLE (1 << 31)

1036 #define DPLL_DVO_HIGH_SPEED (1 << 30)

1037 #define DPLL_SYNCLOCK_ENABLE (1 << 29)

1038 #define DPLL_VGA_MODE_DIS (1 << 28)

1039 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */

1040 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */

1041 #define DPLL_MODE_MASK (3 << 26)

1042 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */

1043 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */

1044 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */

1045 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */

1046 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */

1047 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */

1048 /*

1049 * Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register

1050 * and is 24 bits wide.

1051 */

1052 #define PIPE_PIXEL_MASK 0x00ffffff

1053 #define PIPE_PIXEL_SHIFT 0

1054

1055 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)

1056 #define I915_CRC_ERROR_ENABLE (1UL<<29)

1057 #define I915_CRC_DONE_ENABLE (1UL<<28)

1058 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)

1059 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)

1060 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)

1061 #define I915_DPST_EVENT_ENABLE (1UL<<23)

1062 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)

1063 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)

1064 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)

1065 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */

1066 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)

1067 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)

1068 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)

1069 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)

1070 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)

1071 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)

1072 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)

1073 #define I915_DPST_EVENT_STATUS (1UL<<7)

1074 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)

1075 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)

1076 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)

1077 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */

1078 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)

1079 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)

1080

1081 #define SRX_INDEX 0x3c4

1082 #define SRX_DATA 0x3c5

1083 #define SR01 1

1084 #define SR01_SCREEN_OFF (1<<5)

1085

1086 #define PPCR 0x61204

1087 #define PPCR_ON (1<<0)

1088

1089 #define DVOB 0x61140

1090 #define DVOB_ON (1<<31)

1091 #define DVOC 0x61160

1092 #define DVOC_ON (1<<31)

1093 #define LVDS 0x61180

1094 #define LVDS_ON (1<<31)

1095

1096 #define ADPA 0x61100

1097 #define ADPA_DPMS_MASK (~(3<<10))

1098 #define ADPA_DPMS_ON (0<<10)

1099 #define ADPA_DPMS_SUSPEND (1<<10)

1100 #define ADPA_DPMS_STANDBY (2<<10)

1101 #define ADPA_DPMS_OFF (3<<10)

1102

1103 #define RING_TAIL 0x00

1104 #define TAIL_ADDR 0x001FFFF8

1105 #define RING_HEAD 0x04

1106 #define HEAD_WRAP_COUNT 0xFFE00000

1107 #define HEAD_WRAP_ONE 0x00200000

1108 #define HEAD_ADDR 0x001FFFFC

1109 #define RING_START 0x08

1110 #define START_ADDR 0xFFFFF000

1111 #define RING_LEN 0x0C

1112 #define RING_NR_PAGES 0x001FF000

1113 #define RING_REPORT_MASK 0x00000006

1114 #define RING_REPORT_64K 0x00000002

1115 #define RING_REPORT_128K 0x00000004

1116 #define RING_NO_REPORT 0x00000000

1117 #define RING_VALID_MASK 0x00000001

1118 #define RING_VALID 0x00000001

1119 #define RING_INVALID 0x00000000

1120

1121 /* Scratch pad debug 0 reg:

1122 */

1123 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000

1124 /*

1125 * The i830 generation, in LVDS mode, defines P1 as the bit number set within

1126 * this field (only one bit may be set).

1127 */

1128 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000

1129 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16

1130 /* i830, required in DVO non-gang */

1131 #define PLL_P2_DIVIDE_BY_4 (1 << 23)

1132 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */

1133 #define PLL_REF_INPUT_DREFCLK (0 << 13)

1134 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */

1135 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */

1136 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)

1137 #define PLL_REF_INPUT_MASK (3 << 13)

1138 #define PLL_LOAD_PULSE_PHASE_SHIFT 9

1139 /*

1140 * Parallel to Serial Load Pulse phase selection.

1141 * Selects the phase for the 10X DPLL clock for the PCIe

1142 * digital display port. The range is 4 to 13; 10 or more

1143 * is just a flip delay. The default is 6

1144 */

1145 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)

1146 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)

1147 /*

1148 * SDVO multiplier for 945G/GM. Not used on 965.

1149 */

1150 #define SDVO_MULTIPLIER_MASK 0x000000ff

1151 #define SDVO_MULTIPLIER_SHIFT_HIRES 4

1152 #define SDVO_MULTIPLIER_SHIFT_VGA 0

1153 #define DPLL_A_MD 0x0601c /* 965+ only */

1154 /*

1155 * UDI pixel divider, controlling how many pixels are stuffed into a packet.

1156 *

1157 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.

1158 */

1159 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000

1160 #define DPLL_MD_UDI_DIVIDER_SHIFT 24

1161 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */

1162 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000

1163 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16

1164 /*

1165 * SDVO/UDI pixel multiplier.

1166 *

1167 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus

1168 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate

1169 * modes, the bus rate would be below the limits, so SDVO allows for stuffing

1170 * dummy bytes in the datastream at an increased clock rate, with both sides of

1171 * the link knowing how many bytes are fill.

1172 *

1173 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock

1174 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be

1175 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and

1176 * through an SDVO command.

1177 *

1178 * This register field has values of multiplication factor minus 1, with

1179 * a maximum multiplier of 5 for SDVO.

1180 */

1181 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00

1182 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8

1183 /*

1184 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.

1185 * This best be set to the default value (3) or the CRT won't work. No,

1186 * I don't entirely understand what this does...

1187 */

1188 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f

1189 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0

1190 #define DPLL_B_MD 0x06020 /* 965+ only */

1191 #define FPA0 0x06040

1192 #define FPA1 0x06044

1193 #define FPB0 0x06048

1194 #define FPB1 0x0604c

1195 #define FP_N_DIV_MASK 0x003f0000

1196 #define FP_N_DIV_SHIFT 16

1197 #define FP_M1_DIV_MASK 0x00003f00

1198 #define FP_M1_DIV_SHIFT 8

1199 #define FP_M2_DIV_MASK 0x0000003f

1200 #define FP_M2_DIV_SHIFT 0

1201 #define DPLL_TEST 0x606c

1202 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)

1203 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)

1204 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)

1205 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)

1206 #define DPLLB_TEST_N_BYPASS (1 << 19)

1207 #define DPLLB_TEST_M_BYPASS (1 << 18)

1208 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)

1209 #define DPLLA_TEST_N_BYPASS (1 << 3)

1210 #define DPLLA_TEST_M_BYPASS (1 << 2)

1211 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)

1212 #define D_STATE 0x6104

1213 #define CG_2D_DIS 0x6200

1214 #define CG_3D_DIS 0x6204

1215

1216 /*

1217 * Palette regs

1218 */

1219

1220 #define PALETTE_A 0x0a000

1221 #define PALETTE_B 0x0a800

1222

1223 /*

1224 * Overlay regs

1225 */

1226

1227 #define OVADD 0x30000

1228 #define DOVSTA 0x30008

1229 #define OC_BUF (0x3<<20)

1230 #define OGAMC5 0x30010

1231 #define OGAMC4 0x30014

1232 #define OGAMC3 0x30018

1233 #define OGAMC2 0x3001c

1234 #define OGAMC1 0x30020

1235 #define OGAMC0 0x30024

1236

1237 /*

1238 * Display engine regs

1239 */

1240

1241 /* Pipe A timing regs */

1242 #define HTOTAL_A 0x60000

1243 #define HBLANK_A 0x60004

1244 #define HSYNC_A 0x60008

1245 #define VTOTAL_A 0x6000c

1246 #define VBLANK_A 0x60010

1247 #define VSYNC_A 0x60014

1248 #define PIPEASRC 0x6001c

1249 #define BCLRPAT_A 0x60020

1250

1251 /* Pipe B timing regs */

1252 #define HTOTAL_B 0x61000

1253 #define HBLANK_B 0x61004

1254 #define HSYNC_B 0x61008

1255 #define VTOTAL_B 0x6100c

1256 #define VBLANK_B 0x61010

1257 #define VSYNC_B 0x61014

1258 #define PIPEBSRC 0x6101c

1259 #define BCLRPAT_B 0x61020

1260

1261 /* VGA port control */

1262 #define ADPA 0x61100

1263 #define ADPA_DAC_ENABLE (1<<31)

1264 #define ADPA_DAC_DISABLE 0

1265 #define ADPA_PIPE_SELECT_MASK (1<<30)

1266 #define ADPA_PIPE_A_SELECT 0

1267 #define ADPA_PIPE_B_SELECT (1<<30)

1268 #define ADPA_USE_VGA_HVPOLARITY (1<<15)

1269 #define ADPA_SETS_HVPOLARITY 0

1270 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)

1271 #define ADPA_VSYNC_CNTL_ENABLE 0

1272 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)

1273 #define ADPA_HSYNC_CNTL_ENABLE 0

1274 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)

1275 #define ADPA_VSYNC_ACTIVE_LOW 0

1276 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)

1277 #define ADPA_HSYNC_ACTIVE_LOW 0

1278 #define ADPA_DPMS_MASK (~(3<<10))

1279 #define ADPA_DPMS_ON (0<<10)

1280 #define ADPA_DPMS_SUSPEND (1<<10)

1281 #define ADPA_DPMS_STANDBY (2<<10)

1282 #define ADPA_DPMS_OFF (3<<10)

1283

1284 /* Hotplug control (945+ only) */

1285 #define PORT_HOTPLUG_EN 0x61110

1286 #define SDVOB_HOTPLUG_INT_EN (1 << 26)

1287 #define SDVOC_HOTPLUG_INT_EN (1 << 25)

1288 #define TV_HOTPLUG_INT_EN (1 << 18)

1289 #define CRT_HOTPLUG_INT_EN (1 << 9)

1290 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)

1291

1292 #define PORT_HOTPLUG_STAT 0x61114

1293 #define CRT_HOTPLUG_INT_STATUS (1 << 11)

1294 #define TV_HOTPLUG_INT_STATUS (1 << 10)

1295 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)

1296 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)

1297 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)

1298 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)

1299 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)

1300 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)

1301

1302 /* SDVO port control */

1303 #define SDVOB 0x61140

1304 #define SDVOC 0x61160

1305 #define SDVO_ENABLE (1 << 31)

1306 #define SDVO_PIPE_B_SELECT (1 << 30)

1307 #define SDVO_STALL_SELECT (1 << 29)

1308 #define SDVO_INTERRUPT_ENABLE (1 << 26)

1309 /**

1310 * 915G/GM SDVO pixel multiplier.

1311 *

1312 * Programmed value is multiplier - 1, up to 5x.

1313 *

1314 * \sa DPLL_MD_UDI_MULTIPLIER_MASK

1315 */

1316 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)

1317 #define SDVO_PORT_MULTIPLY_SHIFT 23

1318 #define SDVO_PHASE_SELECT_MASK (15 << 19)

1319 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)

1320 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)

1321 #define SDVOC_GANG_MODE (1 << 16)

1322 #define SDVO_BORDER_ENABLE (1 << 7)

1323 #define SDVOB_PCIE_CONCURRENCY (1 << 3)

1324 #define SDVO_DETECTED (1 << 2)

1325 /* Bits to be preserved when writing */

1326 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))

1327 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))

1328

1329 /* DVO port control */

1330 #define DVOA 0x61120

1331 #define DVOB 0x61140

1332 #define DVOC 0x61160

1333 #define DVO_ENABLE (1 << 31)

1334 #define DVO_PIPE_B_SELECT (1 << 30)

1335 #define DVO_PIPE_STALL_UNUSED (0 << 28)

1336 #define DVO_PIPE_STALL (1 << 28)

1337 #define DVO_PIPE_STALL_TV (2 << 28)

1338 #define DVO_PIPE_STALL_MASK (3 << 28)

1339 #define DVO_USE_VGA_SYNC (1 << 15)

1340 #define DVO_DATA_ORDER_I740 (0 << 14)

1341 #define DVO_DATA_ORDER_FP (1 << 14)

1342 #define DVO_VSYNC_DISABLE (1 << 11)

1343 #define DVO_HSYNC_DISABLE (1 << 10)

1344 #define DVO_VSYNC_TRISTATE (1 << 9)

1345 #define DVO_HSYNC_TRISTATE (1 << 8)

1346 #define DVO_BORDER_ENABLE (1 << 7)

1347 #define DVO_DATA_ORDER_GBRG (1 << 6)

1348 #define DVO_DATA_ORDER_RGGB (0 << 6)

1349 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)

1350 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)

1351 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)

1352 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)

1353 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)

1354 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */

1355 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */

1356 #define DVO_PRESERVE_MASK (0x7<<24)

1357 #define DVOA_SRCDIM 0x61124

1358 #define DVOB_SRCDIM 0x61144

1359 #define DVOC_SRCDIM 0x61164

1360 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12

1361 #define DVO_SRCDIM_VERTICAL_SHIFT 0

1362

1363 /* LVDS port control */

1364 #define LVDS 0x61180

1365 /*

1366 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as

1367 * the DPLL semantics change when the LVDS is assigned to that pipe.

1368 */

1369 #define LVDS_PORT_EN (1 << 31)

1370 /* Selects pipe B for LVDS data. Must be set on pre-965. */

1371 #define LVDS_PIPEB_SELECT (1 << 30)

1372 /*

1373 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per

1374 * pixel.

1375 */

1376 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)

1377 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)

1378 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)

1379 /*

1380 * Controls the A3 data pair, which contains the additional LSBs for 24 bit

1381 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be

1382 * on.

1383 */

1384 #define LVDS_A3_POWER_MASK (3 << 6)

1385 #define LVDS_A3_POWER_DOWN (0 << 6)

1386 #define LVDS_A3_POWER_UP (3 << 6)

1387 /*

1388 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP

1389 * is set.

1390 */

1391 #define LVDS_CLKB_POWER_MASK (3 << 4)

1392 #define LVDS_CLKB_POWER_DOWN (0 << 4)

1393 #define LVDS_CLKB_POWER_UP (3 << 4)

1394 /*

1395 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2

1396 * setting for whether we are in dual-channel mode. The B3 pair will

1397 * additionally only be powered up when LVDS_A3_POWER_UP is set.

1398 */

1399 #define LVDS_B0B3_POWER_MASK (3 << 2)

1400 #define LVDS_B0B3_POWER_DOWN (0 << 2)

1401 #define LVDS_B0B3_POWER_UP (3 << 2)

1402

1403 /* Panel power sequencing */

1404 #define PP_STATUS 0x61200

1405 #define PP_ON (1 << 31)

1406 /*

1407 * Indicates that all dependencies of the panel are on:

1408 *

1409 * - PLL enabled

1410 * - pipe enabled

1411 * - LVDS/DVOB/DVOC on

1412 */

1413 #define PP_READY (1 << 30)

1414 #define PP_SEQUENCE_NONE (0 << 28)

1415 #define PP_SEQUENCE_ON (1 << 28)

1416 #define PP_SEQUENCE_OFF (2 << 28)

1417 #define PP_SEQUENCE_MASK 0x30000000

1418 #define PP_CONTROL 0x61204

1419 #define POWER_TARGET_ON (1 << 0)

1420 #define PP_ON_DELAYS 0x61208

1421 #define PP_OFF_DELAYS 0x6120c

1422 #define PP_DIVISOR 0x61210

1423

1424 /* Panel fitting */

1425 #define PFIT_CONTROL 0x61230

1426 #define PFIT_ENABLE (1 << 31)

1427 #define PFIT_PIPE_MASK (3 << 29)

1428 #define PFIT_PIPE_SHIFT 29

1429 #define VERT_INTERP_DISABLE (0 << 10)

1430 #define VERT_INTERP_BILINEAR (1 << 10)

1431 #define VERT_INTERP_MASK (3 << 10)

1432 #define VERT_AUTO_SCALE (1 << 9)

1433 #define HORIZ_INTERP_DISABLE (0 << 6)

1434 #define HORIZ_INTERP_BILINEAR (1 << 6)

1435 #define HORIZ_INTERP_MASK (3 << 6)

1436 #define HORIZ_AUTO_SCALE (1 << 5)

1437 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)

1438 #define PFIT_PGM_RATIOS 0x61234

1439 #define PFIT_VERT_SCALE_MASK 0xfff00000

1440 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0

1441 #define PFIT_AUTO_RATIOS 0x61238

1442

1443 /* Backlight control */

1444 #define BLC_PWM_CTL 0x61254

1445 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)

1446 #define BLC_PWM_CTL2 0x61250 /* 965+ only */

1447 /*

1448 * This is the most significant 15 bits of the number of backlight cycles in a

1449 * complete cycle of the modulated backlight control.

1450 *

1451 * The actual value is this field multiplied by two.

1452 */

1453 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)

1454 #define BLM_LEGACY_MODE (1 << 16)

1455 /*

1456 * This is the number of cycles out of the backlight modulation cycle for which

1457 * the backlight is on.

1458 *

1459 * This field must be no greater than the number of cycles in the complete

1460 * backlight modulation cycle.

1461 */

1462 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)

1463 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)

1464

1465 /* TV port control */

1466 #define TV_CTL 0x68000

1467 /** Enables the TV encoder */

1468 # define TV_ENC_ENABLE (1 << 31)

1469 /** Sources the TV encoder input from pipe B instead of A. */

1470 # define TV_ENC_PIPEB_SELECT (1 << 30)

1471 /** Outputs composite video (DAC A only) */

1472 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)

1473 /** Outputs SVideo video (DAC B/C) */

1474 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)

1475 /** Outputs Component video (DAC A/B/C) */

1476 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)

1477 /** Outputs Composite and SVideo (DAC A/B/C) */

1478 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)

1479 # define TV_TRILEVEL_SYNC (1 << 21)

1480 /** Enables slow sync generation (945GM only) */

1481 # define TV_SLOW_SYNC (1 << 20)

1482 /** Selects 4x oversampling for 480i and 576p */

1483 # define TV_OVERSAMPLE_4X (0 << 18)

1484 /** Selects 2x oversampling for 720p and 1080i */

1485 # define TV_OVERSAMPLE_2X (1 << 18)

1486 /** Selects no oversampling for 1080p */

1487 # define TV_OVERSAMPLE_NONE (2 << 18)

1488 /** Selects 8x oversampling */

1489 # define TV_OVERSAMPLE_8X (3 << 18)

1490 /** Selects progressive mode rather than interlaced */

1491 # define TV_PROGRESSIVE (1 << 17)

1492 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */

1493 # define TV_PAL_BURST (1 << 16)

1494 /** Field for setting delay of Y compared to C */

1495 # define TV_YC_SKEW_MASK (7 << 12)

1496 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */

1497 # define TV_ENC_SDP_FIX (1 << 11)

1498 /**

1499 * Enables a fix for the 915GM only.

1500 *

1501 * Not sure what it does.

1502 */

1503 # define TV_ENC_C0_FIX (1 << 10)

1504 /** Bits that must be preserved by software */

1505 # define TV_CTL_SAVE ((3 << 8) | (3 << 6))

1506 # define TV_FUSE_STATE_MASK (3 << 4)

1507 /** Read-only state that reports all features enabled */

1508 # define TV_FUSE_STATE_ENABLED (0 << 4)

1509 /** Read-only state that reports that Macrovision is disabled in hardware*/

1510 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)

1511 /** Read-only state that reports that TV-out is disabled in hardware. */

1512 # define TV_FUSE_STATE_DISABLED (2 << 4)

1513 /** Normal operation */

1514 # define TV_TEST_MODE_NORMAL (0 << 0)

1515 /** Encoder test pattern 1 - combo pattern */

1516 # define TV_TEST_MODE_PATTERN_1 (1 << 0)

1517 /** Encoder test pattern 2 - full screen vertical 75% color bars */

1518 # define TV_TEST_MODE_PATTERN_2 (2 << 0)

1519 /** Encoder test pattern 3 - full screen horizontal 75% color bars */

1520 # define TV_TEST_MODE_PATTERN_3 (3 << 0)

1521 /** Encoder test pattern 4 - random noise */

1522 # define TV_TEST_MODE_PATTERN_4 (4 << 0)

1523 /** Encoder test pattern 5 - linear color ramps */

1524 # define TV_TEST_MODE_PATTERN_5 (5 << 0)

1525 /**

1526 * This test mode forces the DACs to 50% of full output.

1527 *

1528 * This is used for load detection in combination with TVDAC_SENSE_MASK

1529 */

1530 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)

1531 # define TV_TEST_MODE_MASK (7 << 0)

1532

1533 #define TV_DAC 0x68004

1534 /**

1535 * Reports that DAC state change logic has reported change (RO).

1536 *

1537 * This gets cleared when TV_DAC_STATE_EN is cleared

1538 */

1539 # define TVDAC_STATE_CHG (1 << 31)

1540 # define TVDAC_SENSE_MASK (7 << 28)

1541 /** Reports that DAC A voltage is above the detect threshold */

1542 # define TVDAC_A_SENSE (1 << 30)

1543 /** Reports that DAC B voltage is above the detect threshold */

1544 # define TVDAC_B_SENSE (1 << 29)

1545 /** Reports that DAC C voltage is above the detect threshold */

1546 # define TVDAC_C_SENSE (1 << 28)

1547 /**

1548 * Enables DAC state detection logic, for load-based TV detection.

1549 *

1550 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set

1551 * to off, for load detection to work.

1552 */

1553 # define TVDAC_STATE_CHG_EN (1 << 27)

1554 /** Sets the DAC A sense value to high */

1555 # define TVDAC_A_SENSE_CTL (1 << 26)

1556 /** Sets the DAC B sense value to high */

1557 # define TVDAC_B_SENSE_CTL (1 << 25)

1558 /** Sets the DAC C sense value to high */

1559 # define TVDAC_C_SENSE_CTL (1 << 24)

1560 /** Overrides the ENC_ENABLE and DAC voltage levels */

1561 # define DAC_CTL_OVERRIDE (1 << 7)

1562 /** Sets the slew rate. Must be preserved in software */

1563 # define ENC_TVDAC_SLEW_FAST (1 << 6)

1564 # define DAC_A_1_3_V (0 << 4)

1565 # define DAC_A_1_1_V (1 << 4)

1566 # define DAC_A_0_7_V (2 << 4)

1567 # define DAC_A_OFF (3 << 4)

1568 # define DAC_B_1_3_V (0 << 2)

1569 # define DAC_B_1_1_V (1 << 2)

1570 # define DAC_B_0_7_V (2 << 2)

1571 # define DAC_B_OFF (3 << 2)

1572 # define DAC_C_1_3_V (0 << 0)

1573 # define DAC_C_1_1_V (1 << 0)

1574 # define DAC_C_0_7_V (2 << 0)

1575 # define DAC_C_OFF (3 << 0)

1576

1577 /**

1578 * CSC coefficients are stored in a floating point format with 9 bits of

1579 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,

1580 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with

1581 * -1 (0x3) being the only legal negative value.

1582 */

1583 #define TV_CSC_Y 0x68010

1584 # define TV_RY_MASK 0x07ff0000

1585 # define TV_RY_SHIFT 16

1586 # define TV_GY_MASK 0x00000fff

1587 # define TV_GY_SHIFT 0

1588

1589 #define TV_CSC_Y2 0x68014

1590 # define TV_BY_MASK 0x07ff0000

1591 # define TV_BY_SHIFT 16

1592 /**

1593 * Y attenuation for component video.

1594 *

1595 * Stored in 1.9 fixed point.

1596 */

1597 # define TV_AY_MASK 0x000003ff

1598 # define TV_AY_SHIFT 0

1599

1600 #define TV_CSC_U 0x68018

1601 # define TV_RU_MASK 0x07ff0000

1602 # define TV_RU_SHIFT 16

1603 # define TV_GU_MASK 0x000007ff

1604 # define TV_GU_SHIFT 0

1605

1606 #define TV_CSC_U2 0x6801c

1607 # define TV_BU_MASK 0x07ff0000

1608 # define TV_BU_SHIFT 16

1609 /**

1610 * U attenuation for component video.

1611 *

1612 * Stored in 1.9 fixed point.

1613 */

1614 # define TV_AU_MASK 0x000003ff

1615 # define TV_AU_SHIFT 0

1616

1617 #define TV_CSC_V 0x68020

1618 # define TV_RV_MASK 0x0fff0000

1619 # define TV_RV_SHIFT 16

1620 # define TV_GV_MASK 0x000007ff

1621 # define TV_GV_SHIFT 0

1622

1623 #define TV_CSC_V2 0x68024

1624 # define TV_BV_MASK 0x07ff0000

1625 # define TV_BV_SHIFT 16

1626 /**

1627 * V attenuation for component video.

1628 *

1629 * Stored in 1.9 fixed point.

1630 */

1631 # define TV_AV_MASK 0x000007ff

1632 # define TV_AV_SHIFT 0

1633

1634 #define TV_CLR_KNOBS 0x68028

1635 /** 2s-complement brightness adjustment */

1636 # define TV_BRIGHTNESS_MASK 0xff000000

1637 # define TV_BRIGHTNESS_SHIFT 24

1638 /** Contrast adjustment, as a 2.6 unsigned floating point number */

1639 # define TV_CONTRAST_MASK 0x00ff0000

1640 # define TV_CONTRAST_SHIFT 16

1641 /** Saturation adjustment, as a 2.6 unsigned floating point number */

1642 # define TV_SATURATION_MASK 0x0000ff00

1643 # define TV_SATURATION_SHIFT 8

1644 /** Hue adjustment, as an integer phase angle in degrees */

1645 # define TV_HUE_MASK 0x000000ff

1646 # define TV_HUE_SHIFT 0

1647

1648 #define TV_CLR_LEVEL 0x6802c

1649 /** Controls the DAC level for black */

1650 # define TV_BLACK_LEVEL_MASK 0x01ff0000

1651 # define TV_BLACK_LEVEL_SHIFT 16

1652 /** Controls the DAC level for blanking */

1653 # define TV_BLANK_LEVEL_MASK 0x000001ff

1654 # define TV_BLANK_LEVEL_SHIFT 0

1655

1656 #define TV_H_CTL_1 0x68030

1657 /** Number of pixels in the hsync. */

1658 # define TV_HSYNC_END_MASK 0x1fff0000

1659 # define TV_HSYNC_END_SHIFT 16

1660 /** Total number of pixels minus one in the line (display and blanking). */

1661 # define TV_HTOTAL_MASK 0x00001fff

1662 # define TV_HTOTAL_SHIFT 0

1663

1664 #define TV_H_CTL_2 0x68034

1665 /** Enables the colorburst (needed for non-component color) */

1666 # define TV_BURST_ENA (1 << 31)

1667 /** Offset of the colorburst from the start of hsync, in pixels minus one. */

1668 # define TV_HBURST_START_SHIFT 16

1669 # define TV_HBURST_START_MASK 0x1fff0000

1670 /** Length of the colorburst */

1671 # define TV_HBURST_LEN_SHIFT 0

1672 # define TV_HBURST_LEN_MASK 0x0001fff

1673

1674 #define TV_H_CTL_3 0x68038

1675 /** End of hblank, measured in pixels minus one from start of hsync */

1676 # define TV_HBLANK_END_SHIFT 16

1677 # define TV_HBLANK_END_MASK 0x1fff0000

1678 /** Start of hblank, measured in pixels minus one from start of hsync */

1679 # define TV_HBLANK_START_SHIFT 0

1680 # define TV_HBLANK_START_MASK 0x0001fff

1681

1682 #define TV_V_CTL_1 0x6803c

1683 /** XXX */

1684 # define TV_NBR_END_SHIFT 16

1685 # define TV_NBR_END_MASK 0x07ff0000

1686 /** XXX */

1687 # define TV_VI_END_F1_SHIFT 8

1688 # define TV_VI_END_F1_MASK 0x00003f00

1689 /** XXX */

1690 # define TV_VI_END_F2_SHIFT 0

1691 # define TV_VI_END_F2_MASK 0x0000003f

1692

1693 #define TV_V_CTL_2 0x68040

1694 /** Length of vsync, in half lines */

1695 # define TV_VSYNC_LEN_MASK 0x07ff0000

1696 # define TV_VSYNC_LEN_SHIFT 16

1697 /** Offset of the start of vsync in field 1, measured in one less than the

1698 * number of half lines.

1699 */

1700 # define TV_VSYNC_START_F1_MASK 0x00007f00

1701 # define TV_VSYNC_START_F1_SHIFT 8

1702 /**

1703 * Offset of the start of vsync in field 2, measured in one less than the

1704 * number of half lines.

1705 */

1706 # define TV_VSYNC_START_F2_MASK 0x0000007f

1707 # define TV_VSYNC_START_F2_SHIFT 0

1708

1709 #define TV_V_CTL_3 0x68044

1710 /** Enables generation of the equalization signal */

1711 # define TV_EQUAL_ENA (1 << 31)

1712 /** Length of vsync, in half lines */

1713 # define TV_VEQ_LEN_MASK 0x007f0000

1714 # define TV_VEQ_LEN_SHIFT 16

1715 /** Offset of the start of equalization in field 1, measured in one less than

1716 * the number of half lines.

1717 */

1718 # define TV_VEQ_START_F1_MASK 0x0007f00

1719 # define TV_VEQ_START_F1_SHIFT 8

1720 /**

1721 * Offset of the start of equalization in field 2, measured in one less than

1722 * the number of half lines.

1723 */

1724 # define TV_VEQ_START_F2_MASK 0x000007f

1725 # define TV_VEQ_START_F2_SHIFT 0

1726

1727 #define TV_V_CTL_4 0x68048

1728 /**

1729 * Offset to start of vertical colorburst, measured in one less than the

1730 * number of lines from vertical start.

1731 */

1732 # define TV_VBURST_START_F1_MASK 0x003f0000

1733 # define TV_VBURST_START_F1_SHIFT 16

1734 /**

1735 * Offset to the end of vertical colorburst, measured in one less than the

1736 * number of lines from the start of NBR.

1737 */

1738 # define TV_VBURST_END_F1_MASK 0x000000ff

1739 # define TV_VBURST_END_F1_SHIFT 0

1740

1741 #define TV_V_CTL_5 0x6804c

1742 /**

1743 * Offset to start of vertical colorburst, measured in one less than the

1744 * number of lines from vertical start.

1745 */

1746 # define TV_VBURST_START_F2_MASK 0x003f0000

1747 # define TV_VBURST_START_F2_SHIFT 16

1748 /**

1749 * Offset to the end of vertical colorburst, measured in one less than the

1750 * number of lines from the start of NBR.

1751 */

1752 # define TV_VBURST_END_F2_MASK 0x000000ff

1753 # define TV_VBURST_END_F2_SHIFT 0

1754

1755 #define TV_V_CTL_6 0x68050

1756 /**

1757 * Offset to start of vertical colorburst, measured in one less than the

1758 * number of lines from vertical start.

1759 */

1760 # define TV_VBURST_START_F3_MASK 0x003f0000

1761 # define TV_VBURST_START_F3_SHIFT 16

1762 /**

1763 * Offset to the end of vertical colorburst, measured in one less than the

1764 * number of lines from the start of NBR.

1765 */

1766 # define TV_VBURST_END_F3_MASK 0x000000ff

1767 # define TV_VBURST_END_F3_SHIFT 0

1768

1769 #define TV_V_CTL_7 0x68054

1770 /**

1771 * Offset to start of vertical colorburst, measured in one less than the

1772 * number of lines from vertical start.

1773 */

1774 # define TV_VBURST_START_F4_MASK 0x003f0000

1775 # define TV_VBURST_START_F4_SHIFT 16

1776 /**

1777 * Offset to the end of vertical colorburst, measured in one less than the

1778 * number of lines from the start of NBR.

1779 */

1780 # define TV_VBURST_END_F4_MASK 0x000000ff

1781 # define TV_VBURST_END_F4_SHIFT 0

1782

1783 #define TV_SC_CTL_1 0x68060

1784 /** Turns on the first subcarrier phase generation DDA */

1785 # define TV_SC_DDA1_EN (1 << 31)

1786 /** Turns on the first subcarrier phase generation DDA */

1787 # define TV_SC_DDA2_EN (1 << 30)

1788 /** Turns on the first subcarrier phase generation DDA */

1789 # define TV_SC_DDA3_EN (1 << 29)

1790 /** Sets the subcarrier DDA to reset frequency every other field */

1791 # define TV_SC_RESET_EVERY_2 (0 << 24)

1792 /** Sets the subcarrier DDA to reset frequency every fourth field */

1793 # define TV_SC_RESET_EVERY_4 (1 << 24)

1794 /** Sets the subcarrier DDA to reset frequency every eighth field */

1795 # define TV_SC_RESET_EVERY_8 (2 << 24)

1796 /** Sets the subcarrier DDA to never reset the frequency */

1797 # define TV_SC_RESET_NEVER (3 << 24)

1798 /** Sets the peak amplitude of the colorburst.*/

1799 # define TV_BURST_LEVEL_MASK 0x00ff0000

1800 # define TV_BURST_LEVEL_SHIFT 16

1801 /** Sets the increment of the first subcarrier phase generation DDA */

1802 # define TV_SCDDA1_INC_MASK 0x00000fff

1803 # define TV_SCDDA1_INC_SHIFT 0

1804

1805 #define TV_SC_CTL_2 0x68064

1806 /** Sets the rollover for the second subcarrier phase generation DDA */

1807 # define TV_SCDDA2_SIZE_MASK 0x7fff0000

1808 # define TV_SCDDA2_SIZE_SHIFT 16

1809 /** Sets the increent of the second subcarrier phase generation DDA */

1810 # define TV_SCDDA2_INC_MASK 0x00007fff

1811 # define TV_SCDDA2_INC_SHIFT 0

1812

1813 #define TV_SC_CTL_3 0x68068

1814 /** Sets the rollover for the third subcarrier phase generation DDA */

1815 # define TV_SCDDA3_SIZE_MASK 0x7fff0000

1816 # define TV_SCDDA3_SIZE_SHIFT 16

1817 /** Sets the increent of the third subcarrier phase generation DDA */

1818 # define TV_SCDDA3_INC_MASK 0x00007fff

1819 # define TV_SCDDA3_INC_SHIFT 0

1820

1821 #define TV_WIN_POS 0x68070

1822 /** X coordinate of the display from the start of horizontal active */

1823 # define TV_XPOS_MASK 0x1fff0000

1824 # define TV_XPOS_SHIFT 16

1825 /** Y coordinate of the display from the start of vertical active (NBR) */

1826 # define TV_YPOS_MASK 0x00000fff

1827 # define TV_YPOS_SHIFT 0

1828

1829 #define TV_WIN_SIZE 0x68074

1830 /** Horizontal size of the display window, measured in pixels*/

1831 # define TV_XSIZE_MASK 0x1fff0000

1832 # define TV_XSIZE_SHIFT 16

1833 /**

1834 * Vertical size of the display window, measured in pixels.

1835 *

1836 * Must be even for interlaced modes.

1837 */

1838 # define TV_YSIZE_MASK 0x00000fff

1839 # define TV_YSIZE_SHIFT 0

1840

1841 #define TV_FILTER_CTL_1 0x68080

1842 /**

1843 * Enables automatic scaling calculation.

1844 *

1845 * If set, the rest of the registers are ignored, and the calculated values can

1846 * be read back from the register.

1847 */

1848 # define TV_AUTO_SCALE (1 << 31)

1849 /**

1850 * Disables the vertical filter.

1851 *

1852 * This is required on modes more than 1024 pixels wide */

1853 # define TV_V_FILTER_BYPASS (1 << 29)

1854 /** Enables adaptive vertical filtering */

1855 # define TV_VADAPT (1 << 28)

1856 # define TV_VADAPT_MODE_MASK (3 << 26)

1857 /** Selects the least adaptive vertical filtering mode */

1858 # define TV_VADAPT_MODE_LEAST (0 << 26)

1859 /** Selects the moderately adaptive vertical filtering mode */

1860 # define TV_VADAPT_MODE_MODERATE (1 << 26)

1861 /** Selects the most adaptive vertical filtering mode */

1862 # define TV_VADAPT_MODE_MOST (3 << 26)

1863 /**

1864 * Sets the horizontal scaling factor.

1865 *

1866 * This should be the fractional part of the horizontal scaling factor divided

1867 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:

1868 *

1869 * (src width - 1) / ((oversample * dest width) - 1)

1870 */

1871 # define TV_HSCALE_FRAC_MASK 0x00003fff

1872 # define TV_HSCALE_FRAC_SHIFT 0

1873

1874 #define TV_FILTER_CTL_2 0x68084

1875 /**

1876 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.

1877 *

1878 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)

1879 */

1880 # define TV_VSCALE_INT_MASK 0x00038000

1881 # define TV_VSCALE_INT_SHIFT 15

1882 /**

1883 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.

1884 *

1885 * \sa TV_VSCALE_INT_MASK

1886 */

1887 # define TV_VSCALE_FRAC_MASK 0x00007fff

1888 # define TV_VSCALE_FRAC_SHIFT 0

1889

1890 #define TV_FILTER_CTL_3 0x68088

1891 /**

1892 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.

1893 *

1894 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))

1895 *

1896 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.

1897 */

1898 # define TV_VSCALE_IP_INT_MASK 0x00038000

1899 # define TV_VSCALE_IP_INT_SHIFT 15

1900 /**

1901 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.

1902 *

1903 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.

1904 *

1905 * \sa TV_VSCALE_IP_INT_MASK

1906 */

1907 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff

1908 # define TV_VSCALE_IP_FRAC_SHIFT 0

1909

1910 #define TV_CC_CONTROL 0x68090

1911 # define TV_CC_ENABLE (1 << 31)

1912 /**

1913 * Specifies which field to send the CC data in.

1914 *

1915 * CC data is usually sent in field 0.

1916 */

1917 # define TV_CC_FID_MASK (1 << 27)

1918 # define TV_CC_FID_SHIFT 27

1919 /** Sets the horizontal position of the CC data. Usually 135. */

1920 # define TV_CC_HOFF_MASK 0x03ff0000

1921 # define TV_CC_HOFF_SHIFT 16

1922 /** Sets the vertical position of the CC data. Usually 21 */

1923 # define TV_CC_LINE_MASK 0x0000003f

1924 # define TV_CC_LINE_SHIFT 0

1925

1926 #define TV_CC_DATA 0x68094

1927 # define TV_CC_RDY (1 << 31)

1928 /** Second word of CC data to be transmitted. */

1929 # define TV_CC_DATA_2_MASK 0x007f0000

1930 # define TV_CC_DATA_2_SHIFT 16

1931 /** First word of CC data to be transmitted. */

1932 # define TV_CC_DATA_1_MASK 0x0000007f

1933 # define TV_CC_DATA_1_SHIFT 0

1934

1935 #define TV_H_LUMA_0 0x68100

1936 #define TV_H_LUMA_59 0x681ec

1937 #define TV_H_CHROMA_0 0x68200

1938 #define TV_H_CHROMA_59 0x682ec

1939 #define TV_V_LUMA_0 0x68300

1940 #define TV_V_LUMA_42 0x683a8

1941 #define TV_V_CHROMA_0 0x68400

1942 #define TV_V_CHROMA_42 0x684a8

1943

1944 /* Display & cursor control */

1945

1946 /* Pipe A */

1947 #define PIPEADSL 0x70000

1948 #define PIPEACONF 0x70008

1949 #define PIPEACONF_ENABLE (1<<31)

1950 #define PIPEACONF_DISABLE 0

1951 #define PIPEACONF_DOUBLE_WIDE (1<<30)

1952 #define I965_PIPECONF_ACTIVE (1<<30)

1953 #define PIPEACONF_SINGLE_WIDE 0

1954 #define PIPEACONF_PIPE_UNLOCKED 0

1955 #define PIPEACONF_PIPE_LOCKED (1<<25)

1956 #define PIPEACONF_PALETTE 0

1957 #define PIPEACONF_GAMMA (1<<24)

1958 #define PIPECONF_FORCE_BORDER (1<<25)

1959 #define PIPECONF_PROGRESSIVE (0 << 21)

1960 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)

1961 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)

1962 #define PIPEASTAT 0x70024

1963 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)

1964 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)

1965 #define PIPE_CRC_DONE_ENABLE (1UL<<28)

1966 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)

1967 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)

1968 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)

1969 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)

1970 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)

1971 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)

1972 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)

1973 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)

1974 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */

1975 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */

1976 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)

1977 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)

1978 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)

1979 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)

1980 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)

1981 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)

1982 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)

1983 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)

1984 #define PIPE_DPST_EVENT_STATUS (1UL<<7)

1985 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)

1986 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)

1987 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)

1988 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */

1989 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */

1990 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)

1991 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)

1992

1993 #define DSPARB 0x70030

1994 #define DSPARB_CSTART_MASK (0x7f << 7)

1995 #define DSPARB_CSTART_SHIFT 7

1996 #define DSPARB_BSTART_MASK (0x7f)

1997 #define DSPARB_BSTART_SHIFT 0

1998 /*

1999 * The two pipe frame counter registers are not synchronized, so

2000 * reading a stable value is somewhat tricky. The following code

2001 * should work:

2002 *

2003 * do {

2004 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>

2005 * PIPE_FRAME_HIGH_SHIFT;

2006 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>

2007 * PIPE_FRAME_LOW_SHIFT);

2008 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>

2009 * PIPE_FRAME_HIGH_SHIFT);

2010 * } while (high1 != high2);

2011 * frame = (high1 << 8) | low1;

2012 */

2013 #define PIPEAFRAMEHIGH 0x70040

2014 #define PIPE_FRAME_HIGH_MASK 0x0000ffff

2015 #define PIPE_FRAME_HIGH_SHIFT 0

2016 #define PIPEAFRAMEPIXEL 0x70044

2017 #define PIPE_FRAME_LOW_MASK 0xff000000

2018 #define PIPE_FRAME_LOW_SHIFT 24

2019 #define PIPE_PIXEL_MASK 0x00ffffff

2020 #define PIPE_PIXEL_SHIFT 0

2021

2022 /* Cursor A & B regs */

2023 #define CURACNTR 0x70080

2024 #define CURSOR_MODE_DISABLE 0x00

2025 #define CURSOR_MODE_64_32B_AX 0x07

2026 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)

2027 #define MCURSOR_GAMMA_ENABLE (1 << 26)

2028 #define CURABASE 0x70084

2029 #define CURAPOS 0x70088

2030 #define CURSOR_POS_MASK 0x007FF

2031 #define CURSOR_POS_SIGN 0x8000

2032 #define CURSOR_X_SHIFT 0

2033 #define CURSOR_Y_SHIFT 16

2034 #define CURBCNTR 0x700c0

2035 #define CURBBASE 0x700c4

2036 #define CURBPOS 0x700c8

2037

2038 /* Display A control */

2039 #define DSPACNTR 0x70180

2040 #define DISPLAY_PLANE_ENABLE (1<<31)

2041 #define DISPLAY_PLANE_DISABLE 0

2042 #define DISPPLANE_GAMMA_ENABLE (1<<30)

2043 #define DISPPLANE_GAMMA_DISABLE 0

2044 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)

2045 #define DISPPLANE_8BPP (0x2<<26)

2046 #define DISPPLANE_15_16BPP (0x4<<26)

2047 #define DISPPLANE_16BPP (0x5<<26)

2048 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)

2049 #define DISPPLANE_32BPP (0x7<<26)

2050 #define DISPPLANE_STEREO_ENABLE (1<<25)

2051 #define DISPPLANE_STEREO_DISABLE 0

2052 #define DISPPLANE_SEL_PIPE_MASK (1<<24)

2053 #define DISPPLANE_SEL_PIPE_A 0

2054 #define DISPPLANE_SEL_PIPE_B (1<<24)

2055 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)

2056 #define DISPPLANE_SRC_KEY_DISABLE 0

2057 #define DISPPLANE_LINE_DOUBLE (1<<20)

2058 #define DISPPLANE_NO_LINE_DOUBLE 0

2059 #define DISPPLANE_STEREO_POLARITY_FIRST 0

2060 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)

2061 #define DSPAADDR 0x70184

2062 #define DSPASTRIDE 0x70188

2063 #define DSPAPOS 0x7018C /* reserved */

2064 #define DSPASIZE 0x70190

2065 #define DSPASURF 0x7019C /* 965+ only */

2066 #define DSPATILEOFF 0x701A4 /* 965+ only */

2067

2068 /* VBIOS flags */

2069 #define SWF00 0x71410

2070 #define SWF01 0x71414

2071 #define SWF02 0x71418

2072 #define SWF03 0x7141c

2073 #define SWF04 0x71420

2074 #define SWF05 0x71424

2075 #define SWF06 0x71428

2076 #define SWF10 0x70410

2077 #define SWF11 0x70414

2078 #define SWF14 0x71420

2079 #define SWF30 0x72414

2080 #define SWF31 0x72418

2081 #define SWF32 0x7241c

2082

2083 /* Pipe B */

2084 #define PIPEBDSL 0x71000

2085 #define PIPEBCONF 0x71008

2086 #define PIPEBSTAT 0x71024

2087 #define PIPEBFRAMEHIGH 0x71040

2088 #define PIPEBFRAMEPIXEL 0x71044

2089

2090 /* Display B control */

2091 #define DSPBCNTR 0x71180

2092 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)

2093 #define DISPPLANE_ALPHA_TRANS_DISABLE 0

2094 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0

2095 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)

2096 #define DSPBADDR 0x71184

2097 #define DSPBSTRIDE 0x71188

2098 #define DSPBPOS 0x7118C

2099 #define DSPBSIZE 0x71190

2100 #define DSPBSURF 0x7119C

2101 #define DSPBTILEOFF 0x711A4

2102

2103 /* VBIOS regs */

2104 #define VGACNTRL 0x71400

2105 # define VGA_DISP_DISABLE (1 << 31)

2106 # define VGA_2X_MODE (1 << 30)

2107 # define VGA_PIPE_B_SELECT (1 << 29)

2108

2109 /* Chipset type macros */

2110

2111 #define IS_I830(dev) ((dev)->pci_device == 0x3577)

2112 #define IS_845G(dev) ((dev)->pci_device == 0x2562)

2113 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)

2114 #define IS_I855(dev) ((dev)->pci_device == 0x3582)

2115 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)

2116

2117 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)

2118 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)

2119 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)

2120 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\

2121 (dev)->pci_device == 0x27AE)

2122 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \

2123 (dev)->pci_device == 0x2982 || \

2124 (dev)->pci_device == 0x2992 || \

2125 (dev)->pci_device == 0x29A2 || \

2126 (dev)->pci_device == 0x2A02 || \

2127 (dev)->pci_device == 0x2A12 || \

2128 (dev)->pci_device == 0x2A42 || \

2129 (dev)->pci_device == 0x2E02 || \

2130 (dev)->pci_device == 0x2E12 || \

2131 (dev)->pci_device == 0x2E22)

2132

2133 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)

2134

2135 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)

2136

2137 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \

2138 (dev)->pci_device == 0x2E12 || \

2139 (dev)->pci_device == 0x2E22)

2140

2141 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \

2142 (dev)->pci_device == 0x29B2 || \

2143 (dev)->pci_device == 0x29D2)

2144

2145 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \

2146 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))

2147

2148 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \

2149 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))

2150

2151 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))

2152

2153 #endif