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1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-

2 */

3 /*

4 *

7 *

8 * Permission is hereby granted, free of charge, to any person obtaining a

9 * copy of this software and associated documentation files (the

10 * "Software"), to deal in the Software without restriction, including

11 * without limitation the rights to use, copy, modify, merge, publish,

12 * distribute, sub license, and/or sell copies of the Software, and to

13 * permit persons to whom the Software is furnished to do so, subject to

14 * the following conditions:

15 *

16 * The above copyright notice and this permission notice (including the

17 * next paragraph) shall be included in all copies or substantial portions

18 * of the Software.

19 *

20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

27 *

28 */

29

30 #ifndef _I915_DRV_H_

31 #define _I915_DRV_H_

32

33 /* General customization:

34 */

35

36 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."

37

38 #define DRIVER_NAME "i915"

39 #define DRIVER_DESC "Intel Graphics"

40 #define DRIVER_DATE "20070209"

41

42 #if defined(__linux__)

43 #define I915_HAVE_FENCE

44 #define I915_HAVE_BUFFER

45 #endif

46

47 /* Interface history:

48 *

49 * 1.1: Original.

50 * 1.2: Add Power Management

51 * 1.3: Add vblank support

52 * 1.4: Fix cmdbuffer path, add heap destroy

53 * 1.5: Add vblank pipe configuration

54 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank

55 * - Support vertical blank on secondary display pipe

56 * 1.8: New ioctl for ARB_Occlusion_Query

57 * 1.9: Usable page flipping and triple buffering

58 */

59 #define DRIVER_MAJOR 1

60 #if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER)

61 #define DRIVER_MINOR 9

62 #else

63 #define DRIVER_MINOR 6

64 #endif

65 #define DRIVER_PATCHLEVEL 0

66

67 typedef struct _drm_i915_ring_buffer {

68 int tail_mask;

69 unsigned long Start;

70 unsigned long End;

71 unsigned long Size;

72 u8 *virtual_start;

73 int head;

74 int tail;

75 int space;

76 drm_local_map_t map;

77 } drm_i915_ring_buffer_t;

78

79 struct mem_block {

80 struct mem_block *next;

81 struct mem_block *prev;

82 int start;

83 int size;

84 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */

85 };

86

87 typedef struct _drm_i915_vbl_swap {

88 struct list_head head;

89 drm_drawable_t drw_id;

90 unsigned int pipe;

91 unsigned int sequence;

92 int flip;

93 } drm_i915_vbl_swap_t;

94

95 typedef struct drm_i915_private {

96 drm_local_map_t *sarea;

97 drm_local_map_t *mmio_map;

98

99 drm_i915_sarea_t *sarea_priv;

100 drm_i915_ring_buffer_t ring;

101

102 drm_dma_handle_t *status_page_dmah;

103 void *hw_status_page;

104 dma_addr_t dma_status_page;

105 uint32_t counter;

106 unsigned int status_gfx_addr;

107 drm_local_map_t hws_map;

108

109 unsigned int cpp;

110 int use_mi_batchbuffer_start;

111

112 wait_queue_head_t irq_queue;

113 atomic_t irq_received;

114 atomic_t irq_emitted;

115

116 int tex_lru_log_granularity;

117 int allow_batchbuffer;

118 struct mem_block *agp_heap;

119 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;

120 int vblank_pipe;

121 DRM_SPINTYPE user_irq_lock;

122 int user_irq_refcount;

123 int fence_irq_on;

124 uint32_t irq_enable_reg;

125 int irq_enabled;

126

127 #ifdef I915_HAVE_FENCE

128 uint32_t flush_sequence;

129 uint32_t flush_flags;

130 uint32_t flush_pending;

131 uint32_t saved_flush_status;

132 #endif

133 #ifdef I915_HAVE_BUFFER

134 void *agp_iomap;

135 #endif

136 DRM_SPINTYPE swaps_lock;

137 drm_i915_vbl_swap_t vbl_swaps;

138 unsigned int swaps_pending;

139 } drm_i915_private_t;

140

141 enum intel_chip_family {

142 CHIP_I8XX = 0x01,

143 CHIP_I9XX = 0x02,

144 CHIP_I915 = 0x04,

145 CHIP_I965 = 0x08,

146 };

147

148 extern struct drm_ioctl_desc i915_ioctls[];

149 extern int i915_max_ioctl;

150

151 /* i915_dma.c */

152 extern void i915_kernel_lost_context(struct drm_device * dev);

153 extern int i915_driver_load(struct drm_device *, unsigned long flags);

154 extern void i915_driver_lastclose(struct drm_device * dev);

155 extern void i915_driver_preclose(struct drm_device *dev,

156 struct drm_file *file_priv);

157 extern int i915_driver_device_is_agp(struct drm_device * dev);

158 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,

159 unsigned long arg);

160 extern void i915_emit_breadcrumb(struct drm_device *dev);

161 extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync);

162 extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush);

163 extern int i915_driver_firstopen(struct drm_device *dev);

164

165 /* i915_irq.c */

166 extern int i915_irq_emit(struct drm_device *dev, void *data,

167 struct drm_file *file_priv);

168 extern int i915_irq_wait(struct drm_device *dev, void *data,

169 struct drm_file *file_priv);

170

171 extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);

172 extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);

173 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);

174 extern void i915_driver_irq_preinstall(struct drm_device * dev);

175 extern void i915_driver_irq_postinstall(struct drm_device * dev);

176 extern void i915_driver_irq_uninstall(struct drm_device * dev);

177 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,

178 struct drm_file *file_priv);

179 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,

180 struct drm_file *file_priv);

181 extern int i915_emit_irq(struct drm_device * dev);

182 extern void i915_user_irq_on(drm_i915_private_t *dev_priv);

183 extern void i915_user_irq_off(drm_i915_private_t *dev_priv);

184 extern int i915_vblank_swap(struct drm_device *dev, void *data,

185 struct drm_file *file_priv);

186

187 /* i915_mem.c */

188 extern int i915_mem_alloc(struct drm_device *dev, void *data,

189 struct drm_file *file_priv);

190 extern int i915_mem_free(struct drm_device *dev, void *data,

191 struct drm_file *file_priv);

192 extern int i915_mem_init_heap(struct drm_device *dev, void *data,

193 struct drm_file *file_priv);

194 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,

195 struct drm_file *file_priv);

196 extern void i915_mem_takedown(struct mem_block **heap);

197 extern void i915_mem_release(struct drm_device * dev,

198 struct drm_file *file_priv,

199 struct mem_block *heap);

200 #ifdef I915_HAVE_FENCE

201 /* i915_fence.c */

202

203

204 extern void i915_fence_handler(struct drm_device *dev);

205 extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class,

206 uint32_t flags,

207 uint32_t *sequence,

208 uint32_t *native_type);

209 extern void i915_poke_flush(struct drm_device *dev, uint32_t class);

210 extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);

211 #endif

212

213 #ifdef I915_HAVE_BUFFER

214 /* i915_buffer.c */

215 extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev);

216 extern int i915_fence_types(struct drm_buffer_object *bo, uint32_t *type);

217 extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);

218 extern int i915_init_mem_type(struct drm_device *dev, uint32_t type,

219 struct drm_mem_type_manager *man);

220 extern uint32_t i915_evict_mask(struct drm_buffer_object *bo);

221 extern int i915_move(struct drm_buffer_object *bo, int evict,

222 int no_wait, struct drm_bo_mem_reg *new_mem);

223

224 #endif

225

226 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))

227 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))

228 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))

229 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))

230

231 #define I915_VERBOSE 0

232

233 #define RING_LOCALS unsigned int outring, ringmask, outcount; \

234 volatile char *virt;

235

236 #define BEGIN_LP_RING(n) do { \

237 if (I915_VERBOSE) \

238 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \

239 (n), __FUNCTION__); \

240 if (dev_priv->ring.space < (n)*4) \

241 i915_wait_ring(dev, (n)*4, __FUNCTION__); \

242 outcount = 0; \

243 outring = dev_priv->ring.tail; \

244 ringmask = dev_priv->ring.tail_mask; \

245 virt = dev_priv->ring.virtual_start; \

246 } while (0)

247

248 #define OUT_RING(n) do { \

249 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \

250 *(volatile unsigned int *)(virt + outring) = (n); \

251 outcount++; \

252 outring += 4; \

253 outring &= ringmask; \

254 } while (0)

255

256 #define ADVANCE_LP_RING() do { \

257 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \

258 dev_priv->ring.tail = outring; \

259 dev_priv->ring.space -= outcount * 4; \

260 I915_WRITE(LP_RING + RING_TAIL, outring); \

261 } while(0)

262

263 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);

264

265 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))

266 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))

267 #define CMD_REPORT_HEAD (7<<23)

268 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)

269 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)

270

271 #define CMD_MI_FLUSH (0x04 << 23)

272 #define MI_NO_WRITE_FLUSH (1 << 2)

273 #define MI_READ_FLUSH (1 << 0)

274 #define MI_EXE_FLUSH (1 << 1)

275

276 #define BB1_START_ADDR_MASK (~0x7)

277 #define BB1_PROTECTED (1<<0)

278 #define BB1_UNPROTECTED (0<<0)

279 #define BB2_END_ADDR_MASK (~0x7)

280

281 #define I915REG_HWSTAM 0x02098

282 #define I915REG_INT_IDENTITY_R 0x020a4

283 #define I915REG_INT_MASK_R 0x020a8

284 #define I915REG_INT_ENABLE_R 0x020a0

285 #define I915REG_INSTPM 0x020c0

286

287 #define I915REG_PIPEASTAT 0x70024

288 #define I915REG_PIPEBSTAT 0x71024

289

290 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)

291 #define I915_VBLANK_CLEAR (1UL<<1)

292

293 #define SRX_INDEX 0x3c4

294 #define SRX_DATA 0x3c5

295 #define SR01 1

296 #define SR01_SCREEN_OFF (1<<5)

297

298 #define PPCR 0x61204

299 #define PPCR_ON (1<<0)

300

301 #define DVOB 0x61140

302 #define DVOB_ON (1<<31)

303 #define DVOC 0x61160

304 #define DVOC_ON (1<<31)

305 #define LVDS 0x61180

306 #define LVDS_ON (1<<31)

307

308 #define ADPA 0x61100

309 #define ADPA_DPMS_MASK (~(3<<10))

310 #define ADPA_DPMS_ON (0<<10)

311 #define ADPA_DPMS_SUSPEND (1<<10)

312 #define ADPA_DPMS_STANDBY (2<<10)

313 #define ADPA_DPMS_OFF (3<<10)

314

315 #define NOPID 0x2094

316 #define LP_RING 0x2030

317 #define HP_RING 0x2040

318 #define RING_TAIL 0x00

319 #define TAIL_ADDR 0x001FFFF8

320 #define RING_HEAD 0x04

321 #define HEAD_WRAP_COUNT 0xFFE00000

322 #define HEAD_WRAP_ONE 0x00200000

323 #define HEAD_ADDR 0x001FFFFC

324 #define RING_START 0x08

325 #define START_ADDR 0x0xFFFFF000

326 #define RING_LEN 0x0C

327 #define RING_NR_PAGES 0x001FF000

328 #define RING_REPORT_MASK 0x00000006

329 #define RING_REPORT_64K 0x00000002

330 #define RING_REPORT_128K 0x00000004

331 #define RING_NO_REPORT 0x00000000

332 #define RING_VALID_MASK 0x00000001

333 #define RING_VALID 0x00000001

334 #define RING_INVALID 0x00000000

335

336 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))

337 #define SC_UPDATE_SCISSOR (0x1<<1)

338 #define SC_ENABLE_MASK (0x1<<0)

339 #define SC_ENABLE (0x1<<0)

340

341 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))

342 #define SCI_YMIN_MASK (0xffff<<16)

343 #define SCI_XMIN_MASK (0xffff<<0)

344 #define SCI_YMAX_MASK (0xffff<<16)

345 #define SCI_XMAX_MASK (0xffff<<0)

346

347 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))

348 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)

349 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)

350 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))

351 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)

352 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)

353 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))

354

355 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)

356

357 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)

358 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)

359 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)

360 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)

361

362 #define MI_BATCH_BUFFER ((0x30<<23)|1)

363 #define MI_BATCH_BUFFER_START (0x31<<23)

364 #define MI_BATCH_BUFFER_END (0xA<<23)

365 #define MI_BATCH_NON_SECURE (1)

366

367 #define MI_WAIT_FOR_EVENT ((0x3<<23))

368 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)

369 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)

370 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)

371

372 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))

373

374 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)

375 #define ASYNC_FLIP (1<<22)

376 #define DISPLAY_PLANE_A (0<<20)

377 #define DISPLAY_PLANE_B (1<<20)

378

379 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)

380

381 #define BREADCRUMB_BITS 31

382 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)

383

384 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])

385 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])

386 #endif