git.osdn.net Git - android-x86/external-libdrm.git/blob

1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-

2 */

3 /*

4 *

7 *

8 * Permission is hereby granted, free of charge, to any person obtaining a

9 * copy of this software and associated documentation files (the

10 * "Software"), to deal in the Software without restriction, including

11 * without limitation the rights to use, copy, modify, merge, publish,

12 * distribute, sub license, and/or sell copies of the Software, and to

13 * permit persons to whom the Software is furnished to do so, subject to

14 * the following conditions:

15 *

16 * The above copyright notice and this permission notice (including the

17 * next paragraph) shall be included in all copies or substantial portions

18 * of the Software.

19 *

20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

27 *

28 */

29

30 #ifndef _I915_DRV_H_

31 #define _I915_DRV_H_

32

33 /* General customization:

34 */

35

36 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."

37

38 #define DRIVER_NAME "i915"

39 #define DRIVER_DESC "Intel Graphics"

40 #define DRIVER_DATE "20070209"

41

42 /* Interface history:

43 *

44 * 1.1: Original.

45 * 1.2: Add Power Management

46 * 1.3: Add vblank support

47 * 1.4: Fix cmdbuffer path, add heap destroy

48 * 1.5: Add vblank pipe configuration

49 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank

50 * - Support vertical blank on secondary display pipe

51 * 1.8: New ioctl for ARB_Occlusion_Query

52 * 1.9: Usable page flipping and triple buffering

53 */

54 #define DRIVER_MAJOR 1

55 #define DRIVER_MINOR 9

56 #define DRIVER_PATCHLEVEL 0

57

58 #if defined(__linux__)

59 #define I915_HAVE_FENCE

60 #define I915_HAVE_BUFFER

61 #endif

62

63 typedef struct _drm_i915_ring_buffer {

64 int tail_mask;

65 unsigned long Start;

66 unsigned long End;

67 unsigned long Size;

68 u8 *virtual_start;

69 int head;

70 int tail;

71 int space;

72 drm_local_map_t map;

73 } drm_i915_ring_buffer_t;

74

75 struct mem_block {

76 struct mem_block *next;

77 struct mem_block *prev;

78 int start;

79 int size;

80 DRMFILE filp; /* 0: free, -1: heap, other: real files */

81 };

82

83 typedef struct _drm_i915_vbl_swap {

84 struct list_head head;

85 drm_drawable_t drw_id;

86 unsigned int pipe;

87 unsigned int sequence;

88 int flip;

89 } drm_i915_vbl_swap_t;

90

91 typedef struct drm_i915_private {

92 drm_local_map_t *sarea;

93 drm_local_map_t *mmio_map;

94

95 drm_i915_sarea_t *sarea_priv;

96 drm_i915_ring_buffer_t ring;

97

98 drm_dma_handle_t *status_page_dmah;

99 void *hw_status_page;

100 dma_addr_t dma_status_page;

101 uint32_t counter;

102

103 unsigned int cpp;

104 int use_mi_batchbuffer_start;

105

106 wait_queue_head_t irq_queue;

107 atomic_t irq_received;

108 atomic_t irq_emitted;

109

110 int tex_lru_log_granularity;

111 int allow_batchbuffer;

112 struct mem_block *agp_heap;

113 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;

114 int vblank_pipe;

115 spinlock_t user_irq_lock;

116 int user_irq_refcount;

117 int fence_irq_on;

118 uint32_t irq_enable_reg;

119 int irq_enabled;

120

121 #ifdef I915_HAVE_FENCE

122 uint32_t flush_sequence;

123 uint32_t flush_flags;

124 uint32_t flush_pending;

125 uint32_t saved_flush_status;

126 #endif

127 #ifdef I915_HAVE_BUFFER

128 void *agp_iomap;

129 #endif

130 spinlock_t swaps_lock;

131 drm_i915_vbl_swap_t vbl_swaps;

132 unsigned int swaps_pending;

133 } drm_i915_private_t;

134

135 enum intel_chip_family {

136 CHIP_I8XX = 0x01,

137 CHIP_I9XX = 0x02,

138 CHIP_I915 = 0x04,

139 CHIP_I965 = 0x08,

140 };

141

142 extern drm_ioctl_desc_t i915_ioctls[];

143 extern int i915_max_ioctl;

144

145 /* i915_dma.c */

146 extern void i915_kernel_lost_context(drm_device_t * dev);

147 extern int i915_driver_load(struct drm_device *, unsigned long flags);

148 extern void i915_driver_lastclose(drm_device_t * dev);

149 extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp);

150 extern int i915_driver_device_is_agp(drm_device_t * dev);

151 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,

152 unsigned long arg);

153 extern void i915_emit_breadcrumb(drm_device_t *dev);

154 extern void i915_dispatch_flip(drm_device_t * dev, int pipes, int sync);

155 extern int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush);

156 extern int i915_driver_firstopen(struct drm_device *dev);

157

158 /* i915_irq.c */

159 extern int i915_irq_emit(DRM_IOCTL_ARGS);

160 extern int i915_irq_wait(DRM_IOCTL_ARGS);

161

162 extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);

163 extern int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence);

164 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);

165 extern void i915_driver_irq_preinstall(drm_device_t * dev);

166 extern void i915_driver_irq_postinstall(drm_device_t * dev);

167 extern void i915_driver_irq_uninstall(drm_device_t * dev);

168 extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS);

169 extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS);

170 extern int i915_emit_irq(drm_device_t * dev);

171 extern void i915_user_irq_on(drm_i915_private_t *dev_priv);

172 extern void i915_user_irq_off(drm_i915_private_t *dev_priv);

173 extern int i915_vblank_swap(DRM_IOCTL_ARGS);

174

175 /* i915_mem.c */

176 extern int i915_mem_alloc(DRM_IOCTL_ARGS);

177 extern int i915_mem_free(DRM_IOCTL_ARGS);

178 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);

179 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS);

180 extern void i915_mem_takedown(struct mem_block **heap);

181 extern void i915_mem_release(drm_device_t * dev,

182 DRMFILE filp, struct mem_block *heap);

183 #ifdef I915_HAVE_FENCE

184 /* i915_fence.c */

185

186

187 extern void i915_fence_handler(drm_device_t *dev);

188 extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class,

189 uint32_t flags,

190 uint32_t *sequence,

191 uint32_t *native_type);

192 extern void i915_poke_flush(drm_device_t *dev, uint32_t class);

193 extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags);

194 #endif

195

196 #ifdef I915_HAVE_BUFFER

197 /* i915_buffer.c */

198 extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev);

199 extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type);

200 extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags);

201 extern int i915_init_mem_type(drm_device_t *dev, uint32_t type,

202 drm_mem_type_manager_t *man);

203 extern uint32_t i915_evict_mask(drm_buffer_object_t *bo);

204 extern int i915_move(drm_buffer_object_t *bo, int evict,

205 int no_wait, drm_bo_mem_reg_t *new_mem);

206

207 #endif

208

209 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))

210 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))

211 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))

212 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))

213

214 #define I915_VERBOSE 0

215

216 #define RING_LOCALS unsigned int outring, ringmask, outcount; \

217 volatile char *virt;

218

219 #define BEGIN_LP_RING(n) do { \

220 if (I915_VERBOSE) \

221 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \

222 (n), __FUNCTION__); \

223 if (dev_priv->ring.space < (n)*4) \

224 i915_wait_ring(dev, (n)*4, __FUNCTION__); \

225 outcount = 0; \

226 outring = dev_priv->ring.tail; \

227 ringmask = dev_priv->ring.tail_mask; \

228 virt = dev_priv->ring.virtual_start; \

229 } while (0)

230

231 #define OUT_RING(n) do { \

232 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \

233 *(volatile unsigned int *)(virt + outring) = (n); \

234 outcount++; \

235 outring += 4; \

236 outring &= ringmask; \

237 } while (0)

238

239 #define ADVANCE_LP_RING() do { \

240 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \

241 dev_priv->ring.tail = outring; \

242 dev_priv->ring.space -= outcount * 4; \

243 I915_WRITE(LP_RING + RING_TAIL, outring); \

244 } while(0)

245

246 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);

247

248 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))

249 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))

250 #define CMD_REPORT_HEAD (7<<23)

251 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)

252 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)

253

254 #define CMD_MI_FLUSH (0x04 << 23)

255 #define MI_NO_WRITE_FLUSH (1 << 2)

256 #define MI_READ_FLUSH (1 << 0)

257 #define MI_EXE_FLUSH (1 << 1)

258

259 #define BB1_START_ADDR_MASK (~0x7)

260 #define BB1_PROTECTED (1<<0)

261 #define BB1_UNPROTECTED (0<<0)

262 #define BB2_END_ADDR_MASK (~0x7)

263

264 #define I915REG_HWSTAM 0x02098

265 #define I915REG_INT_IDENTITY_R 0x020a4

266 #define I915REG_INT_MASK_R 0x020a8

267 #define I915REG_INT_ENABLE_R 0x020a0

268 #define I915REG_INSTPM 0x020c0

269

270 #define I915REG_PIPEASTAT 0x70024

271 #define I915REG_PIPEBSTAT 0x71024

272

273 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)

274 #define I915_VBLANK_CLEAR (1UL<<1)

275

276 #define SRX_INDEX 0x3c4

277 #define SRX_DATA 0x3c5

278 #define SR01 1

279 #define SR01_SCREEN_OFF (1<<5)

280

281 #define PPCR 0x61204

282 #define PPCR_ON (1<<0)

283

284 #define DVOB 0x61140

285 #define DVOB_ON (1<<31)

286 #define DVOC 0x61160

287 #define DVOC_ON (1<<31)

288 #define LVDS 0x61180

289 #define LVDS_ON (1<<31)

290

291 #define ADPA 0x61100

292 #define ADPA_DPMS_MASK (~(3<<10))

293 #define ADPA_DPMS_ON (0<<10)

294 #define ADPA_DPMS_SUSPEND (1<<10)

295 #define ADPA_DPMS_STANDBY (2<<10)

296 #define ADPA_DPMS_OFF (3<<10)

297

298 #define NOPID 0x2094

299 #define LP_RING 0x2030

300 #define HP_RING 0x2040

301 #define RING_TAIL 0x00

302 #define TAIL_ADDR 0x001FFFF8

303 #define RING_HEAD 0x04

304 #define HEAD_WRAP_COUNT 0xFFE00000

305 #define HEAD_WRAP_ONE 0x00200000

306 #define HEAD_ADDR 0x001FFFFC

307 #define RING_START 0x08

308 #define START_ADDR 0x0xFFFFF000

309 #define RING_LEN 0x0C

310 #define RING_NR_PAGES 0x001FF000

311 #define RING_REPORT_MASK 0x00000006

312 #define RING_REPORT_64K 0x00000002

313 #define RING_REPORT_128K 0x00000004

314 #define RING_NO_REPORT 0x00000000

315 #define RING_VALID_MASK 0x00000001

316 #define RING_VALID 0x00000001

317 #define RING_INVALID 0x00000000

318

319 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))

320 #define SC_UPDATE_SCISSOR (0x1<<1)

321 #define SC_ENABLE_MASK (0x1<<0)

322 #define SC_ENABLE (0x1<<0)

323

324 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))

325 #define SCI_YMIN_MASK (0xffff<<16)

326 #define SCI_XMIN_MASK (0xffff<<0)

327 #define SCI_YMAX_MASK (0xffff<<16)

328 #define SCI_XMAX_MASK (0xffff<<0)

329

330 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))

331 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)

332 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)

333 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))

334 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)

335 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)

336 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))

337

338 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)

339

340 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)

341 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)

342 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)

343 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)

344

345 #define MI_BATCH_BUFFER ((0x30<<23)|1)

346 #define MI_BATCH_BUFFER_START (0x31<<23)

347 #define MI_BATCH_BUFFER_END (0xA<<23)

348 #define MI_BATCH_NON_SECURE (1)

349

350 #define MI_WAIT_FOR_EVENT ((0x3<<23))

351 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)

352 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)

353 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)

354

355 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))

356

357 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)

358 #define ASYNC_FLIP (1<<22)

359 #define DISPLAY_PLANE_A (0<<20)

360 #define DISPLAY_PLANE_B (1<<20)

361

362 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)

363

364 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])

365 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])

366 #endif