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1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-

2 */

3 /*

4 *

7 *

8 * Permission is hereby granted, free of charge, to any person obtaining a

9 * copy of this software and associated documentation files (the

10 * "Software"), to deal in the Software without restriction, including

11 * without limitation the rights to use, copy, modify, merge, publish,

12 * distribute, sub license, and/or sell copies of the Software, and to

13 * permit persons to whom the Software is furnished to do so, subject to

14 * the following conditions:

15 *

16 * The above copyright notice and this permission notice (including the

17 * next paragraph) shall be included in all copies or substantial portions

18 * of the Software.

19 *

20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

27 *

28 */

29

30 #ifndef _I915_DRV_H_

31 #define _I915_DRV_H_

32

33 /* General customization:

34 */

35

36 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."

37

38 #define DRIVER_NAME "i915"

39 #define DRIVER_DESC "Intel Graphics"

40 #define DRIVER_DATE "20080730"

41

42 #if defined(__linux__)

43 #define I915_HAVE_FENCE

44 #define I915_HAVE_BUFFER

45 #endif

46

47 /* Interface history:

48 *

49 * 1.1: Original.

50 * 1.2: Add Power Management

51 * 1.3: Add vblank support

52 * 1.4: Fix cmdbuffer path, add heap destroy

53 * 1.5: Add vblank pipe configuration

54 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank

55 * - Support vertical blank on secondary display pipe

56 * 1.8: New ioctl for ARB_Occlusion_Query

57 * 1.9: Usable page flipping and triple buffering

58 * 1.10: Plane/pipe disentangling

59 * 1.11: TTM superioctl

60 * 1.12: TTM relocation optimization

61 */

62 #define DRIVER_MAJOR 1

63 #if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER)

64 #define DRIVER_MINOR 13

65 #else

66 #define DRIVER_MINOR 6

67 #endif

68 #define DRIVER_PATCHLEVEL 0

69

70 enum pipe {

71 PIPE_A = 0,

72 PIPE_B,

73 };

74

75 #ifdef I915_HAVE_BUFFER

76 #define I915_MAX_VALIDATE_BUFFERS 4096

77 struct drm_i915_validate_buffer;

78 #endif

79

80 #define WATCH_COHERENCY 0

81 #define WATCH_BUF 0

82 #define WATCH_EXEC 0

83 #define WATCH_LRU 0

84 #define WATCH_RELOC 0

85 #define WATCH_INACTIVE 0

86 #define WATCH_PWRITE 0

87

88 typedef struct _drm_i915_ring_buffer {

89 int tail_mask;

90 unsigned long Size;

91 u8 *virtual_start;

92 int head;

93 int tail;

94 int space;

95 drm_local_map_t map;

96 struct drm_gem_object *ring_obj;

97 } drm_i915_ring_buffer_t;

98

99 struct mem_block {

100 struct mem_block *next;

101 struct mem_block *prev;

102 int start;

103 int size;

104 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */

105 };

106

107 typedef struct _drm_i915_vbl_swap {

108 struct list_head head;

109 drm_drawable_t drw_id;

110 unsigned int plane;

111 unsigned int sequence;

112 int flip;

113 } drm_i915_vbl_swap_t;

114

115 #ifdef __linux__

116 struct opregion_header;

117 struct opregion_acpi;

118 struct opregion_swsci;

119 struct opregion_asle;

120

121 struct intel_opregion {

122 struct opregion_header *header;

123 struct opregion_acpi *acpi;

124 struct opregion_swsci *swsci;

125 struct opregion_asle *asle;

126

127 int enabled;

128 };

129 #endif

130

131 typedef struct drm_i915_private {

132 struct drm_device *dev;

133

134 drm_local_map_t *sarea;

135 drm_local_map_t *mmio_map;

136

137 drm_i915_sarea_t *sarea_priv;

138 drm_i915_ring_buffer_t ring;

139

140 drm_dma_handle_t *status_page_dmah;

141 void *hw_status_page;

142 dma_addr_t dma_status_page;

143 uint32_t counter;

144 unsigned int status_gfx_addr;

145 drm_local_map_t hws_map;

146 struct drm_gem_object *hws_obj;

147

148 unsigned int cpp;

149

150 wait_queue_head_t irq_queue;

151 atomic_t irq_received;

152

153 int tex_lru_log_granularity;

154 int allow_batchbuffer;

155 struct mem_block *agp_heap;

156 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;

157 int vblank_pipe;

158 DRM_SPINTYPE user_irq_lock;

159 int user_irq_refcount;

160 int fence_irq_on;

161 uint32_t irq_mask_reg;

162 int irq_enabled;

163

164 #ifdef I915_HAVE_FENCE

165 uint32_t flush_sequence;

166 uint32_t flush_flags;

167 uint32_t flush_pending;

168 uint32_t saved_flush_status;

169 #endif

170 #ifdef I915_HAVE_BUFFER

171 void *agp_iomap;

172 unsigned int max_validate_buffers;

173 struct mutex cmdbuf_mutex;

174 struct drm_i915_validate_buffer *val_bufs;

175 #endif

176

177 DRM_SPINTYPE swaps_lock;

178 drm_i915_vbl_swap_t vbl_swaps;

179 unsigned int swaps_pending;

180 #if defined(I915_HAVE_BUFFER)

181 /* DRI2 sarea */

182 struct drm_buffer_object *sarea_bo;

183 struct drm_bo_kmap_obj sarea_kmap;

184 #endif

185

186 #ifdef __linux__

187 struct intel_opregion opregion;

188 #endif

189

190 /* Register state */

191 u8 saveLBB;

192 u32 saveDSPACNTR;

193 u32 saveDSPBCNTR;

194 u32 saveDSPARB;

195 u32 savePIPEACONF;

196 u32 savePIPEBCONF;

197 u32 savePIPEASRC;

198 u32 savePIPEBSRC;

199 u32 saveFPA0;

200 u32 saveFPA1;

201 u32 saveDPLL_A;

202 u32 saveDPLL_A_MD;

203 u32 saveHTOTAL_A;

204 u32 saveHBLANK_A;

205 u32 saveHSYNC_A;

206 u32 saveVTOTAL_A;

207 u32 saveVBLANK_A;

208 u32 saveVSYNC_A;

209 u32 saveBCLRPAT_A;

210 u32 savePIPEASTAT;

211 u32 saveDSPASTRIDE;

212 u32 saveDSPASIZE;

213 u32 saveDSPAPOS;

214 u32 saveDSPAADDR;

215 u32 saveDSPASURF;

216 u32 saveDSPATILEOFF;

217 u32 savePFIT_PGM_RATIOS;

218 u32 saveBLC_PWM_CTL;

219 u32 saveBLC_PWM_CTL2;

220 u32 saveFPB0;

221 u32 saveFPB1;

222 u32 saveDPLL_B;

223 u32 saveDPLL_B_MD;

224 u32 saveHTOTAL_B;

225 u32 saveHBLANK_B;

226 u32 saveHSYNC_B;

227 u32 saveVTOTAL_B;

228 u32 saveVBLANK_B;

229 u32 saveVSYNC_B;

230 u32 saveBCLRPAT_B;

231 u32 savePIPEBSTAT;

232 u32 saveDSPBSTRIDE;

233 u32 saveDSPBSIZE;

234 u32 saveDSPBPOS;

235 u32 saveDSPBADDR;

236 u32 saveDSPBSURF;

237 u32 saveDSPBTILEOFF;

238 u32 saveVGA0;

239 u32 saveVGA1;

240 u32 saveVGA_PD;

241 u32 saveVGACNTRL;

242 u32 saveADPA;

243 u32 saveLVDS;

244 u32 savePP_ON_DELAYS;

245 u32 savePP_OFF_DELAYS;

246 u32 saveDVOA;

247 u32 saveDVOB;

248 u32 saveDVOC;

249 u32 savePP_ON;

250 u32 savePP_OFF;

251 u32 savePP_CONTROL;

252 u32 savePP_DIVISOR;

253 u32 savePFIT_CONTROL;

254 u32 save_palette_a[256];

255 u32 save_palette_b[256];

256 u32 saveFBC_CFB_BASE;

257 u32 saveFBC_LL_BASE;

258 u32 saveFBC_CONTROL;

259 u32 saveFBC_CONTROL2;

260 u32 saveIER;

261 u32 saveIIR;

262 u32 saveIMR;

263 u32 saveCACHE_MODE_0;

264 u32 saveD_STATE;

265 u32 saveCG_2D_DIS;

266 u32 saveMI_ARB_STATE;

267 u32 saveSWF0[16];

268 u32 saveSWF1[16];

269 u32 saveSWF2[3];

270 u8 saveMSR;

271 u8 saveSR[8];

272 u8 saveGR[25];

273 u8 saveAR_INDEX;

274 u8 saveAR[21];

275 u8 saveDACMASK;

276 u8 saveDACDATA[256*3]; /* 256 3-byte colors */

277 u8 saveCR[37];

278

279 struct {

280 struct drm_mm gtt_space;

281

282 /**

283 * List of objects currently involved in rendering from the

284 * ringbuffer.

285 *

286 * A reference is held on the buffer while on this list.

287 */

288 struct list_head active_list;

289

290 /**

291 * List of objects which are not in the ringbuffer but which

292 * still have a write_domain which needs to be flushed before

293 * unbinding.

294 *

295 * A reference is held on the buffer while on this list.

296 */

297 struct list_head flushing_list;

298

299 /**

300 * LRU list of objects which are not in the ringbuffer and

301 * are ready to unbind, but are still in the GTT.

302 *

303 * A reference is not held on the buffer while on this list,

304 * as merely being GTT-bound shouldn't prevent its being

305 * freed, and we'll pull it off the list in the free path.

306 */

307 struct list_head inactive_list;

308

309 /**

310 * List of breadcrumbs associated with GPU requests currently

311 * outstanding.

312 */

313 struct list_head request_list;

314

315 /**

316 * We leave the user IRQ off as much as possible,

317 * but this means that requests will finish and never

318 * be retired once the system goes idle. Set a timer to

319 * fire periodically while the ring is running. When it

320 * fires, go retire requests.

321 */

322 struct delayed_work retire_work;

323

324 uint32_t next_gem_seqno;

325

326 /**

327 * Waiting sequence number, if any

328 */

329 uint32_t waiting_gem_seqno;

330

331 /**

332 * Last seq seen at irq time

333 */

334 uint32_t irq_gem_seqno;

335

336 /**

337 * Flag if the X Server, and thus DRM, is not currently in

338 * control of the device.

339 *

340 * This is set between LeaveVT and EnterVT. It needs to be

341 * replaced with a semaphore. It also needs to be

342 * transitioned away from for kernel modesetting.

343 */

344 int suspended;

345

346 /**

347 * Flag if the hardware appears to be wedged.

348 *

349 * This is set when attempts to idle the device timeout.

350 * It prevents command submission from occuring and makes

351 * every pending request fail

352 */

353 int wedged;

354

355 /** Bit 6 swizzling required for X tiling */

356 uint32_t bit_6_swizzle_x;

357 /** Bit 6 swizzling required for Y tiling */

358 uint32_t bit_6_swizzle_y;

359 } mm;

360 } drm_i915_private_t;

361

362 struct drm_i915_file_private {

363 struct {

364 uint32_t last_gem_seqno;

365 uint32_t last_gem_throttle_seqno;

366 } mm;

367 };

368

369 enum intel_chip_family {

370 CHIP_I8XX = 0x01,

371 CHIP_I9XX = 0x02,

372 CHIP_I915 = 0x04,

373 CHIP_I965 = 0x08,

374 };

375

376 /** driver private structure attached to each drm_gem_object */

377 struct drm_i915_gem_object {

378 struct drm_gem_object *obj;

379

380 /** Current space allocated to this object in the GTT, if any. */

381 struct drm_mm_node *gtt_space;

382

383 /** This object's place on the active/flushing/inactive lists */

384 struct list_head list;

385

386 /**

387 * This is set if the object is on the active or flushing lists

388 * (has pending rendering), and is not set if it's on inactive (ready

389 * to be unbound).

390 */

391 int active;

392

393 /**

394 * This is set if the object has been written to since last bound

395 * to the GTT

396 */

397 int dirty;

398

399 /** AGP memory structure for our GTT binding. */

400 DRM_AGP_MEM *agp_mem;

401

402 struct page **page_list;

403

404 /**

405 * Current offset of the object in GTT space.

406 *

407 * This is the same as gtt_space->start

408 */

409 uint32_t gtt_offset;

410

411 /** Boolean whether this object has a valid gtt offset. */

412 int gtt_bound;

413

414 /** How many users have pinned this object in GTT space */

415 int pin_count;

416

417 /** Breadcrumb of last rendering to the buffer. */

418 uint32_t last_rendering_seqno;

419

420 /** Current tiling mode for the object. */

421 uint32_t tiling_mode;

422

423 /**

424 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when

425 * GEM_DOMAIN_CPU is not in the object's read domain.

426 */

427 uint8_t *page_cpu_valid;

428 };

429

430 /**

431 * Request queue structure.

432 *

433 * The request queue allows us to note sequence numbers that have been emitted

434 * and may be associated with active buffers to be retired.

435 *

436 * By keeping this list, we can avoid having to do questionable

437 * sequence-number comparisons on buffer last_rendering_seqnos, and associate

438 * an emission time with seqnos for tracking how far ahead of the GPU we are.

439 */

440 struct drm_i915_gem_request {

441 /** GEM sequence number associated with this request. */

442 uint32_t seqno;

443

444 /** Time at which this request was emitted, in jiffies. */

445 unsigned long emitted_jiffies;

446

447 /** Cache domains that were flushed at the start of the request. */

448 uint32_t flush_domains;

449

450 struct list_head list;

451 };

452

453 extern struct drm_ioctl_desc i915_ioctls[];

454 extern int i915_max_ioctl;

455

456 /* i915_dma.c */

457 extern void i915_kernel_lost_context(struct drm_device * dev);

458 extern int i915_driver_load(struct drm_device *, unsigned long flags);

459 extern int i915_driver_unload(struct drm_device *);

460 extern void i915_driver_lastclose(struct drm_device * dev);

461 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);

462 extern void i915_driver_preclose(struct drm_device *dev,

463 struct drm_file *file_priv);

464 extern void i915_driver_postclose(struct drm_device *dev,

465 struct drm_file *file_priv);

466 extern int i915_driver_device_is_agp(struct drm_device * dev);

467 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,

468 unsigned long arg);

469 extern void i915_emit_breadcrumb(struct drm_device *dev);

470 extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync);

471 extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush);

472 extern int i915_driver_firstopen(struct drm_device *dev);

473 extern int i915_dispatch_batchbuffer(struct drm_device * dev,

474 drm_i915_batchbuffer_t * batch);

475 extern int i915_quiescent(struct drm_device *dev);

476

477 int i915_emit_box(struct drm_device * dev,

478 struct drm_clip_rect __user * boxes,

479 int i, int DR1, int DR4);

480

481 /* i915_irq.c */

482 extern int i915_irq_emit(struct drm_device *dev, void *data,

483 struct drm_file *file_priv);

484 extern int i915_irq_wait(struct drm_device *dev, void *data,

485 struct drm_file *file_priv);

486

487 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);

488 extern void i915_driver_irq_preinstall(struct drm_device * dev);

489 extern int i915_driver_irq_postinstall(struct drm_device * dev);

490 extern void i915_driver_irq_uninstall(struct drm_device * dev);

491 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,

492 struct drm_file *file_priv);

493 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,

494 struct drm_file *file_priv);

495 extern int i915_emit_irq(struct drm_device * dev);

496 extern int i915_wait_irq(struct drm_device * dev, int irq_nr);

497 extern int i915_enable_vblank(struct drm_device *dev, int crtc);

498 extern void i915_disable_vblank(struct drm_device *dev, int crtc);

499 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);

500 extern int i915_vblank_swap(struct drm_device *dev, void *data,

501 struct drm_file *file_priv);

502 extern void i915_user_irq_on(drm_i915_private_t *dev_priv);

503 extern void i915_user_irq_off(drm_i915_private_t *dev_priv);

504

505 /* i915_mem.c */

506 extern int i915_mem_alloc(struct drm_device *dev, void *data,

507 struct drm_file *file_priv);

508 extern int i915_mem_free(struct drm_device *dev, void *data,

509 struct drm_file *file_priv);

510 extern int i915_mem_init_heap(struct drm_device *dev, void *data,

511 struct drm_file *file_priv);

512 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,

513 struct drm_file *file_priv);

514 extern void i915_mem_takedown(struct mem_block **heap);

515 extern void i915_mem_release(struct drm_device * dev,

516 struct drm_file *file_priv,

517 struct mem_block *heap);

518

519 /* i915_suspend.c */

520 extern int i915_save_state(struct drm_device *dev);

521 extern int i915_restore_state(struct drm_device *dev);

522

523 #ifdef I915_HAVE_FENCE

524 /* i915_fence.c */

525 extern void i915_fence_handler(struct drm_device *dev);

526 extern void i915_invalidate_reported_sequence(struct drm_device *dev);

527

528 #endif

529

530 #ifdef I915_HAVE_BUFFER

531 /* i915_buffer.c */

532 extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev);

533 extern int i915_fence_type(struct drm_buffer_object *bo, uint32_t *fclass,

534 uint32_t *type);

535 extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);

536 extern int i915_init_mem_type(struct drm_device *dev, uint32_t type,

537 struct drm_mem_type_manager *man);

538 extern uint64_t i915_evict_flags(struct drm_buffer_object *bo);

539 extern int i915_move(struct drm_buffer_object *bo, int evict,

540 int no_wait, struct drm_bo_mem_reg *new_mem);

541 void i915_flush_ttm(struct drm_ttm *ttm);

542 /* i915_execbuf.c */

543 int i915_execbuffer(struct drm_device *dev, void *data,

544 struct drm_file *file_priv);

545 /* i915_gem.c */

546 int i915_gem_init_ioctl(struct drm_device *dev, void *data,

547 struct drm_file *file_priv);

548 int i915_gem_create_ioctl(struct drm_device *dev, void *data,

549 struct drm_file *file_priv);

550 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,

551 struct drm_file *file_priv);

552 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,

553 struct drm_file *file_priv);

554 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,

555 struct drm_file *file_priv);

556 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,

557 struct drm_file *file_priv);

558 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,

559 struct drm_file *file_priv);

560 int i915_gem_execbuffer(struct drm_device *dev, void *data,

561 struct drm_file *file_priv);

562 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,

563 struct drm_file *file_priv);

564 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,

565 struct drm_file *file_priv);

566 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,

567 struct drm_file *file_priv);

568 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,

569 struct drm_file *file_priv);

570 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,

571 struct drm_file *file_priv);

572 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,

573 struct drm_file *file_priv);

574 int i915_gem_set_tiling(struct drm_device *dev, void *data,

575 struct drm_file *file_priv);

576 int i915_gem_get_tiling(struct drm_device *dev, void *data,

577 struct drm_file *file_priv);

578 void i915_gem_load(struct drm_device *dev);

579 int i915_gem_proc_init(struct drm_minor *minor);

580 void i915_gem_proc_cleanup(struct drm_minor *minor);

581 int i915_gem_init_object(struct drm_gem_object *obj);

582 void i915_gem_free_object(struct drm_gem_object *obj);

583 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);

584 void i915_gem_object_unpin(struct drm_gem_object *obj);

585 void i915_gem_lastclose(struct drm_device *dev);

586 uint32_t i915_get_gem_seqno(struct drm_device *dev);

587 void i915_gem_retire_requests(struct drm_device *dev);

588 void i915_gem_retire_work_handler(struct work_struct *work);

589 void i915_gem_clflush_object(struct drm_gem_object *obj);

590 #endif

591

592 /* i915_gem_tiling.c */

593 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);

594

595 /* i915_gem_debug.c */

596 void i915_gem_dump_object(struct drm_gem_object *obj, int len,

597 const char *where, uint32_t mark);

598 #if WATCH_INACTIVE

599 void i915_verify_inactive(struct drm_device *dev, char *file, int line);

600 #else

601 #define i915_verify_inactive(dev,file,line)

602 #endif

603 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);

604 void i915_gem_dump_object(struct drm_gem_object *obj, int len,

605 const char *where, uint32_t mark);

606 void i915_dump_lru(struct drm_device *dev, const char *where);

607

608 #ifdef __linux__

609 /* i915_opregion.c */

610 extern int intel_opregion_init(struct drm_device *dev);

611 extern void intel_opregion_free(struct drm_device *dev);

612 extern void opregion_asle_intr(struct drm_device *dev);

613 extern void opregion_enable_asle(struct drm_device *dev);

614 #endif

615

616 #ifdef __linux__

617 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)

618 extern void intel_init_chipset_flush_compat(struct drm_device *dev);

619 extern void intel_fini_chipset_flush_compat(struct drm_device *dev);

620 #endif

621 #endif

622

623 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))

624 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))

625 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))

626 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))

627 #define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg))

628 #define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val))

629

630 #if defined(__FreeBSD__)

631 typedef boolean_t bool;

632 #endif

633

634 #define I915_VERBOSE 0

635 #define I915_RING_VALIDATE 0

636

637 #define PRIMARY_RINGBUFFER_SIZE (128*1024)

638

639 #define RING_LOCALS unsigned int outring, ringmask, outcount; \

640 volatile char *virt;

641

642 #if I915_RING_VALIDATE

643 void i915_ring_validate(struct drm_device *dev, const char *func, int line);

644 #define I915_RING_DO_VALIDATE(dev) i915_ring_validate(dev, __FUNCTION__, __LINE__)

645 #else

646 #define I915_RING_DO_VALIDATE(dev)

647 #endif

648

649 #define BEGIN_LP_RING(n) do { \

650 if (I915_VERBOSE) \

651 DRM_DEBUG("BEGIN_LP_RING(%d)\n", \

652 (n)); \

653 I915_RING_DO_VALIDATE(dev); \

654 if (dev_priv->ring.space < (n)*4) \

655 i915_wait_ring(dev, (n)*4, __FUNCTION__); \

656 outcount = 0; \

657 outring = dev_priv->ring.tail; \

658 ringmask = dev_priv->ring.tail_mask; \

659 virt = dev_priv->ring.virtual_start; \

660 } while (0)

661

662 #define OUT_RING(n) do { \

663 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \

664 *(volatile unsigned int *)(virt + outring) = (n); \

665 outcount++; \

666 outring += 4; \

667 outring &= ringmask; \

668 } while (0)

669

670 #define ADVANCE_LP_RING() do { \

671 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \

672 I915_RING_DO_VALIDATE(dev); \

673 dev_priv->ring.tail = outring; \

674 dev_priv->ring.space -= outcount * 4; \

675 I915_WRITE(PRB0_TAIL, outring); \

676 } while(0)

677

678 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);

679

680 #define BREADCRUMB_BITS 31

681 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)

682

683 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])

684 /**

685 * Reads a dword out of the status page, which is written to from the command

686 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or

687 * MI_STORE_DATA_IMM.

688 *

689 * The following dwords have a reserved meaning:

690 * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.

691 * 4: ring 0 head pointer

692 * 5: ring 1 head pointer (915-class)

693 * 6: ring 2 head pointer (915-class)

694 *

695 * The area from dword 0x10 to 0x3ff is available for driver usage.

696 */

697 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])

698 #define I915_GEM_HWS_INDEX 0x10

699

700 /* MCH MMIO space */

701 /** 915-945 and GM965 MCH register controlling DRAM channel access */

702 #define DCC 0x200

703 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)

704 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)

705 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)

706 #define DCC_ADDRESSING_MODE_MASK (3 << 0)

707 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)

708

709 /** 965 MCH register controlling DRAM channel configuration */

710 #define CHDECMISC 0x111

711 #define CHDECMISC_FLEXMEMORY (1 << 1)

712

713 /*

714 * The Bridge device's PCI config space has information about the

715 * fb aperture size and the amount of pre-reserved memory.

716 */

717 #define INTEL_GMCH_CTRL 0x52

718 #define INTEL_GMCH_ENABLED 0x4

719 #define INTEL_GMCH_MEM_MASK 0x1

720 #define INTEL_GMCH_MEM_64M 0x1

721 #define INTEL_GMCH_MEM_128M 0

722

723 #define INTEL_855_GMCH_GMS_MASK (0x7 << 4)

724 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)

725 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)

726 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)

727 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)

728 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)

729 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)

730

731 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)

732 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)

733

734 /* PCI config space */

735

736 #define HPLLCC 0xc0 /* 855 only */

737 #define GC_CLOCK_CONTROL_MASK (3 << 0)

738 #define GC_CLOCK_133_200 (0 << 0)

739 #define GC_CLOCK_100_200 (1 << 0)

740 #define GC_CLOCK_100_133 (2 << 0)

741 #define GC_CLOCK_166_250 (3 << 0)

742 #define GCFGC 0xf0 /* 915+ only */

743 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)

744 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)

745 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)

746 #define GC_DISPLAY_CLOCK_MASK (7 << 4)

747 #define LBB 0xf4

748

749 /* VGA stuff */

750

751 #define VGA_ST01_MDA 0x3ba

752 #define VGA_ST01_CGA 0x3da

753

754 #define VGA_MSR_WRITE 0x3c2

755 #define VGA_MSR_READ 0x3cc

756 #define VGA_MSR_MEM_EN (1<<1)

757 #define VGA_MSR_CGA_MODE (1<<0)

758

759 #define VGA_SR_INDEX 0x3c4

760 #define VGA_SR_DATA 0x3c5

761

762 #define VGA_AR_INDEX 0x3c0

763 #define VGA_AR_VID_EN (1<<5)

764 #define VGA_AR_DATA_WRITE 0x3c0

765 #define VGA_AR_DATA_READ 0x3c1

766

767 #define VGA_GR_INDEX 0x3ce

768 #define VGA_GR_DATA 0x3cf

769 /* GR05 */

770 #define VGA_GR_MEM_READ_MODE_SHIFT 3

771 #define VGA_GR_MEM_READ_MODE_PLANE 1

772 /* GR06 */

773 #define VGA_GR_MEM_MODE_MASK 0xc

774 #define VGA_GR_MEM_MODE_SHIFT 2

775 #define VGA_GR_MEM_A0000_AFFFF 0

776 #define VGA_GR_MEM_A0000_BFFFF 1

777 #define VGA_GR_MEM_B0000_B7FFF 2

778 #define VGA_GR_MEM_B0000_BFFFF 3

779

780 #define VGA_DACMASK 0x3c6

781 #define VGA_DACRX 0x3c7

782 #define VGA_DACWX 0x3c8

783 #define VGA_DACDATA 0x3c9

784

785 #define VGA_CR_INDEX_MDA 0x3b4

786 #define VGA_CR_DATA_MDA 0x3b5

787 #define VGA_CR_INDEX_CGA 0x3d4

788 #define VGA_CR_DATA_CGA 0x3d5

789

790 /*

791 * Memory interface instructions used by the kernel

792 */

793 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))

794

795 #define MI_NOOP MI_INSTR(0, 0)

796 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)

797 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)

798 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)

799 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)

800 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)

801 #define MI_FLUSH MI_INSTR(0x04, 0)

802 #define MI_READ_FLUSH (1 << 0)

803 #define MI_EXE_FLUSH (1 << 1)

804 #define MI_NO_WRITE_FLUSH (1 << 2)

805 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */

806 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */

807 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)

808 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)

809 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)

810 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)

811 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */

812 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)

813 #define MI_STORE_DWORD_INDEX_SHIFT 2

814 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)

815 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)

816 #define MI_BATCH_NON_SECURE (1)

817 #define MI_BATCH_NON_SECURE_I965 (1<<8)

818 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)

819

820 /*

821 * 3D instructions used by the kernel

822 */

823 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))

824

825 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))

826 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))

827 #define SC_UPDATE_SCISSOR (0x1<<1)

828 #define SC_ENABLE_MASK (0x1<<0)

829 #define SC_ENABLE (0x1<<0)

830 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))

831 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))

832 #define SCI_YMIN_MASK (0xffff<<16)

833 #define SCI_XMIN_MASK (0xffff<<0)

834 #define SCI_YMAX_MASK (0xffff<<16)

835 #define SCI_XMAX_MASK (0xffff<<0)

836 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))

837 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)

838 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)

839 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))

840 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)

841 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)

842 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)

843 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))

844 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)

845 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)

846 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)

847 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)

848 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)

849 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)

850 #define BLT_DEPTH_8 (0<<24)

851 #define BLT_DEPTH_16_565 (1<<24)

852 #define BLT_DEPTH_16_1555 (2<<24)

853 #define BLT_DEPTH_32 (3<<24)

854 #define BLT_ROP_GXCOPY (0xcc<<16)

855 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */

856 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */

857 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)

858 #define ASYNC_FLIP (1<<22)

859 #define DISPLAY_PLANE_A (0<<20)

860 #define DISPLAY_PLANE_B (1<<20)

861

862 /*

863 * Instruction and interrupt control regs

864 */

865

866 #define PRB0_TAIL 0x02030

867 #define PRB0_HEAD 0x02034

868 #define PRB0_START 0x02038

869 #define PRB0_CTL 0x0203c

870 #define TAIL_ADDR 0x001FFFF8

871 #define HEAD_WRAP_COUNT 0xFFE00000

872 #define HEAD_WRAP_ONE 0x00200000

873 #define HEAD_ADDR 0x001FFFFC

874 #define RING_NR_PAGES 0x001FF000

875 #define RING_REPORT_MASK 0x00000006

876 #define RING_REPORT_64K 0x00000002

877 #define RING_REPORT_128K 0x00000004

878 #define RING_NO_REPORT 0x00000000

879 #define RING_VALID_MASK 0x00000001

880 #define RING_VALID 0x00000001

881 #define RING_INVALID 0x00000000

882 #define PRB1_TAIL 0x02040 /* 915+ only */

883 #define PRB1_HEAD 0x02044 /* 915+ only */

884 #define PRB1_START 0x02048 /* 915+ only */

885 #define PRB1_CTL 0x0204c /* 915+ only */

886 #define ACTHD_I965 0x02074

887 #define HWS_PGA 0x02080

888 #define HWS_ADDRESS_MASK 0xfffff000

889 #define HWS_START_ADDRESS_SHIFT 4

890 #define IPEIR 0x02088

891 #define NOPID 0x02094

892 #define HWSTAM 0x02098

893 #define SCPD0 0x0209c /* 915+ only */

894 #define IER 0x020a0

895 #define IIR 0x020a4

896 #define IMR 0x020a8

897 #define ISR 0x020ac

898 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)

899 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)

900 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)

901 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)

902 #define I915_HWB_OOM_INTERRUPT (1<<13)

903 #define I915_SYNC_STATUS_INTERRUPT (1<<12)

904 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)

905 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)

906 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)

907 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)

908 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)

909 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)

910 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)

911 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)

912 #define I915_DEBUG_INTERRUPT (1<<2)

913 #define I915_USER_INTERRUPT (1<<1)

914 #define I915_ASLE_INTERRUPT (1<<0)

915 #define EIR 0x020b0

916 #define EMR 0x020b4

917 #define ESR 0x020b8

918 #define INSTPM 0x020c0

919 #define ACTHD 0x020c8

920 #define FW_BLC 0x020d8

921 #define FW_BLC_SELF 0x020e0 /* 915+ only */

922 #define MI_ARB_STATE 0x020e4 /* 915+ only */

923 #define CACHE_MODE_0 0x02120 /* 915+ only */

924 #define CM0_MASK_SHIFT 16

925 #define CM0_IZ_OPT_DISABLE (1<<6)

926 #define CM0_ZR_OPT_DISABLE (1<<5)

927 #define CM0_DEPTH_EVICT_DISABLE (1<<4)

928 #define CM0_COLOR_EVICT_DISABLE (1<<3)

929 #define CM0_DEPTH_WRITE_DISABLE (1<<1)

930 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)

931 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */

932

933 /*

934 * Framebuffer compression (915+ only)

935 */

936

937 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */

938 #define FBC_LL_BASE 0x03204 /* 4k page aligned */

939 #define FBC_CONTROL 0x03208

940 #define FBC_CTL_EN (1<<31)

941 #define FBC_CTL_PERIODIC (1<<30)

942 #define FBC_CTL_INTERVAL_SHIFT (16)

943 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)

944 #define FBC_CTL_STRIDE_SHIFT (5)

945 #define FBC_CTL_FENCENO (1<<0)

946 #define FBC_COMMAND 0x0320c

947 #define FBC_CMD_COMPRESS (1<<0)

948 #define FBC_STATUS 0x03210

949 #define FBC_STAT_COMPRESSING (1<<31)

950 #define FBC_STAT_COMPRESSED (1<<30)

951 #define FBC_STAT_MODIFIED (1<<29)

952 #define FBC_STAT_CURRENT_LINE (1<<0)

953 #define FBC_CONTROL2 0x03214

954 #define FBC_CTL_FENCE_DBL (0<<4)

955 #define FBC_CTL_IDLE_IMM (0<<2)

956 #define FBC_CTL_IDLE_FULL (1<<2)

957 #define FBC_CTL_IDLE_LINE (2<<2)

958 #define FBC_CTL_IDLE_DEBUG (3<<2)

959 #define FBC_CTL_CPU_FENCE (1<<1)

960 #define FBC_CTL_PLANEA (0<<0)

961 #define FBC_CTL_PLANEB (1<<0)

962 #define FBC_FENCE_OFF 0x0321b

963

964 #define FBC_LL_SIZE (1536)

965

966 /*

967 * GPIO regs

968 */

969 #define GPIOA 0x5010

970 #define GPIOB 0x5014

971 #define GPIOC 0x5018

972 #define GPIOD 0x501c

973 #define GPIOE 0x5020

974 #define GPIOF 0x5024

975 #define GPIOG 0x5028

976 #define GPIOH 0x502c

977 # define GPIO_CLOCK_DIR_MASK (1 << 0)

978 # define GPIO_CLOCK_DIR_IN (0 << 1)

979 # define GPIO_CLOCK_DIR_OUT (1 << 1)

980 # define GPIO_CLOCK_VAL_MASK (1 << 2)

981 # define GPIO_CLOCK_VAL_OUT (1 << 3)

982 # define GPIO_CLOCK_VAL_IN (1 << 4)

983 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)

984 # define GPIO_DATA_DIR_MASK (1 << 8)

985 # define GPIO_DATA_DIR_IN (0 << 9)

986 # define GPIO_DATA_DIR_OUT (1 << 9)

987 # define GPIO_DATA_VAL_MASK (1 << 10)

988 # define GPIO_DATA_VAL_OUT (1 << 11)

989 # define GPIO_DATA_VAL_IN (1 << 12)

990 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)

991

992 /*

993 * Clock control & power management

994 */

995

996 #define VGA0 0x6000

997 #define VGA1 0x6004

998 #define VGA_PD 0x6010

999 #define VGA0_PD_P2_DIV_4 (1 << 7)

1000 #define VGA0_PD_P1_DIV_2 (1 << 5)

1001 #define VGA0_PD_P1_SHIFT 0

1002 #define VGA0_PD_P1_MASK (0x1f << 0)

1003 #define VGA1_PD_P2_DIV_4 (1 << 15)

1004 #define VGA1_PD_P1_DIV_2 (1 << 13)

1005 #define VGA1_PD_P1_SHIFT 8

1006 #define VGA1_PD_P1_MASK (0x1f << 8)

1007 #define DPLL_A 0x06014

1008 #define DPLL_B 0x06018

1009 #define DPLL_VCO_ENABLE (1 << 31)

1010 #define DPLL_DVO_HIGH_SPEED (1 << 30)

1011 #define DPLL_SYNCLOCK_ENABLE (1 << 29)

1012 #define DPLL_VGA_MODE_DIS (1 << 28)

1013 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */

1014 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */

1015 #define DPLL_MODE_MASK (3 << 26)

1016 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */

1017 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */

1018 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */

1019 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */

1020 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */

1021 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */

1022

1023 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)

1024 #define I915_CRC_ERROR_ENABLE (1UL<<29)

1025 #define I915_CRC_DONE_ENABLE (1UL<<28)

1026 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)

1027 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)

1028 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)

1029 #define I915_DPST_EVENT_ENABLE (1UL<<23)

1030 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)

1031 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)

1032 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)

1033 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */

1034 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)

1035 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)

1036 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)

1037 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)

1038 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)

1039 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)

1040 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)

1041 #define I915_DPST_EVENT_STATUS (1UL<<7)

1042 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)

1043 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)

1044 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)

1045 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */

1046 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)

1047 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)

1048

1049 #define SRX_INDEX 0x3c4

1050 #define SRX_DATA 0x3c5

1051 #define SR01 1

1052 #define SR01_SCREEN_OFF (1<<5)

1053

1054 #define PPCR 0x61204

1055 #define PPCR_ON (1<<0)

1056

1057 #define DVOB 0x61140

1058 #define DVOB_ON (1<<31)

1059 #define DVOC 0x61160

1060 #define DVOC_ON (1<<31)

1061 #define LVDS 0x61180

1062 #define LVDS_ON (1<<31)

1063

1064 #define ADPA 0x61100

1065 #define ADPA_DPMS_MASK (~(3<<10))

1066 #define ADPA_DPMS_ON (0<<10)

1067 #define ADPA_DPMS_SUSPEND (1<<10)

1068 #define ADPA_DPMS_STANDBY (2<<10)

1069 #define ADPA_DPMS_OFF (3<<10)

1070

1071 #define RING_TAIL 0x00

1072 #define TAIL_ADDR 0x001FFFF8

1073 #define RING_HEAD 0x04

1074 #define HEAD_WRAP_COUNT 0xFFE00000

1075 #define HEAD_WRAP_ONE 0x00200000

1076 #define HEAD_ADDR 0x001FFFFC

1077 #define RING_START 0x08

1078 #define START_ADDR 0xFFFFF000

1079 #define RING_LEN 0x0C

1080 #define RING_NR_PAGES 0x001FF000

1081 #define RING_REPORT_MASK 0x00000006

1082 #define RING_REPORT_64K 0x00000002

1083 #define RING_REPORT_128K 0x00000004

1084 #define RING_NO_REPORT 0x00000000

1085 #define RING_VALID_MASK 0x00000001

1086 #define RING_VALID 0x00000001

1087 #define RING_INVALID 0x00000000

1088

1089 /* Scratch pad debug 0 reg:

1090 */

1091 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000

1092 /*

1093 * The i830 generation, in LVDS mode, defines P1 as the bit number set within

1094 * this field (only one bit may be set).

1095 */

1096 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000

1097 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16

1098 /* i830, required in DVO non-gang */

1099 #define PLL_P2_DIVIDE_BY_4 (1 << 23)

1100 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */

1101 #define PLL_REF_INPUT_DREFCLK (0 << 13)

1102 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */

1103 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */

1104 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)

1105 #define PLL_REF_INPUT_MASK (3 << 13)

1106 #define PLL_LOAD_PULSE_PHASE_SHIFT 9

1107 /*

1108 * Parallel to Serial Load Pulse phase selection.

1109 * Selects the phase for the 10X DPLL clock for the PCIe

1110 * digital display port. The range is 4 to 13; 10 or more

1111 * is just a flip delay. The default is 6

1112 */

1113 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)

1114 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)

1115 /*

1116 * SDVO multiplier for 945G/GM. Not used on 965.

1117 */

1118 #define SDVO_MULTIPLIER_MASK 0x000000ff

1119 #define SDVO_MULTIPLIER_SHIFT_HIRES 4

1120 #define SDVO_MULTIPLIER_SHIFT_VGA 0

1121 #define DPLL_A_MD 0x0601c /* 965+ only */

1122 /*

1123 * UDI pixel divider, controlling how many pixels are stuffed into a packet.

1124 *

1125 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.

1126 */

1127 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000

1128 #define DPLL_MD_UDI_DIVIDER_SHIFT 24

1129 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */

1130 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000

1131 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16

1132 /*

1133 * SDVO/UDI pixel multiplier.

1134 *

1135 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus

1136 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate

1137 * modes, the bus rate would be below the limits, so SDVO allows for stuffing

1138 * dummy bytes in the datastream at an increased clock rate, with both sides of

1139 * the link knowing how many bytes are fill.

1140 *

1141 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock

1142 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be

1143 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and

1144 * through an SDVO command.

1145 *

1146 * This register field has values of multiplication factor minus 1, with

1147 * a maximum multiplier of 5 for SDVO.

1148 */

1149 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00

1150 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8

1151 /*

1152 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.

1153 * This best be set to the default value (3) or the CRT won't work. No,

1154 * I don't entirely understand what this does...

1155 */

1156 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f

1157 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0

1158 #define DPLL_B_MD 0x06020 /* 965+ only */

1159 #define FPA0 0x06040

1160 #define FPA1 0x06044

1161 #define FPB0 0x06048

1162 #define FPB1 0x0604c

1163 #define FP_N_DIV_MASK 0x003f0000

1164 #define FP_N_DIV_SHIFT 16

1165 #define FP_M1_DIV_MASK 0x00003f00

1166 #define FP_M1_DIV_SHIFT 8

1167 #define FP_M2_DIV_MASK 0x0000003f

1168 #define FP_M2_DIV_SHIFT 0

1169 #define DPLL_TEST 0x606c

1170 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)

1171 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)

1172 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)

1173 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)

1174 #define DPLLB_TEST_N_BYPASS (1 << 19)

1175 #define DPLLB_TEST_M_BYPASS (1 << 18)

1176 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)

1177 #define DPLLA_TEST_N_BYPASS (1 << 3)

1178 #define DPLLA_TEST_M_BYPASS (1 << 2)

1179 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)

1180 #define D_STATE 0x6104

1181 #define CG_2D_DIS 0x6200

1182 #define CG_3D_DIS 0x6204

1183

1184 /*

1185 * Palette regs

1186 */

1187

1188 #define PALETTE_A 0x0a000

1189 #define PALETTE_B 0x0a800

1190

1191 /*

1192 * Overlay regs

1193 */

1194

1195 #define OVADD 0x30000

1196 #define DOVSTA 0x30008

1197 #define OC_BUF (0x3<<20)

1198 #define OGAMC5 0x30010

1199 #define OGAMC4 0x30014

1200 #define OGAMC3 0x30018

1201 #define OGAMC2 0x3001c

1202 #define OGAMC1 0x30020

1203 #define OGAMC0 0x30024

1204

1205 /*

1206 * Display engine regs

1207 */

1208

1209 /* Pipe A timing regs */

1210 #define HTOTAL_A 0x60000

1211 #define HBLANK_A 0x60004

1212 #define HSYNC_A 0x60008

1213 #define VTOTAL_A 0x6000c

1214 #define VBLANK_A 0x60010

1215 #define VSYNC_A 0x60014

1216 #define PIPEASRC 0x6001c

1217 #define BCLRPAT_A 0x60020

1218

1219 /* Pipe B timing regs */

1220 #define HTOTAL_B 0x61000

1221 #define HBLANK_B 0x61004

1222 #define HSYNC_B 0x61008

1223 #define VTOTAL_B 0x6100c

1224 #define VBLANK_B 0x61010

1225 #define VSYNC_B 0x61014

1226 #define PIPEBSRC 0x6101c

1227 #define BCLRPAT_B 0x61020

1228

1229 /* VGA port control */

1230 #define ADPA 0x61100

1231 #define ADPA_DAC_ENABLE (1<<31)

1232 #define ADPA_DAC_DISABLE 0

1233 #define ADPA_PIPE_SELECT_MASK (1<<30)

1234 #define ADPA_PIPE_A_SELECT 0

1235 #define ADPA_PIPE_B_SELECT (1<<30)

1236 #define ADPA_USE_VGA_HVPOLARITY (1<<15)

1237 #define ADPA_SETS_HVPOLARITY 0

1238 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)

1239 #define ADPA_VSYNC_CNTL_ENABLE 0

1240 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)

1241 #define ADPA_HSYNC_CNTL_ENABLE 0

1242 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)

1243 #define ADPA_VSYNC_ACTIVE_LOW 0

1244 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)

1245 #define ADPA_HSYNC_ACTIVE_LOW 0

1246 #define ADPA_DPMS_MASK (~(3<<10))

1247 #define ADPA_DPMS_ON (0<<10)

1248 #define ADPA_DPMS_SUSPEND (1<<10)

1249 #define ADPA_DPMS_STANDBY (2<<10)

1250 #define ADPA_DPMS_OFF (3<<10)

1251

1252 /* Hotplug control (945+ only) */

1253 #define PORT_HOTPLUG_EN 0x61110

1254 #define SDVOB_HOTPLUG_INT_EN (1 << 26)

1255 #define SDVOC_HOTPLUG_INT_EN (1 << 25)

1256 #define TV_HOTPLUG_INT_EN (1 << 18)

1257 #define CRT_HOTPLUG_INT_EN (1 << 9)

1258 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)

1259

1260 #define PORT_HOTPLUG_STAT 0x61114

1261 #define CRT_HOTPLUG_INT_STATUS (1 << 11)

1262 #define TV_HOTPLUG_INT_STATUS (1 << 10)

1263 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)

1264 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)

1265 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)

1266 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)

1267 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)

1268 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)

1269

1270 /* SDVO port control */

1271 #define SDVOB 0x61140

1272 #define SDVOC 0x61160

1273 #define SDVO_ENABLE (1 << 31)

1274 #define SDVO_PIPE_B_SELECT (1 << 30)

1275 #define SDVO_STALL_SELECT (1 << 29)

1276 #define SDVO_INTERRUPT_ENABLE (1 << 26)

1277 /**

1278 * 915G/GM SDVO pixel multiplier.

1279 *

1280 * Programmed value is multiplier - 1, up to 5x.

1281 *

1282 * \sa DPLL_MD_UDI_MULTIPLIER_MASK

1283 */

1284 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)

1285 #define SDVO_PORT_MULTIPLY_SHIFT 23

1286 #define SDVO_PHASE_SELECT_MASK (15 << 19)

1287 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)

1288 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)

1289 #define SDVOC_GANG_MODE (1 << 16)

1290 #define SDVO_BORDER_ENABLE (1 << 7)

1291 #define SDVOB_PCIE_CONCURRENCY (1 << 3)

1292 #define SDVO_DETECTED (1 << 2)

1293 /* Bits to be preserved when writing */

1294 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))

1295 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))

1296

1297 /* DVO port control */

1298 #define DVOA 0x61120

1299 #define DVOB 0x61140

1300 #define DVOC 0x61160

1301 #define DVO_ENABLE (1 << 31)

1302 #define DVO_PIPE_B_SELECT (1 << 30)

1303 #define DVO_PIPE_STALL_UNUSED (0 << 28)

1304 #define DVO_PIPE_STALL (1 << 28)

1305 #define DVO_PIPE_STALL_TV (2 << 28)

1306 #define DVO_PIPE_STALL_MASK (3 << 28)

1307 #define DVO_USE_VGA_SYNC (1 << 15)

1308 #define DVO_DATA_ORDER_I740 (0 << 14)

1309 #define DVO_DATA_ORDER_FP (1 << 14)

1310 #define DVO_VSYNC_DISABLE (1 << 11)

1311 #define DVO_HSYNC_DISABLE (1 << 10)

1312 #define DVO_VSYNC_TRISTATE (1 << 9)

1313 #define DVO_HSYNC_TRISTATE (1 << 8)

1314 #define DVO_BORDER_ENABLE (1 << 7)

1315 #define DVO_DATA_ORDER_GBRG (1 << 6)

1316 #define DVO_DATA_ORDER_RGGB (0 << 6)

1317 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)

1318 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)

1319 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)

1320 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)

1321 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)

1322 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */

1323 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */

1324 #define DVO_PRESERVE_MASK (0x7<<24)

1325 #define DVOA_SRCDIM 0x61124

1326 #define DVOB_SRCDIM 0x61144

1327 #define DVOC_SRCDIM 0x61164

1328 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12

1329 #define DVO_SRCDIM_VERTICAL_SHIFT 0

1330

1331 /* LVDS port control */

1332 #define LVDS 0x61180

1333 /*

1334 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as

1335 * the DPLL semantics change when the LVDS is assigned to that pipe.

1336 */

1337 #define LVDS_PORT_EN (1 << 31)

1338 /* Selects pipe B for LVDS data. Must be set on pre-965. */

1339 #define LVDS_PIPEB_SELECT (1 << 30)

1340 /*

1341 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per

1342 * pixel.

1343 */

1344 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)

1345 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)

1346 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)

1347 /*

1348 * Controls the A3 data pair, which contains the additional LSBs for 24 bit

1349 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be

1350 * on.

1351 */

1352 #define LVDS_A3_POWER_MASK (3 << 6)

1353 #define LVDS_A3_POWER_DOWN (0 << 6)

1354 #define LVDS_A3_POWER_UP (3 << 6)

1355 /*

1356 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP

1357 * is set.

1358 */

1359 #define LVDS_CLKB_POWER_MASK (3 << 4)

1360 #define LVDS_CLKB_POWER_DOWN (0 << 4)

1361 #define LVDS_CLKB_POWER_UP (3 << 4)

1362 /*

1363 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2

1364 * setting for whether we are in dual-channel mode. The B3 pair will

1365 * additionally only be powered up when LVDS_A3_POWER_UP is set.

1366 */

1367 #define LVDS_B0B3_POWER_MASK (3 << 2)

1368 #define LVDS_B0B3_POWER_DOWN (0 << 2)

1369 #define LVDS_B0B3_POWER_UP (3 << 2)

1370

1371 /* Panel power sequencing */

1372 #define PP_STATUS 0x61200

1373 #define PP_ON (1 << 31)

1374 /*

1375 * Indicates that all dependencies of the panel are on:

1376 *

1377 * - PLL enabled

1378 * - pipe enabled

1379 * - LVDS/DVOB/DVOC on

1380 */

1381 #define PP_READY (1 << 30)

1382 #define PP_SEQUENCE_NONE (0 << 28)

1383 #define PP_SEQUENCE_ON (1 << 28)

1384 #define PP_SEQUENCE_OFF (2 << 28)

1385 #define PP_SEQUENCE_MASK 0x30000000

1386 #define PP_CONTROL 0x61204

1387 #define POWER_TARGET_ON (1 << 0)

1388 #define PP_ON_DELAYS 0x61208

1389 #define PP_OFF_DELAYS 0x6120c

1390 #define PP_DIVISOR 0x61210

1391

1392 /* Panel fitting */

1393 #define PFIT_CONTROL 0x61230

1394 #define PFIT_ENABLE (1 << 31)

1395 #define PFIT_PIPE_MASK (3 << 29)

1396 #define PFIT_PIPE_SHIFT 29

1397 #define VERT_INTERP_DISABLE (0 << 10)

1398 #define VERT_INTERP_BILINEAR (1 << 10)

1399 #define VERT_INTERP_MASK (3 << 10)

1400 #define VERT_AUTO_SCALE (1 << 9)

1401 #define HORIZ_INTERP_DISABLE (0 << 6)

1402 #define HORIZ_INTERP_BILINEAR (1 << 6)

1403 #define HORIZ_INTERP_MASK (3 << 6)

1404 #define HORIZ_AUTO_SCALE (1 << 5)

1405 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)

1406 #define PFIT_PGM_RATIOS 0x61234

1407 #define PFIT_VERT_SCALE_MASK 0xfff00000

1408 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0

1409 #define PFIT_AUTO_RATIOS 0x61238

1410

1411 /* Backlight control */

1412 #define BLC_PWM_CTL 0x61254

1413 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)

1414 #define BLC_PWM_CTL2 0x61250 /* 965+ only */

1415 /*

1416 * This is the most significant 15 bits of the number of backlight cycles in a

1417 * complete cycle of the modulated backlight control.

1418 *

1419 * The actual value is this field multiplied by two.

1420 */

1421 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)

1422 #define BLM_LEGACY_MODE (1 << 16)

1423 /*

1424 * This is the number of cycles out of the backlight modulation cycle for which

1425 * the backlight is on.

1426 *

1427 * This field must be no greater than the number of cycles in the complete

1428 * backlight modulation cycle.

1429 */

1430 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)

1431 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)

1432

1433 /* TV port control */

1434 #define TV_CTL 0x68000

1435 /** Enables the TV encoder */

1436 # define TV_ENC_ENABLE (1 << 31)

1437 /** Sources the TV encoder input from pipe B instead of A. */

1438 # define TV_ENC_PIPEB_SELECT (1 << 30)

1439 /** Outputs composite video (DAC A only) */

1440 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)

1441 /** Outputs SVideo video (DAC B/C) */

1442 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)

1443 /** Outputs Component video (DAC A/B/C) */

1444 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)

1445 /** Outputs Composite and SVideo (DAC A/B/C) */

1446 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)

1447 # define TV_TRILEVEL_SYNC (1 << 21)

1448 /** Enables slow sync generation (945GM only) */

1449 # define TV_SLOW_SYNC (1 << 20)

1450 /** Selects 4x oversampling for 480i and 576p */

1451 # define TV_OVERSAMPLE_4X (0 << 18)

1452 /** Selects 2x oversampling for 720p and 1080i */

1453 # define TV_OVERSAMPLE_2X (1 << 18)

1454 /** Selects no oversampling for 1080p */

1455 # define TV_OVERSAMPLE_NONE (2 << 18)

1456 /** Selects 8x oversampling */

1457 # define TV_OVERSAMPLE_8X (3 << 18)

1458 /** Selects progressive mode rather than interlaced */

1459 # define TV_PROGRESSIVE (1 << 17)

1460 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */

1461 # define TV_PAL_BURST (1 << 16)

1462 /** Field for setting delay of Y compared to C */

1463 # define TV_YC_SKEW_MASK (7 << 12)

1464 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */

1465 # define TV_ENC_SDP_FIX (1 << 11)

1466 /**

1467 * Enables a fix for the 915GM only.

1468 *

1469 * Not sure what it does.

1470 */

1471 # define TV_ENC_C0_FIX (1 << 10)

1472 /** Bits that must be preserved by software */

1473 # define TV_CTL_SAVE ((3 << 8) | (3 << 6))

1474 # define TV_FUSE_STATE_MASK (3 << 4)

1475 /** Read-only state that reports all features enabled */

1476 # define TV_FUSE_STATE_ENABLED (0 << 4)

1477 /** Read-only state that reports that Macrovision is disabled in hardware*/

1478 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)

1479 /** Read-only state that reports that TV-out is disabled in hardware. */

1480 # define TV_FUSE_STATE_DISABLED (2 << 4)

1481 /** Normal operation */

1482 # define TV_TEST_MODE_NORMAL (0 << 0)

1483 /** Encoder test pattern 1 - combo pattern */

1484 # define TV_TEST_MODE_PATTERN_1 (1 << 0)

1485 /** Encoder test pattern 2 - full screen vertical 75% color bars */

1486 # define TV_TEST_MODE_PATTERN_2 (2 << 0)

1487 /** Encoder test pattern 3 - full screen horizontal 75% color bars */

1488 # define TV_TEST_MODE_PATTERN_3 (3 << 0)

1489 /** Encoder test pattern 4 - random noise */

1490 # define TV_TEST_MODE_PATTERN_4 (4 << 0)

1491 /** Encoder test pattern 5 - linear color ramps */

1492 # define TV_TEST_MODE_PATTERN_5 (5 << 0)

1493 /**

1494 * This test mode forces the DACs to 50% of full output.

1495 *

1496 * This is used for load detection in combination with TVDAC_SENSE_MASK

1497 */

1498 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)

1499 # define TV_TEST_MODE_MASK (7 << 0)

1500

1501 #define TV_DAC 0x68004

1502 /**

1503 * Reports that DAC state change logic has reported change (RO).

1504 *

1505 * This gets cleared when TV_DAC_STATE_EN is cleared

1506 */

1507 # define TVDAC_STATE_CHG (1 << 31)

1508 # define TVDAC_SENSE_MASK (7 << 28)

1509 /** Reports that DAC A voltage is above the detect threshold */

1510 # define TVDAC_A_SENSE (1 << 30)

1511 /** Reports that DAC B voltage is above the detect threshold */

1512 # define TVDAC_B_SENSE (1 << 29)

1513 /** Reports that DAC C voltage is above the detect threshold */

1514 # define TVDAC_C_SENSE (1 << 28)

1515 /**

1516 * Enables DAC state detection logic, for load-based TV detection.

1517 *

1518 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set

1519 * to off, for load detection to work.

1520 */

1521 # define TVDAC_STATE_CHG_EN (1 << 27)

1522 /** Sets the DAC A sense value to high */

1523 # define TVDAC_A_SENSE_CTL (1 << 26)

1524 /** Sets the DAC B sense value to high */

1525 # define TVDAC_B_SENSE_CTL (1 << 25)

1526 /** Sets the DAC C sense value to high */

1527 # define TVDAC_C_SENSE_CTL (1 << 24)

1528 /** Overrides the ENC_ENABLE and DAC voltage levels */

1529 # define DAC_CTL_OVERRIDE (1 << 7)

1530 /** Sets the slew rate. Must be preserved in software */

1531 # define ENC_TVDAC_SLEW_FAST (1 << 6)

1532 # define DAC_A_1_3_V (0 << 4)

1533 # define DAC_A_1_1_V (1 << 4)

1534 # define DAC_A_0_7_V (2 << 4)

1535 # define DAC_A_OFF (3 << 4)

1536 # define DAC_B_1_3_V (0 << 2)

1537 # define DAC_B_1_1_V (1 << 2)

1538 # define DAC_B_0_7_V (2 << 2)

1539 # define DAC_B_OFF (3 << 2)

1540 # define DAC_C_1_3_V (0 << 0)

1541 # define DAC_C_1_1_V (1 << 0)

1542 # define DAC_C_0_7_V (2 << 0)

1543 # define DAC_C_OFF (3 << 0)

1544

1545 /**

1546 * CSC coefficients are stored in a floating point format with 9 bits of

1547 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,

1548 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with

1549 * -1 (0x3) being the only legal negative value.

1550 */

1551 #define TV_CSC_Y 0x68010

1552 # define TV_RY_MASK 0x07ff0000

1553 # define TV_RY_SHIFT 16

1554 # define TV_GY_MASK 0x00000fff

1555 # define TV_GY_SHIFT 0

1556

1557 #define TV_CSC_Y2 0x68014

1558 # define TV_BY_MASK 0x07ff0000

1559 # define TV_BY_SHIFT 16

1560 /**

1561 * Y attenuation for component video.

1562 *

1563 * Stored in 1.9 fixed point.

1564 */

1565 # define TV_AY_MASK 0x000003ff

1566 # define TV_AY_SHIFT 0

1567

1568 #define TV_CSC_U 0x68018

1569 # define TV_RU_MASK 0x07ff0000

1570 # define TV_RU_SHIFT 16

1571 # define TV_GU_MASK 0x000007ff

1572 # define TV_GU_SHIFT 0

1573

1574 #define TV_CSC_U2 0x6801c

1575 # define TV_BU_MASK 0x07ff0000

1576 # define TV_BU_SHIFT 16

1577 /**

1578 * U attenuation for component video.

1579 *

1580 * Stored in 1.9 fixed point.

1581 */

1582 # define TV_AU_MASK 0x000003ff

1583 # define TV_AU_SHIFT 0

1584

1585 #define TV_CSC_V 0x68020

1586 # define TV_RV_MASK 0x0fff0000

1587 # define TV_RV_SHIFT 16

1588 # define TV_GV_MASK 0x000007ff

1589 # define TV_GV_SHIFT 0

1590

1591 #define TV_CSC_V2 0x68024

1592 # define TV_BV_MASK 0x07ff0000

1593 # define TV_BV_SHIFT 16

1594 /**

1595 * V attenuation for component video.

1596 *

1597 * Stored in 1.9 fixed point.

1598 */

1599 # define TV_AV_MASK 0x000007ff

1600 # define TV_AV_SHIFT 0

1601

1602 #define TV_CLR_KNOBS 0x68028

1603 /** 2s-complement brightness adjustment */

1604 # define TV_BRIGHTNESS_MASK 0xff000000

1605 # define TV_BRIGHTNESS_SHIFT 24

1606 /** Contrast adjustment, as a 2.6 unsigned floating point number */

1607 # define TV_CONTRAST_MASK 0x00ff0000

1608 # define TV_CONTRAST_SHIFT 16

1609 /** Saturation adjustment, as a 2.6 unsigned floating point number */

1610 # define TV_SATURATION_MASK 0x0000ff00

1611 # define TV_SATURATION_SHIFT 8

1612 /** Hue adjustment, as an integer phase angle in degrees */

1613 # define TV_HUE_MASK 0x000000ff

1614 # define TV_HUE_SHIFT 0

1615

1616 #define TV_CLR_LEVEL 0x6802c

1617 /** Controls the DAC level for black */

1618 # define TV_BLACK_LEVEL_MASK 0x01ff0000

1619 # define TV_BLACK_LEVEL_SHIFT 16

1620 /** Controls the DAC level for blanking */

1621 # define TV_BLANK_LEVEL_MASK 0x000001ff

1622 # define TV_BLANK_LEVEL_SHIFT 0

1623

1624 #define TV_H_CTL_1 0x68030

1625 /** Number of pixels in the hsync. */

1626 # define TV_HSYNC_END_MASK 0x1fff0000

1627 # define TV_HSYNC_END_SHIFT 16

1628 /** Total number of pixels minus one in the line (display and blanking). */

1629 # define TV_HTOTAL_MASK 0x00001fff

1630 # define TV_HTOTAL_SHIFT 0

1631

1632 #define TV_H_CTL_2 0x68034

1633 /** Enables the colorburst (needed for non-component color) */

1634 # define TV_BURST_ENA (1 << 31)

1635 /** Offset of the colorburst from the start of hsync, in pixels minus one. */

1636 # define TV_HBURST_START_SHIFT 16

1637 # define TV_HBURST_START_MASK 0x1fff0000

1638 /** Length of the colorburst */

1639 # define TV_HBURST_LEN_SHIFT 0

1640 # define TV_HBURST_LEN_MASK 0x0001fff

1641

1642 #define TV_H_CTL_3 0x68038

1643 /** End of hblank, measured in pixels minus one from start of hsync */

1644 # define TV_HBLANK_END_SHIFT 16

1645 # define TV_HBLANK_END_MASK 0x1fff0000

1646 /** Start of hblank, measured in pixels minus one from start of hsync */

1647 # define TV_HBLANK_START_SHIFT 0

1648 # define TV_HBLANK_START_MASK 0x0001fff

1649

1650 #define TV_V_CTL_1 0x6803c

1651 /** XXX */

1652 # define TV_NBR_END_SHIFT 16

1653 # define TV_NBR_END_MASK 0x07ff0000

1654 /** XXX */

1655 # define TV_VI_END_F1_SHIFT 8

1656 # define TV_VI_END_F1_MASK 0x00003f00

1657 /** XXX */

1658 # define TV_VI_END_F2_SHIFT 0

1659 # define TV_VI_END_F2_MASK 0x0000003f

1660

1661 #define TV_V_CTL_2 0x68040

1662 /** Length of vsync, in half lines */

1663 # define TV_VSYNC_LEN_MASK 0x07ff0000

1664 # define TV_VSYNC_LEN_SHIFT 16

1665 /** Offset of the start of vsync in field 1, measured in one less than the

1666 * number of half lines.

1667 */

1668 # define TV_VSYNC_START_F1_MASK 0x00007f00

1669 # define TV_VSYNC_START_F1_SHIFT 8

1670 /**

1671 * Offset of the start of vsync in field 2, measured in one less than the

1672 * number of half lines.

1673 */

1674 # define TV_VSYNC_START_F2_MASK 0x0000007f

1675 # define TV_VSYNC_START_F2_SHIFT 0

1676

1677 #define TV_V_CTL_3 0x68044

1678 /** Enables generation of the equalization signal */

1679 # define TV_EQUAL_ENA (1 << 31)

1680 /** Length of vsync, in half lines */

1681 # define TV_VEQ_LEN_MASK 0x007f0000

1682 # define TV_VEQ_LEN_SHIFT 16

1683 /** Offset of the start of equalization in field 1, measured in one less than

1684 * the number of half lines.

1685 */

1686 # define TV_VEQ_START_F1_MASK 0x0007f00

1687 # define TV_VEQ_START_F1_SHIFT 8

1688 /**

1689 * Offset of the start of equalization in field 2, measured in one less than

1690 * the number of half lines.

1691 */

1692 # define TV_VEQ_START_F2_MASK 0x000007f

1693 # define TV_VEQ_START_F2_SHIFT 0

1694

1695 #define TV_V_CTL_4 0x68048

1696 /**

1697 * Offset to start of vertical colorburst, measured in one less than the

1698 * number of lines from vertical start.

1699 */

1700 # define TV_VBURST_START_F1_MASK 0x003f0000

1701 # define TV_VBURST_START_F1_SHIFT 16

1702 /**

1703 * Offset to the end of vertical colorburst, measured in one less than the

1704 * number of lines from the start of NBR.

1705 */

1706 # define TV_VBURST_END_F1_MASK 0x000000ff

1707 # define TV_VBURST_END_F1_SHIFT 0

1708

1709 #define TV_V_CTL_5 0x6804c

1710 /**

1711 * Offset to start of vertical colorburst, measured in one less than the

1712 * number of lines from vertical start.

1713 */

1714 # define TV_VBURST_START_F2_MASK 0x003f0000

1715 # define TV_VBURST_START_F2_SHIFT 16

1716 /**

1717 * Offset to the end of vertical colorburst, measured in one less than the

1718 * number of lines from the start of NBR.

1719 */

1720 # define TV_VBURST_END_F2_MASK 0x000000ff

1721 # define TV_VBURST_END_F2_SHIFT 0

1722

1723 #define TV_V_CTL_6 0x68050

1724 /**

1725 * Offset to start of vertical colorburst, measured in one less than the

1726 * number of lines from vertical start.

1727 */

1728 # define TV_VBURST_START_F3_MASK 0x003f0000

1729 # define TV_VBURST_START_F3_SHIFT 16

1730 /**

1731 * Offset to the end of vertical colorburst, measured in one less than the

1732 * number of lines from the start of NBR.

1733 */

1734 # define TV_VBURST_END_F3_MASK 0x000000ff

1735 # define TV_VBURST_END_F3_SHIFT 0

1736

1737 #define TV_V_CTL_7 0x68054

1738 /**

1739 * Offset to start of vertical colorburst, measured in one less than the

1740 * number of lines from vertical start.

1741 */

1742 # define TV_VBURST_START_F4_MASK 0x003f0000

1743 # define TV_VBURST_START_F4_SHIFT 16

1744 /**

1745 * Offset to the end of vertical colorburst, measured in one less than the

1746 * number of lines from the start of NBR.

1747 */

1748 # define TV_VBURST_END_F4_MASK 0x000000ff

1749 # define TV_VBURST_END_F4_SHIFT 0

1750

1751 #define TV_SC_CTL_1 0x68060

1752 /** Turns on the first subcarrier phase generation DDA */

1753 # define TV_SC_DDA1_EN (1 << 31)

1754 /** Turns on the first subcarrier phase generation DDA */

1755 # define TV_SC_DDA2_EN (1 << 30)

1756 /** Turns on the first subcarrier phase generation DDA */

1757 # define TV_SC_DDA3_EN (1 << 29)

1758 /** Sets the subcarrier DDA to reset frequency every other field */

1759 # define TV_SC_RESET_EVERY_2 (0 << 24)

1760 /** Sets the subcarrier DDA to reset frequency every fourth field */

1761 # define TV_SC_RESET_EVERY_4 (1 << 24)

1762 /** Sets the subcarrier DDA to reset frequency every eighth field */

1763 # define TV_SC_RESET_EVERY_8 (2 << 24)

1764 /** Sets the subcarrier DDA to never reset the frequency */

1765 # define TV_SC_RESET_NEVER (3 << 24)

1766 /** Sets the peak amplitude of the colorburst.*/

1767 # define TV_BURST_LEVEL_MASK 0x00ff0000

1768 # define TV_BURST_LEVEL_SHIFT 16

1769 /** Sets the increment of the first subcarrier phase generation DDA */

1770 # define TV_SCDDA1_INC_MASK 0x00000fff

1771 # define TV_SCDDA1_INC_SHIFT 0

1772

1773 #define TV_SC_CTL_2 0x68064

1774 /** Sets the rollover for the second subcarrier phase generation DDA */

1775 # define TV_SCDDA2_SIZE_MASK 0x7fff0000

1776 # define TV_SCDDA2_SIZE_SHIFT 16

1777 /** Sets the increent of the second subcarrier phase generation DDA */

1778 # define TV_SCDDA2_INC_MASK 0x00007fff

1779 # define TV_SCDDA2_INC_SHIFT 0

1780

1781 #define TV_SC_CTL_3 0x68068

1782 /** Sets the rollover for the third subcarrier phase generation DDA */

1783 # define TV_SCDDA3_SIZE_MASK 0x7fff0000

1784 # define TV_SCDDA3_SIZE_SHIFT 16

1785 /** Sets the increent of the third subcarrier phase generation DDA */

1786 # define TV_SCDDA3_INC_MASK 0x00007fff

1787 # define TV_SCDDA3_INC_SHIFT 0

1788

1789 #define TV_WIN_POS 0x68070

1790 /** X coordinate of the display from the start of horizontal active */

1791 # define TV_XPOS_MASK 0x1fff0000

1792 # define TV_XPOS_SHIFT 16

1793 /** Y coordinate of the display from the start of vertical active (NBR) */

1794 # define TV_YPOS_MASK 0x00000fff

1795 # define TV_YPOS_SHIFT 0

1796

1797 #define TV_WIN_SIZE 0x68074

1798 /** Horizontal size of the display window, measured in pixels*/

1799 # define TV_XSIZE_MASK 0x1fff0000

1800 # define TV_XSIZE_SHIFT 16

1801 /**

1802 * Vertical size of the display window, measured in pixels.

1803 *

1804 * Must be even for interlaced modes.

1805 */

1806 # define TV_YSIZE_MASK 0x00000fff

1807 # define TV_YSIZE_SHIFT 0

1808

1809 #define TV_FILTER_CTL_1 0x68080

1810 /**

1811 * Enables automatic scaling calculation.

1812 *

1813 * If set, the rest of the registers are ignored, and the calculated values can

1814 * be read back from the register.

1815 */

1816 # define TV_AUTO_SCALE (1 << 31)

1817 /**

1818 * Disables the vertical filter.

1819 *

1820 * This is required on modes more than 1024 pixels wide */

1821 # define TV_V_FILTER_BYPASS (1 << 29)

1822 /** Enables adaptive vertical filtering */

1823 # define TV_VADAPT (1 << 28)

1824 # define TV_VADAPT_MODE_MASK (3 << 26)

1825 /** Selects the least adaptive vertical filtering mode */

1826 # define TV_VADAPT_MODE_LEAST (0 << 26)

1827 /** Selects the moderately adaptive vertical filtering mode */

1828 # define TV_VADAPT_MODE_MODERATE (1 << 26)

1829 /** Selects the most adaptive vertical filtering mode */

1830 # define TV_VADAPT_MODE_MOST (3 << 26)

1831 /**

1832 * Sets the horizontal scaling factor.

1833 *

1834 * This should be the fractional part of the horizontal scaling factor divided

1835 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:

1836 *

1837 * (src width - 1) / ((oversample * dest width) - 1)

1838 */

1839 # define TV_HSCALE_FRAC_MASK 0x00003fff

1840 # define TV_HSCALE_FRAC_SHIFT 0

1841

1842 #define TV_FILTER_CTL_2 0x68084

1843 /**

1844 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.

1845 *

1846 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)

1847 */

1848 # define TV_VSCALE_INT_MASK 0x00038000

1849 # define TV_VSCALE_INT_SHIFT 15

1850 /**

1851 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.

1852 *

1853 * \sa TV_VSCALE_INT_MASK

1854 */

1855 # define TV_VSCALE_FRAC_MASK 0x00007fff

1856 # define TV_VSCALE_FRAC_SHIFT 0

1857

1858 #define TV_FILTER_CTL_3 0x68088

1859 /**

1860 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.

1861 *

1862 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))

1863 *

1864 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.

1865 */

1866 # define TV_VSCALE_IP_INT_MASK 0x00038000

1867 # define TV_VSCALE_IP_INT_SHIFT 15

1868 /**

1869 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.

1870 *

1871 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.

1872 *

1873 * \sa TV_VSCALE_IP_INT_MASK

1874 */

1875 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff

1876 # define TV_VSCALE_IP_FRAC_SHIFT 0

1877

1878 #define TV_CC_CONTROL 0x68090

1879 # define TV_CC_ENABLE (1 << 31)

1880 /**

1881 * Specifies which field to send the CC data in.

1882 *

1883 * CC data is usually sent in field 0.

1884 */

1885 # define TV_CC_FID_MASK (1 << 27)

1886 # define TV_CC_FID_SHIFT 27

1887 /** Sets the horizontal position of the CC data. Usually 135. */

1888 # define TV_CC_HOFF_MASK 0x03ff0000

1889 # define TV_CC_HOFF_SHIFT 16

1890 /** Sets the vertical position of the CC data. Usually 21 */

1891 # define TV_CC_LINE_MASK 0x0000003f

1892 # define TV_CC_LINE_SHIFT 0

1893

1894 #define TV_CC_DATA 0x68094

1895 # define TV_CC_RDY (1 << 31)

1896 /** Second word of CC data to be transmitted. */

1897 # define TV_CC_DATA_2_MASK 0x007f0000

1898 # define TV_CC_DATA_2_SHIFT 16

1899 /** First word of CC data to be transmitted. */

1900 # define TV_CC_DATA_1_MASK 0x0000007f

1901 # define TV_CC_DATA_1_SHIFT 0

1902

1903 #define TV_H_LUMA_0 0x68100

1904 #define TV_H_LUMA_59 0x681ec

1905 #define TV_H_CHROMA_0 0x68200

1906 #define TV_H_CHROMA_59 0x682ec

1907 #define TV_V_LUMA_0 0x68300

1908 #define TV_V_LUMA_42 0x683a8

1909 #define TV_V_CHROMA_0 0x68400

1910 #define TV_V_CHROMA_42 0x684a8

1911

1912 /* Display & cursor control */

1913

1914 /* Pipe A */

1915 #define PIPEADSL 0x70000

1916 #define PIPEACONF 0x70008

1917 #define PIPEACONF_ENABLE (1<<31)

1918 #define PIPEACONF_DISABLE 0

1919 #define PIPEACONF_DOUBLE_WIDE (1<<30)

1920 #define I965_PIPECONF_ACTIVE (1<<30)

1921 #define PIPEACONF_SINGLE_WIDE 0

1922 #define PIPEACONF_PIPE_UNLOCKED 0

1923 #define PIPEACONF_PIPE_LOCKED (1<<25)

1924 #define PIPEACONF_PALETTE 0

1925 #define PIPEACONF_GAMMA (1<<24)

1926 #define PIPECONF_FORCE_BORDER (1<<25)

1927 #define PIPECONF_PROGRESSIVE (0 << 21)

1928 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)

1929 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)

1930 #define PIPEASTAT 0x70024

1931 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)

1932 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)

1933 #define PIPE_CRC_DONE_ENABLE (1UL<<28)

1934 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)

1935 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)

1936 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)

1937 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)

1938 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)

1939 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)

1940 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)

1941 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)

1942 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */

1943 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */

1944 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)

1945 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)

1946 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)

1947 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)

1948 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)

1949 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)

1950 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)

1951 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)

1952 #define PIPE_DPST_EVENT_STATUS (1UL<<7)

1953 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)

1954 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)

1955 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)

1956 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */

1957 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */

1958 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)

1959 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)

1960

1961 #define DSPARB 0x70030

1962 #define DSPARB_CSTART_MASK (0x7f << 7)

1963 #define DSPARB_CSTART_SHIFT 7

1964 #define DSPARB_BSTART_MASK (0x7f)

1965 #define DSPARB_BSTART_SHIFT 0

1966 /*

1967 * The two pipe frame counter registers are not synchronized, so

1968 * reading a stable value is somewhat tricky. The following code

1969 * should work:

1970 *

1971 * do {

1972 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>

1973 * PIPE_FRAME_HIGH_SHIFT;

1974 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>

1975 * PIPE_FRAME_LOW_SHIFT);

1976 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>

1977 * PIPE_FRAME_HIGH_SHIFT);

1978 * } while (high1 != high2);

1979 * frame = (high1 << 8) | low1;

1980 */

1981 #define PIPEAFRAMEHIGH 0x70040

1982 #define PIPE_FRAME_HIGH_MASK 0x0000ffff

1983 #define PIPE_FRAME_HIGH_SHIFT 0

1984 #define PIPEAFRAMEPIXEL 0x70044

1985 #define PIPE_FRAME_LOW_MASK 0xff000000

1986 #define PIPE_FRAME_LOW_SHIFT 24

1987 #define PIPE_PIXEL_MASK 0x00ffffff

1988 #define PIPE_PIXEL_SHIFT 0

1989

1990 /* Cursor A & B regs */

1991 #define CURACNTR 0x70080

1992 #define CURSOR_MODE_DISABLE 0x00

1993 #define CURSOR_MODE_64_32B_AX 0x07

1994 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)

1995 #define MCURSOR_GAMMA_ENABLE (1 << 26)

1996 #define CURABASE 0x70084

1997 #define CURAPOS 0x70088

1998 #define CURSOR_POS_MASK 0x007FF

1999 #define CURSOR_POS_SIGN 0x8000

2000 #define CURSOR_X_SHIFT 0

2001 #define CURSOR_Y_SHIFT 16

2002 #define CURBCNTR 0x700c0

2003 #define CURBBASE 0x700c4

2004 #define CURBPOS 0x700c8

2005

2006 /* Display A control */

2007 #define DSPACNTR 0x70180

2008 #define DISPLAY_PLANE_ENABLE (1<<31)

2009 #define DISPLAY_PLANE_DISABLE 0

2010 #define DISPPLANE_GAMMA_ENABLE (1<<30)

2011 #define DISPPLANE_GAMMA_DISABLE 0

2012 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)

2013 #define DISPPLANE_8BPP (0x2<<26)

2014 #define DISPPLANE_15_16BPP (0x4<<26)

2015 #define DISPPLANE_16BPP (0x5<<26)

2016 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)

2017 #define DISPPLANE_32BPP (0x7<<26)

2018 #define DISPPLANE_STEREO_ENABLE (1<<25)

2019 #define DISPPLANE_STEREO_DISABLE 0

2020 #define DISPPLANE_SEL_PIPE_MASK (1<<24)

2021 #define DISPPLANE_SEL_PIPE_A 0

2022 #define DISPPLANE_SEL_PIPE_B (1<<24)

2023 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)

2024 #define DISPPLANE_SRC_KEY_DISABLE 0

2025 #define DISPPLANE_LINE_DOUBLE (1<<20)

2026 #define DISPPLANE_NO_LINE_DOUBLE 0

2027 #define DISPPLANE_STEREO_POLARITY_FIRST 0

2028 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)

2029 #define DSPAADDR 0x70184

2030 #define DSPASTRIDE 0x70188

2031 #define DSPAPOS 0x7018C /* reserved */

2032 #define DSPASIZE 0x70190

2033 #define DSPASURF 0x7019C /* 965+ only */

2034 #define DSPATILEOFF 0x701A4 /* 965+ only */

2035

2036 /* VBIOS flags */

2037 #define SWF00 0x71410

2038 #define SWF01 0x71414

2039 #define SWF02 0x71418

2040 #define SWF03 0x7141c

2041 #define SWF04 0x71420

2042 #define SWF05 0x71424

2043 #define SWF06 0x71428

2044 #define SWF10 0x70410

2045 #define SWF11 0x70414

2046 #define SWF14 0x71420

2047 #define SWF30 0x72414

2048 #define SWF31 0x72418

2049 #define SWF32 0x7241c

2050

2051 /* Pipe B */

2052 #define PIPEBDSL 0x71000

2053 #define PIPEBCONF 0x71008

2054 #define PIPEBSTAT 0x71024

2055 #define PIPEBFRAMEHIGH 0x71040

2056 #define PIPEBFRAMEPIXEL 0x71044

2057

2058 /* Display B control */

2059 #define DSPBCNTR 0x71180

2060 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)

2061 #define DISPPLANE_ALPHA_TRANS_DISABLE 0

2062 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0

2063 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)

2064 #define DSPBADDR 0x71184

2065 #define DSPBSTRIDE 0x71188

2066 #define DSPBPOS 0x7118C

2067 #define DSPBSIZE 0x71190

2068 #define DSPBSURF 0x7119C

2069 #define DSPBTILEOFF 0x711A4

2070

2071 /* VBIOS regs */

2072 #define VGACNTRL 0x71400

2073 # define VGA_DISP_DISABLE (1 << 31)

2074 # define VGA_2X_MODE (1 << 30)

2075 # define VGA_PIPE_B_SELECT (1 << 29)

2076

2077 /* Chipset type macros */

2078

2079 #define IS_I830(dev) ((dev)->pci_device == 0x3577)

2080 #define IS_845G(dev) ((dev)->pci_device == 0x2562)

2081 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)

2082 #define IS_I855(dev) ((dev)->pci_device == 0x3582)

2083 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)

2084

2085 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)

2086 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)

2087 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)

2088 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\

2089 (dev)->pci_device == 0x27AE)

2090 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \

2091 (dev)->pci_device == 0x2982 || \

2092 (dev)->pci_device == 0x2992 || \

2093 (dev)->pci_device == 0x29A2 || \

2094 (dev)->pci_device == 0x2A02 || \

2095 (dev)->pci_device == 0x2A12 || \

2096 (dev)->pci_device == 0x2A42 || \

2097 (dev)->pci_device == 0x2E02 || \

2098 (dev)->pci_device == 0x2E12 || \

2099 (dev)->pci_device == 0x2E22)

2100

2101 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)

2102

2103 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)

2104

2105 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \

2106 (dev)->pci_device == 0x2E12 || \

2107 (dev)->pci_device == 0x2E22)

2108

2109 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \

2110 (dev)->pci_device == 0x29B2 || \

2111 (dev)->pci_device == 0x29D2)

2112

2113 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \

2114 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))

2115

2116 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \

2117 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))

2118

2119 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))

2120

2121 #endif