2 * Copyright (c) 2007 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
12 #include "drm_sarea.h"
15 #include "intel_bios.h"
16 #include "intel_drv.h"
19 * i915_probe_agp - get AGP bootup configuration
21 * @aperture_size: returns AGP aperture configured size
22 * @preallocated_size: returns size of BIOS preallocated AGP space
24 * Since Intel integrated graphics are UMA, the BIOS has to set aside
25 * some RAM for the framebuffer at early boot. This code figures out
26 * how much was set aside so we can use it for our own purposes.
28 int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
29 unsigned long *preallocated_size)
31 struct pci_dev *bridge_dev;
33 unsigned long overhead;
35 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
37 DRM_ERROR("bridge device not found\n");
41 /* Get the fb aperture size and "stolen" memory amount. */
42 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
43 pci_dev_put(bridge_dev);
45 *aperture_size = 1024 * 1024;
46 *preallocated_size = 1024 * 1024;
48 switch (pdev->device) {
49 case PCI_DEVICE_ID_INTEL_82830_CGC:
50 case PCI_DEVICE_ID_INTEL_82845G_IG:
51 case PCI_DEVICE_ID_INTEL_82855GM_IG:
52 case PCI_DEVICE_ID_INTEL_82865_IG:
53 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
56 *aperture_size *= 128;
59 /* 9xx supports large sizes, just look at the length */
60 *aperture_size = pci_resource_len(pdev, 2);
65 * Some of the preallocated space is taken by the GTT
66 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
68 overhead = (*aperture_size / 1024) + 4096;
69 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
70 case INTEL_855_GMCH_GMS_STOLEN_1M:
71 break; /* 1M already */
72 case INTEL_855_GMCH_GMS_STOLEN_4M:
73 *preallocated_size *= 4;
75 case INTEL_855_GMCH_GMS_STOLEN_8M:
76 *preallocated_size *= 8;
78 case INTEL_855_GMCH_GMS_STOLEN_16M:
79 *preallocated_size *= 16;
81 case INTEL_855_GMCH_GMS_STOLEN_32M:
82 *preallocated_size *= 32;
84 case INTEL_915G_GMCH_GMS_STOLEN_48M:
85 *preallocated_size *= 48;
87 case INTEL_915G_GMCH_GMS_STOLEN_64M:
88 *preallocated_size *= 64;
90 case INTEL_855_GMCH_GMS_DISABLED:
91 DRM_ERROR("video memory is disabled\n");
94 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
95 tmp & INTEL_855_GMCH_GMS_MASK);
98 *preallocated_size -= overhead;
104 i915_init_hws_phys(struct drm_device *dev)
106 struct drm_i915_private *dev_priv = dev->dev_private;
109 dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
112 if (!dev_priv->status_page_dmah) {
113 DRM_ERROR("Can not allocate hardware status page\n");
117 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
118 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
120 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
122 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
123 DRM_DEBUG("hws kernel virt: 0x%p\n", dev_priv->hw_status_page);
129 static int i915_load_modeset_init(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
132 unsigned long agp_size, prealloc_size;
135 i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
137 /* Basic memrange allocator for stolen space (aka vram) */
138 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
139 /* Let GEM Manage from end of prealloc space to end of aperture */
140 i915_gem_do_init(dev, prealloc_size, agp_size);
142 if (!I915_NEED_GFX_HWS(dev))
143 i915_init_hws_phys(dev);
145 ret = i915_gem_init_ringbuffer(dev);
149 /* Allow hardware batchbuffers unless told otherwise.
151 dev_priv->allow_batchbuffer = 1;
152 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
153 mutex_init(&dev_priv->cmdbuf_mutex);
155 dev_priv->wq = create_singlethread_workqueue("i915");
156 if (dev_priv->wq == 0) {
157 DRM_DEBUG("Error\n");
159 goto destroy_ringbuffer;
162 ret = intel_init_bios(dev);
164 DRM_ERROR("failed to find VBIOS tables\n");
169 intel_modeset_init(dev);
170 drm_helper_initial_config(dev, false);
172 dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
175 goto modeset_cleanup;
178 ret = drm_irq_install(dev);
181 goto modeset_cleanup;
186 intel_modeset_cleanup(dev);
188 destroy_workqueue(dev_priv->wq);
190 i915_gem_cleanup_ringbuffer(dev);
196 * i915_driver_load - setup chip and create an initial config
198 * @flags: startup flags
200 * The driver load routine has to do several things:
201 * - drive output discovery via intel_modeset_init()
202 * - initialize the memory manager
203 * - allocate initial config memory
204 * - setup the DRM framebuffer with the allocated memory
206 int i915_driver_load(struct drm_device *dev, unsigned long flags)
208 struct drm_i915_private *dev_priv;
209 int ret = 0, num_pipes = 2;
212 dev_priv = drm_alloc(sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
213 if (dev_priv == NULL)
216 memset(dev_priv, 0, sizeof(struct drm_i915_private));
217 dev->dev_private = (void *)dev_priv;
220 /* i915 has 4 more counters */
222 dev->types[6] = _DRM_STAT_IRQ;
223 dev->types[7] = _DRM_STAT_PRIMARY;
224 dev->types[8] = _DRM_STAT_SECONDARY;
225 dev->types[9] = _DRM_STAT_DMA;
227 if (IS_MOBILE(dev) || IS_I9XX(dev))
228 dev_priv->cursor_needs_physical = true;
230 dev_priv->cursor_needs_physical = false;
232 if (IS_I965G(dev) || IS_G33(dev))
233 dev_priv->cursor_needs_physical = false;
236 pci_read_config_dword(dev->pdev, 0x5C, &dev_priv->stolen_base);
239 dev_priv->mmiobase = drm_get_resource_start(dev, 0);
240 dev_priv->mmiolen = drm_get_resource_len(dev, 0);
241 dev->mode_config.fb_base =
242 drm_get_resource_start(dev, 2) & 0xff000000;
243 } else if (drm_get_resource_start(dev, 1)) {
244 dev_priv->mmiobase = drm_get_resource_start(dev, 1);
245 dev_priv->mmiolen = drm_get_resource_len(dev, 1);
246 dev->mode_config.fb_base =
247 drm_get_resource_start(dev, 0) & 0xff000000;
249 DRM_ERROR("Unable to find MMIO registers\n");
254 DRM_DEBUG("fb_base: 0x%08lx\n", dev->mode_config.fb_base);
256 ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
257 _DRM_REGISTERS, _DRM_KERNEL|_DRM_READ_ONLY|_DRM_DRIVER,
258 &dev_priv->mmio_map);
260 DRM_ERROR("Cannot add mapping for MMIO registers\n");
267 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
268 intel_init_chipset_flush_compat(dev);
270 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
271 intel_opregion_init(dev);
275 tmp = I915_READ(PIPEASTAT);
276 I915_WRITE(PIPEASTAT, tmp);
277 tmp = I915_READ(PIPEBSTAT);
278 I915_WRITE(PIPEBSTAT, tmp);
280 atomic_set(&dev_priv->irq_received, 0);
281 I915_WRITE(HWSTAM, 0xeffe);
282 I915_WRITE(IMR, 0x0);
283 I915_WRITE(IER, 0x0);
285 DRM_SPININIT(&dev_priv->swaps_lock, "swap");
286 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
287 dev_priv->swaps_pending = 0;
289 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
290 dev_priv->user_irq_refcount = 0;
291 dev_priv->irq_mask_reg = ~0;
293 ret = drm_vblank_init(dev, num_pipes);
297 ret = drm_hotplug_init(dev);
301 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
302 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
304 i915_enable_interrupt(dev);
305 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
308 * Initialize the hardware status page IRQ location.
311 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
313 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
314 ret = i915_load_modeset_init(dev);
316 DRM_ERROR("failed to init modeset\n");
324 drm_rmmap(dev, dev_priv->mmio_map);
326 drm_free(dev_priv, sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
330 int i915_driver_unload(struct drm_device *dev)
332 struct drm_i915_private *dev_priv = dev->dev_private;
336 dev_priv->vblank_pipe = 0;
338 dev_priv->irq_enabled = 0;
340 I915_WRITE(HWSTAM, 0xffffffff);
341 I915_WRITE(IMR, 0xffffffff);
342 I915_WRITE(IER, 0x0);
344 temp = I915_READ(PIPEASTAT);
345 I915_WRITE(PIPEASTAT, temp);
346 temp = I915_READ(PIPEBSTAT);
347 I915_WRITE(PIPEBSTAT, temp);
348 temp = I915_READ(IIR);
349 I915_WRITE(IIR, temp);
351 I915_WRITE(PRB0_CTL, 0);
353 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
354 drm_irq_uninstall(dev);
355 intel_modeset_cleanup(dev);
356 destroy_workqueue(dev_priv->wq);
360 if (dev_priv->ring.virtual_start) {
361 drm_core_ioremapfree(&dev_priv->ring.map, dev);
366 if (dev_priv->sarea_kmap.virtual) {
367 drm_bo_kunmap(&dev_priv->sarea_kmap);
368 dev_priv->sarea_kmap.virtual = NULL;
369 dev->sigdata.lock = NULL;
372 if (dev_priv->sarea_bo) {
373 mutex_lock(&dev->struct_mutex);
374 drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
375 mutex_unlock(&dev->struct_mutex);
376 dev_priv->sarea_bo = NULL;
380 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
381 mutex_lock(&dev->struct_mutex);
382 i915_gem_cleanup_ringbuffer(dev);
383 mutex_unlock(&dev->struct_mutex);
384 drm_mm_takedown(&dev_priv->vram);
385 i915_gem_lastclose(dev);
386 if (!I915_NEED_GFX_HWS(dev))
387 drm_pci_free(dev, dev_priv->status_page_dmah);
390 drm_rmmap(dev, dev_priv->mmio_map);
393 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
394 intel_opregion_free(dev);
396 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
397 intel_fini_chipset_flush_compat(dev);
401 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
403 dev->dev_private = NULL;
407 int i915_master_create(struct drm_device *dev, struct drm_master *master)
409 struct drm_i915_master_private *master_priv;
410 unsigned long sareapage;
413 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
417 /* prebuild the SAREA */
418 sareapage = max(SAREA_MAX, PAGE_SIZE);
419 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
420 &master_priv->sarea);
422 DRM_ERROR("SAREA setup failed\n");
425 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
426 master_priv->sarea_priv->pf_current_page = 0;
428 master->driver_priv = master_priv;
432 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
434 struct drm_i915_master_private *master_priv = master->driver_priv;
439 if (master_priv->sarea)
440 drm_rmmap_locked(dev, master_priv->sarea);
442 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
444 master->driver_priv = NULL;
447 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
449 struct drm_i915_file_private *i915_file_priv;
452 i915_file_priv = (struct drm_i915_file_private *)
453 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
458 file_priv->driver_priv = i915_file_priv;
460 i915_file_priv->mm.last_gem_seqno = 0;
461 i915_file_priv->mm.last_gem_throttle_seqno = 0;
466 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
468 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
470 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
473 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
475 struct drm_i915_private *dev_priv = dev->dev_private;
476 if (!drm_core_check_feature(dev, DRIVER_MODESET))
477 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
480 void i915_driver_lastclose(struct drm_device * dev)
482 struct drm_i915_private *dev_priv = dev->dev_private;
484 if (drm_core_check_feature(dev, DRIVER_MODESET))
487 #ifdef I915_HAVE_BUFFER
488 if (dev_priv->val_bufs) {
489 vfree(dev_priv->val_bufs);
490 dev_priv->val_bufs = NULL;
494 i915_gem_lastclose(dev);
496 if (dev_priv->agp_heap)
497 i915_mem_takedown(&(dev_priv->agp_heap));
500 if (dev_priv->sarea_kmap.virtual) {
501 drm_bo_kunmap(&dev_priv->sarea_kmap);
502 dev_priv->sarea_kmap.virtual = NULL;
503 dev->control->master->lock.hw_lock = NULL;
504 dev->sigdata.lock = NULL;
507 if (dev_priv->sarea_bo) {
508 mutex_lock(&dev->struct_mutex);
509 drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
510 mutex_unlock(&dev->struct_mutex);
511 dev_priv->sarea_bo = NULL;
515 i915_dma_cleanup(dev);
518 int i915_driver_firstopen(struct drm_device *dev)
520 if (drm_core_check_feature(dev, DRIVER_MODESET))