1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define MAX_NOPID ((u32)~0)
37 * These are the interrupts used by the driver
39 #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \
40 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
41 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
44 i915_enable_irq(drm_i915_private_t *dev_priv, uint32_t mask)
46 if ((dev_priv->irq_mask_reg & mask) != 0) {
47 dev_priv->irq_mask_reg &= ~mask;
48 I915_WRITE(IMR, dev_priv->irq_mask_reg);
49 (void) I915_READ(IMR);
54 i915_disable_irq(drm_i915_private_t *dev_priv, uint32_t mask)
56 if ((dev_priv->irq_mask_reg & mask) != mask) {
57 dev_priv->irq_mask_reg |= mask;
58 I915_WRITE(IMR, dev_priv->irq_mask_reg);
59 (void) I915_READ(IMR);
64 * i915_get_pipe - return the the pipe associated with a given plane
66 * @plane: plane to look for
68 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
69 * rather than a pipe number, since they may not always be equal. This routine
70 * maps the given @plane back to a pipe number.
73 i915_get_pipe(struct drm_device *dev, int plane)
75 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
78 dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
80 return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
84 * i915_get_plane - return the the plane associated with a given pipe
86 * @pipe: pipe to look for
88 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
89 * rather than a plane number, since they may not always be equal. This routine
90 * maps the given @pipe back to a plane number.
93 i915_get_plane(struct drm_device *dev, int pipe)
95 if (i915_get_pipe(dev, 0) == pipe)
101 * i915_pipe_enabled - check if a pipe is enabled
103 * @pipe: pipe to check
105 * Reading certain registers when the pipe is disabled can hang the chip.
106 * Use this routine to make sure the PLL is running and the pipe is active
107 * before reading such registers if unsure.
110 i915_pipe_enabled(struct drm_device *dev, int pipe)
112 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
113 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
115 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
122 * Emit a synchronous flip.
124 * This function must be called with the drawable spinlock held.
127 i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
130 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
131 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
133 int pf_planes = 1 << plane;
135 DRM_SPINLOCK_ASSERT(&dev->drw_lock);
137 /* If the window is visible on the other plane, we have to flip on that
141 x1 = sarea_priv->planeA_x;
142 y1 = sarea_priv->planeA_y;
143 x2 = x1 + sarea_priv->planeA_w;
144 y2 = y1 + sarea_priv->planeA_h;
146 x1 = sarea_priv->planeB_x;
147 y1 = sarea_priv->planeB_y;
148 x2 = x1 + sarea_priv->planeB_w;
149 y2 = y1 + sarea_priv->planeB_h;
152 if (x2 > 0 && y2 > 0) {
153 int i, num_rects = drw->num_rects;
154 struct drm_clip_rect *rect = drw->rects;
156 for (i = 0; i < num_rects; i++)
157 if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
158 rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
165 i915_dispatch_flip(dev, pf_planes, 1);
169 * Emit blits for scheduled buffer swaps.
171 * This function will be called with the HW lock held.
173 static void i915_vblank_tasklet(struct drm_device *dev)
175 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
176 struct list_head *list, *tmp, hits, *hit;
177 int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
179 struct drm_drawable_info *drw;
180 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
181 u32 cpp = dev_priv->cpp, offsets[3];
182 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
183 XY_SRC_COPY_BLT_WRITE_ALPHA |
184 XY_SRC_COPY_BLT_WRITE_RGB)
185 : XY_SRC_COPY_BLT_CMD;
186 u32 src_pitch = sarea_priv->pitch * cpp;
187 u32 dst_pitch = sarea_priv->pitch * cpp;
188 /* COPY rop (0xcc), map cpp to magic color depth constants */
189 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
192 if (IS_I965G(dev) && sarea_priv->front_tiled) {
193 cmd |= XY_SRC_COPY_BLT_DST_TILED;
196 if (IS_I965G(dev) && sarea_priv->back_tiled) {
197 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
201 counter[0] = drm_vblank_count(dev, 0);
202 counter[1] = drm_vblank_count(dev, 1);
206 INIT_LIST_HEAD(&hits);
210 /* No irqsave/restore necessary. This tasklet may be run in an
211 * interrupt context or normal context, but we don't have to worry
212 * about getting interrupted by something acquiring the lock, because
213 * we are the interrupt context thing that acquires the lock.
215 DRM_SPINLOCK(&dev_priv->swaps_lock);
217 /* Find buffer swaps scheduled for this vertical blank */
218 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
219 drm_i915_vbl_swap_t *vbl_swap =
220 list_entry(list, drm_i915_vbl_swap_t, head);
221 int pipe = i915_get_pipe(dev, vbl_swap->plane);
223 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
227 dev_priv->swaps_pending--;
228 drm_vblank_put(dev, pipe);
230 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
231 DRM_SPINLOCK(&dev->drw_lock);
233 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
236 DRM_SPINUNLOCK(&dev->drw_lock);
237 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
238 DRM_SPINLOCK(&dev_priv->swaps_lock);
242 list_for_each(hit, &hits) {
243 drm_i915_vbl_swap_t *swap_cmp =
244 list_entry(hit, drm_i915_vbl_swap_t, head);
245 struct drm_drawable_info *drw_cmp =
246 drm_get_drawable_info(dev, swap_cmp->drw_id);
249 drw_cmp->rects[0].y1 > drw->rects[0].y1) {
250 list_add_tail(list, hit);
255 DRM_SPINUNLOCK(&dev->drw_lock);
257 /* List of hits was empty, or we reached the end of it */
259 list_add_tail(list, hits.prev);
263 DRM_SPINLOCK(&dev_priv->swaps_lock);
266 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
272 i915_kernel_lost_context(dev);
274 upper[0] = upper[1] = 0;
275 slice[0] = max(sarea_priv->planeA_h / nhits, 1);
276 slice[1] = max(sarea_priv->planeB_h / nhits, 1);
277 lower[0] = sarea_priv->planeA_y + slice[0];
278 lower[1] = sarea_priv->planeB_y + slice[0];
280 offsets[0] = sarea_priv->front_offset;
281 offsets[1] = sarea_priv->back_offset;
282 offsets[2] = sarea_priv->third_offset;
283 num_pages = sarea_priv->third_handle ? 3 : 2;
285 DRM_SPINLOCK(&dev->drw_lock);
287 /* Emit blits for buffer swaps, partitioning both outputs into as many
288 * slices as there are buffer swaps scheduled in order to avoid tearing
289 * (based on the assumption that a single buffer swap would always
290 * complete before scanout starts).
292 for (i = 0; i++ < nhits;
293 upper[0] = lower[0], lower[0] += slice[0],
294 upper[1] = lower[1], lower[1] += slice[1]) {
295 int init_drawrect = 1;
298 lower[0] = lower[1] = sarea_priv->height;
300 list_for_each(hit, &hits) {
301 drm_i915_vbl_swap_t *swap_hit =
302 list_entry(hit, drm_i915_vbl_swap_t, head);
303 struct drm_clip_rect *rect;
304 int num_rects, plane, front, back;
305 unsigned short top, bottom;
307 drw = drm_get_drawable_info(dev, swap_hit->drw_id);
312 plane = swap_hit->plane;
314 if (swap_hit->flip) {
315 i915_dispatch_vsync_flip(dev, drw, plane);
320 int width = sarea_priv->width;
321 int height = sarea_priv->height;
325 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
327 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
334 OUT_RING(GFX_OP_DRAWRECT_INFO);
337 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
344 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
351 bottom = lower[plane];
353 front = (dev_priv->sarea_priv->pf_current_page >>
355 back = (front + 1) % num_pages;
357 for (num_rects = drw->num_rects; num_rects--; rect++) {
358 int y1 = max(rect->y1, top);
359 int y2 = min(rect->y2, bottom);
367 OUT_RING(ropcpp | dst_pitch);
368 OUT_RING((y1 << 16) | rect->x1);
369 OUT_RING((y2 << 16) | rect->x2);
370 OUT_RING(offsets[front]);
371 OUT_RING((y1 << 16) | rect->x1);
373 OUT_RING(offsets[back]);
380 DRM_SPINUNLOCK(&dev->drw_lock);
382 list_for_each_safe(hit, tmp, &hits) {
383 drm_i915_vbl_swap_t *swap_hit =
384 list_entry(hit, drm_i915_vbl_swap_t, head);
388 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
392 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
394 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
395 unsigned long high_frame;
396 unsigned long low_frame;
397 u32 high1, high2, low, count;
400 pipe = i915_get_pipe(dev, plane);
401 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
402 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
404 if (!i915_pipe_enabled(dev, pipe)) {
405 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
410 * High & low register fields aren't synchronized, so make sure
411 * we get a low value that's stable across two reads of the high
415 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
416 PIPE_FRAME_HIGH_SHIFT);
417 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
418 PIPE_FRAME_LOW_SHIFT);
419 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
420 PIPE_FRAME_HIGH_SHIFT);
421 } while (high1 != high2);
423 count = (high1 << 8) | low;
428 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
430 struct drm_device *dev = (struct drm_device *) arg;
431 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
433 u32 pipea_stats = 0, pipeb_stats = 0;
436 if (dev->pdev->msi_enabled)
439 iir = I915_READ(IIR);
441 DRM_DEBUG("flag=%08x\n", iir);
443 atomic_inc(&dev_priv->irq_received);
446 if (dev->pdev->msi_enabled) {
447 I915_WRITE(IMR, dev_priv->irq_mask_reg);
448 (void) I915_READ(IMR);
455 * Clear the PIPE(A|B)STAT regs before the IIR otherwise
456 * we may get extra interrupts.
458 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
459 pipea_stats = I915_READ(PIPEASTAT);
460 if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
461 PIPE_VBLANK_INTERRUPT_STATUS))
464 drm_handle_vblank(dev, i915_get_plane(dev, 0));
466 I915_WRITE(PIPEASTAT, pipea_stats);
468 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
469 pipeb_stats = I915_READ(PIPEBSTAT);
471 I915_WRITE(PIPEBSTAT, pipeb_stats);
473 /* The vblank interrupt gets enabled even if we didn't ask for
474 it, so make sure it's shut down again */
475 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B))
476 pipeb_stats &= ~(I915_VBLANK_INTERRUPT_ENABLE);
478 if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
479 PIPE_VBLANK_INTERRUPT_STATUS))
482 drm_handle_vblank(dev, i915_get_plane(dev, 1));
486 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
487 if (pipeb_stats & I915_LEGACY_BLC_EVENT_ENABLE)
488 opregion_asle_intr(dev);
491 I915_WRITE(PIPEBSTAT, pipeb_stats);
495 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
496 if (iir & I915_ASLE_INTERRUPT)
497 opregion_asle_intr(dev);
501 if (dev_priv->sarea_priv)
502 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
504 I915_WRITE(IIR, iir);
506 if (dev->pdev->msi_enabled)
507 I915_WRITE(IMR, dev_priv->irq_mask_reg);
509 (void) I915_READ(IIR); /* Flush posted writes */
511 if (iir & I915_USER_INTERRUPT) {
513 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
515 DRM_WAKEUP(&dev_priv->irq_queue);
516 #ifdef I915_HAVE_FENCE
517 i915_fence_handler(dev);
522 if (dev_priv->swaps_pending > 0)
523 drm_locked_tasklet(dev, i915_vblank_tasklet);
529 int i915_emit_irq(struct drm_device *dev)
531 drm_i915_private_t *dev_priv = dev->dev_private;
534 i915_kernel_lost_context(dev);
538 i915_emit_breadcrumb(dev);
542 OUT_RING(MI_USER_INTERRUPT);
545 return dev_priv->counter;
548 void i915_user_irq_on(drm_i915_private_t *dev_priv)
550 DRM_SPINLOCK(&dev_priv->user_irq_lock);
551 if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1))
552 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
553 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
556 void i915_user_irq_off(drm_i915_private_t *dev_priv)
558 DRM_SPINLOCK(&dev_priv->user_irq_lock);
560 BUG_ON(dev_priv->irq_enabled && dev_priv->user_irq_refcount <= 0);
562 if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0))
563 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
564 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
568 int i915_wait_irq(struct drm_device * dev, int irq_nr)
570 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
574 DRM_ERROR("called with no initialization\n");
578 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
579 READ_BREADCRUMB(dev_priv));
581 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
582 if (dev_priv->sarea_priv)
583 dev_priv->sarea_priv->last_dispatch =
584 READ_BREADCRUMB(dev_priv);
588 i915_user_irq_on(dev_priv);
589 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
590 READ_BREADCRUMB(dev_priv) >= irq_nr);
591 i915_user_irq_off(dev_priv);
594 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
595 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
598 if (dev_priv->sarea_priv)
599 dev_priv->sarea_priv->last_dispatch =
600 READ_BREADCRUMB(dev_priv);
604 /* Needs the lock as it touches the ring.
606 int i915_irq_emit(struct drm_device *dev, void *data,
607 struct drm_file *file_priv)
609 drm_i915_private_t *dev_priv = dev->dev_private;
610 drm_i915_irq_emit_t *emit = data;
613 LOCK_TEST_WITH_RETURN(dev, file_priv);
616 DRM_ERROR("called with no initialization\n");
620 result = i915_emit_irq(dev);
622 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
623 DRM_ERROR("copy_to_user\n");
630 /* Doesn't need the hardware lock.
632 int i915_irq_wait(struct drm_device *dev, void *data,
633 struct drm_file *file_priv)
635 drm_i915_private_t *dev_priv = dev->dev_private;
636 drm_i915_irq_wait_t *irqwait = data;
639 DRM_ERROR("called with no initialization\n");
643 return i915_wait_irq(dev, irqwait->irq_seq);
646 int i915_enable_vblank(struct drm_device *dev, int plane)
648 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
649 int pipe = i915_get_pipe(dev, plane);
650 u32 pipestat_reg = 0;
656 pipestat_reg = PIPEASTAT;
657 mask_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
660 pipestat_reg = PIPEBSTAT;
661 mask_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
664 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
671 pipestat = I915_READ (pipestat_reg);
673 * Older chips didn't have the start vblank interrupt,
677 pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
679 pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
681 * Clear any pending status
683 pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
684 PIPE_VBLANK_INTERRUPT_STATUS);
685 I915_WRITE(pipestat_reg, pipestat);
687 DRM_SPINLOCK(&dev_priv->user_irq_lock);
688 i915_enable_irq(dev_priv, mask_reg);
689 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
694 void i915_disable_vblank(struct drm_device *dev, int plane)
696 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
697 int pipe = i915_get_pipe(dev, plane);
698 u32 pipestat_reg = 0;
704 pipestat_reg = PIPEASTAT;
705 mask_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
708 pipestat_reg = PIPEBSTAT;
709 mask_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
712 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
717 DRM_SPINLOCK(&dev_priv->user_irq_lock);
718 i915_disable_irq(dev_priv, mask_reg);
719 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
723 pipestat = I915_READ (pipestat_reg);
724 pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
725 PIPE_VBLANK_INTERRUPT_ENABLE);
727 * Clear any pending status
729 pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
730 PIPE_VBLANK_INTERRUPT_STATUS);
731 I915_WRITE(pipestat_reg, pipestat);
732 (void) I915_READ(pipestat_reg);
736 static void i915_enable_interrupt (struct drm_device *dev)
738 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
740 dev_priv->irq_mask_reg = ~0;
741 I915_WRITE(IMR, dev_priv->irq_mask_reg);
742 I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
743 (void) I915_READ (IER);
746 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
747 opregion_enable_asle(dev);
751 dev_priv->irq_enabled = 1;
754 /* Set the vblank monitor pipe
756 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
757 struct drm_file *file_priv)
759 drm_i915_private_t *dev_priv = dev->dev_private;
762 DRM_ERROR("called with no initialization\n");
769 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
770 struct drm_file *file_priv)
772 drm_i915_private_t *dev_priv = dev->dev_private;
773 drm_i915_vblank_pipe_t *pipe = data;
776 DRM_ERROR("called with no initialization\n");
780 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
786 * Schedule buffer swap at given vertical blank.
788 int i915_vblank_swap(struct drm_device *dev, void *data,
789 struct drm_file *file_priv)
791 drm_i915_private_t *dev_priv = dev->dev_private;
792 drm_i915_vblank_swap_t *swap = data;
793 drm_i915_vbl_swap_t *vbl_swap;
794 unsigned int pipe, seqtype, curseq, plane;
795 unsigned long irqflags;
796 struct list_head *list;
800 DRM_ERROR("%s called with no initialization\n", __func__);
804 if (!dev_priv->sarea_priv || dev_priv->sarea_priv->rotation) {
805 DRM_DEBUG("Rotation not supported\n");
809 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
810 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
812 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
816 plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
817 pipe = i915_get_pipe(dev, plane);
819 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
821 if (!(dev_priv->vblank_pipe & (1 << pipe))) {
822 DRM_ERROR("Invalid pipe %d\n", pipe);
826 DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
828 /* It makes no sense to schedule a swap for a drawable that doesn't have
829 * valid information at this point. E.g. this could mean that the X
830 * server is too old to push drawable information to the DRM, in which
831 * case all such swaps would become ineffective.
833 if (!drm_get_drawable_info(dev, swap->drawable)) {
834 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
835 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
839 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
842 * We take the ref here and put it when the swap actually completes
845 ret = drm_vblank_get(dev, pipe);
848 curseq = drm_vblank_count(dev, pipe);
850 if (seqtype == _DRM_VBLANK_RELATIVE)
851 swap->sequence += curseq;
853 if ((curseq - swap->sequence) <= (1<<23)) {
854 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
855 swap->sequence = curseq + 1;
857 DRM_DEBUG("Missed target sequence\n");
858 drm_vblank_put(dev, pipe);
863 if (swap->seqtype & _DRM_VBLANK_FLIP) {
866 if ((curseq - swap->sequence) <= (1<<23)) {
867 struct drm_drawable_info *drw;
869 LOCK_TEST_WITH_RETURN(dev, file_priv);
871 DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
873 drw = drm_get_drawable_info(dev, swap->drawable);
876 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock,
878 DRM_DEBUG("Invalid drawable ID %d\n",
880 drm_vblank_put(dev, pipe);
884 i915_dispatch_vsync_flip(dev, drw, plane);
886 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
888 drm_vblank_put(dev, pipe);
893 DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
895 list_for_each(list, &dev_priv->vbl_swaps.head) {
896 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
898 if (vbl_swap->drw_id == swap->drawable &&
899 vbl_swap->plane == plane &&
900 vbl_swap->sequence == swap->sequence) {
901 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
902 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
903 DRM_DEBUG("Already scheduled\n");
908 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
910 if (dev_priv->swaps_pending >= 100) {
911 DRM_DEBUG("Too many swaps queued\n");
912 drm_vblank_put(dev, pipe);
916 vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
919 DRM_ERROR("Failed to allocate memory to queue swap\n");
920 drm_vblank_put(dev, pipe);
926 vbl_swap->drw_id = swap->drawable;
927 vbl_swap->plane = plane;
928 vbl_swap->sequence = swap->sequence;
929 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
934 DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
936 list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
937 dev_priv->swaps_pending++;
939 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
946 void i915_driver_irq_preinstall(struct drm_device * dev)
948 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
950 I915_WRITE16(HWSTAM, 0xeffe);
951 I915_WRITE16(IMR, 0x0);
952 I915_WRITE16(IER, 0x0);
955 int i915_driver_irq_postinstall(struct drm_device * dev)
957 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
958 int ret, num_pipes = 2;
960 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
961 dev_priv->swaps_pending = 0;
963 dev_priv->user_irq_refcount = 0;
964 dev_priv->irq_mask_reg = ~0;
966 ret = drm_vblank_init(dev, num_pipes);
970 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
971 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
973 i915_enable_interrupt(dev);
974 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
977 * Initialize the hardware status page IRQ location.
980 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
984 void i915_driver_irq_uninstall(struct drm_device * dev)
986 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
992 dev_priv->vblank_pipe = 0;
994 dev_priv->irq_enabled = 0;
995 I915_WRITE(HWSTAM, 0xffffffff);
996 I915_WRITE(IMR, 0xffffffff);
997 I915_WRITE(IER, 0x0);
999 temp = I915_READ(PIPEASTAT);
1000 I915_WRITE(PIPEASTAT, temp);
1001 temp = I915_READ(PIPEBSTAT);
1002 I915_WRITE(PIPEBSTAT, temp);
1003 temp = I915_READ(IIR);
1004 I915_WRITE(IIR, temp);