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1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-

2 */

3 /*

6 *

7 * Permission is hereby granted, free of charge, to any person obtaining a

8 * copy of this software and associated documentation files (the

9 * "Software"), to deal in the Software without restriction, including

10 * without limitation the rights to use, copy, modify, merge, publish,

11 * distribute, sub license, and/or sell copies of the Software, and to

12 * permit persons to whom the Software is furnished to do so, subject to

13 * the following conditions:

14 *

15 * The above copyright notice and this permission notice (including the

16 * next paragraph) shall be included in all copies or substantial portions

17 * of the Software.

18 *

19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

26 *

27 */

29 #include "drmP.h"

30 #include "drm.h"

31 #include "i915_drm.h"

32 #include "i915_drv.h"

34 #define MAX_NOPID ((u32)~0)

36 /**

37 * i915_get_pipe - return the the pipe associated with a given plane

38 * @dev: DRM device

39 * @plane: plane to look for

40 *

41 * The Intel Mesa & 2D drivers call the vblank routines with a plane number

42 * rather than a pipe number, since they may not always be equal. This routine

43 * maps the given @plane back to a pipe number.

44 */

45 static int

46 i915_get_pipe(struct drm_device *dev, int plane)

47 {

48 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

49 u32 dspcntr;

51 dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);

53 return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;

54 }

56 /**

57 * i915_get_plane - return the the plane associated with a given pipe

58 * @dev: DRM device

59 * @pipe: pipe to look for

60 *

61 * The Intel Mesa & 2D drivers call the vblank routines with a plane number

62 * rather than a plane number, since they may not always be equal. This routine

63 * maps the given @pipe back to a plane number.

64 */

65 static int

66 i915_get_plane(struct drm_device *dev, int pipe)

67 {

68 if (i915_get_pipe(dev, 0) == pipe)

69 return 0;

70 return 1;

71 }

73 /**

74 * i915_pipe_enabled - check if a pipe is enabled

75 * @dev: DRM device

76 * @pipe: pipe to check

77 *

78 * Reading certain registers when the pipe is disabled can hang the chip.

79 * Use this routine to make sure the PLL is running and the pipe is active

80 * before reading such registers if unsure.

81 */

82 static int

83 i915_pipe_enabled(struct drm_device *dev, int pipe)

84 {

85 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

86 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;

88 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)

89 return 1;

91 return 0;

92 }

94 /**

95 * Emit a synchronous flip.

96 *

97 * This function must be called with the drawable spinlock held.

98 */

99 static void

100 i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,

101 int plane)

102 {

103 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

104 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;

105 u16 x1, y1, x2, y2;

106 int pf_planes = 1 << plane;

107

108 DRM_SPINLOCK_ASSERT(&dev->drw_lock);

109

110 /* If the window is visible on the other plane, we have to flip on that

111 * plane as well.

112 */

113 if (plane == 1) {

114 x1 = sarea_priv->planeA_x;

115 y1 = sarea_priv->planeA_y;

116 x2 = x1 + sarea_priv->planeA_w;

117 y2 = y1 + sarea_priv->planeA_h;

118 } else {

119 x1 = sarea_priv->planeB_x;

120 y1 = sarea_priv->planeB_y;

121 x2 = x1 + sarea_priv->planeB_w;

122 y2 = y1 + sarea_priv->planeB_h;

123 }

124

125 if (x2 > 0 && y2 > 0) {

126 int i, num_rects = drw->num_rects;

127 struct drm_clip_rect *rect = drw->rects;

128

129 for (i = 0; i < num_rects; i++)

130 if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||

131 rect[i].x2 <= x1 || rect[i].y2 <= y1)) {

132 pf_planes = 0x3;

133

134 break;

135 }

136 }

137

138 i915_dispatch_flip(dev, pf_planes, 1);

139 }

140

141 /**

142 * Emit blits for scheduled buffer swaps.

143 *

144 * This function will be called with the HW lock held.

145 */

146 static void i915_vblank_tasklet(struct drm_device *dev)

147 {

148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

149 struct list_head *list, *tmp, hits, *hit;

150 int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;

151 unsigned counter[2];

152 struct drm_drawable_info *drw;

153 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;

154 u32 cpp = dev_priv->cpp, offsets[3];

155 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |

156 XY_SRC_COPY_BLT_WRITE_ALPHA |

157 XY_SRC_COPY_BLT_WRITE_RGB)

158 : XY_SRC_COPY_BLT_CMD;

159 u32 pitchropcpp = (sarea_priv->pitch * cpp) | (0xcc << 16) |

160 (cpp << 23) | (1 << 24);

161 RING_LOCALS;

162

163 counter[0] = drm_vblank_count(dev, 0);

164 counter[1] = drm_vblank_count(dev, 1);

165

166 DRM_DEBUG("\n");

167

168 INIT_LIST_HEAD(&hits);

169

170 nhits = nrects = 0;

171

172 /* No irqsave/restore necessary. This tasklet may be run in an

173 * interrupt context or normal context, but we don't have to worry

174 * about getting interrupted by something acquiring the lock, because

175 * we are the interrupt context thing that acquires the lock.

176 */

177 DRM_SPINLOCK(&dev_priv->swaps_lock);

178

179 /* Find buffer swaps scheduled for this vertical blank */

180 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {

181 drm_i915_vbl_swap_t *vbl_swap =

182 list_entry(list, drm_i915_vbl_swap_t, head);

183 int pipe = i915_get_pipe(dev, vbl_swap->plane);

184

185 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))

186 continue;

187

188 list_del(list);

189 dev_priv->swaps_pending--;

190 drm_vblank_put(dev, pipe);

191

192 DRM_SPINUNLOCK(&dev_priv->swaps_lock);

193 DRM_SPINLOCK(&dev->drw_lock);

194

195 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);

196

197 if (!drw) {

198 DRM_SPINUNLOCK(&dev->drw_lock);

199 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);

200 DRM_SPINLOCK(&dev_priv->swaps_lock);

201 continue;

202 }

203

204 list_for_each(hit, &hits) {

205 drm_i915_vbl_swap_t *swap_cmp =

206 list_entry(hit, drm_i915_vbl_swap_t, head);

207 struct drm_drawable_info *drw_cmp =

208 drm_get_drawable_info(dev, swap_cmp->drw_id);

209

210 if (drw_cmp &&

211 drw_cmp->rects[0].y1 > drw->rects[0].y1) {

212 list_add_tail(list, hit);

213 break;

214 }

215 }

216

217 DRM_SPINUNLOCK(&dev->drw_lock);

218

219 /* List of hits was empty, or we reached the end of it */

220 if (hit == &hits)

221 list_add_tail(list, hits.prev);

222

223 nhits++;

224

225 DRM_SPINLOCK(&dev_priv->swaps_lock);

226 }

227

228 DRM_SPINUNLOCK(&dev_priv->swaps_lock);

229

230 if (nhits == 0) {

231 return;

232 }

233

234 i915_kernel_lost_context(dev);

235

236 upper[0] = upper[1] = 0;

237 slice[0] = max(sarea_priv->planeA_h / nhits, 1);

238 slice[1] = max(sarea_priv->planeB_h / nhits, 1);

239 lower[0] = sarea_priv->planeA_y + slice[0];

240 lower[1] = sarea_priv->planeB_y + slice[0];

241

242 offsets[0] = sarea_priv->front_offset;

243 offsets[1] = sarea_priv->back_offset;

244 offsets[2] = sarea_priv->third_offset;

245 num_pages = sarea_priv->third_handle ? 3 : 2;

246

247 DRM_SPINLOCK(&dev->drw_lock);

248

249 /* Emit blits for buffer swaps, partitioning both outputs into as many

250 * slices as there are buffer swaps scheduled in order to avoid tearing

251 * (based on the assumption that a single buffer swap would always

252 * complete before scanout starts).

253 */

254 for (i = 0; i++ < nhits;

255 upper[0] = lower[0], lower[0] += slice[0],

256 upper[1] = lower[1], lower[1] += slice[1]) {

257 int init_drawrect = 1;

258

259 if (i == nhits)

260 lower[0] = lower[1] = sarea_priv->height;

261

262 list_for_each(hit, &hits) {

263 drm_i915_vbl_swap_t *swap_hit =

264 list_entry(hit, drm_i915_vbl_swap_t, head);

265 struct drm_clip_rect *rect;

266 int num_rects, plane, front, back;

267 unsigned short top, bottom;

268

269 drw = drm_get_drawable_info(dev, swap_hit->drw_id);

270

271 if (!drw)

272 continue;

273

274 plane = swap_hit->plane;

275

276 if (swap_hit->flip) {

277 i915_dispatch_vsync_flip(dev, drw, plane);

278 continue;

279 }

280

281 if (init_drawrect) {

282 BEGIN_LP_RING(6);

283

284 OUT_RING(GFX_OP_DRAWRECT_INFO);

285 OUT_RING(0);

286 OUT_RING(0);

287 OUT_RING(sarea_priv->width | sarea_priv->height << 16);

288 OUT_RING(sarea_priv->width | sarea_priv->height << 16);

289 OUT_RING(0);

290

291 ADVANCE_LP_RING();

292

293 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;

294

295 init_drawrect = 0;

296 }

297

298 rect = drw->rects;

299 top = upper[plane];

300 bottom = lower[plane];

301

302 front = (dev_priv->sarea_priv->pf_current_page >>

303 (2 * plane)) & 0x3;

304 back = (front + 1) % num_pages;

305

306 for (num_rects = drw->num_rects; num_rects--; rect++) {

307 int y1 = max(rect->y1, top);

308 int y2 = min(rect->y2, bottom);

309

310 if (y1 >= y2)

311 continue;

312

313 BEGIN_LP_RING(8);

314

315 OUT_RING(cmd);

316 OUT_RING(pitchropcpp);

317 OUT_RING((y1 << 16) | rect->x1);

318 OUT_RING((y2 << 16) | rect->x2);

319 OUT_RING(offsets[front]);

320 OUT_RING((y1 << 16) | rect->x1);

321 OUT_RING(pitchropcpp & 0xffff);

322 OUT_RING(offsets[back]);

323

324 ADVANCE_LP_RING();

325 }

326 }

327 }

328

329 DRM_SPINUNLOCK(&dev->drw_lock);

330

331 list_for_each_safe(hit, tmp, &hits) {

332 drm_i915_vbl_swap_t *swap_hit =

333 list_entry(hit, drm_i915_vbl_swap_t, head);

334

335 list_del(hit);

336

337 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);

338 }

339 }

340 #if 0

341 static int i915_in_vblank(struct drm_device *dev, int pipe)

342 {

343 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

344 unsigned long pipedsl, vblank, vtotal;

345 unsigned long vbl_start, vbl_end, cur_line;

346

347 pipedsl = pipe ? PIPEBDSL : PIPEADSL;

348 vblank = pipe ? VBLANK_B : VBLANK_A;

349 vtotal = pipe ? VTOTAL_B : VTOTAL_A;

350

351 vbl_start = I915_READ(vblank) & VBLANK_START_MASK;

352 vbl_end = (I915_READ(vblank) >> VBLANK_END_SHIFT) & VBLANK_END_MASK;

353

354 cur_line = I915_READ(pipedsl);

355

356 if (cur_line >= vbl_start)

357 return 1;

358

359 return 0;

360 }

361 #endif

362 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)

363 {

364 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

365 unsigned long high_frame;

366 unsigned long low_frame;

367 u32 high1, high2, low, count;

368 int pipe;

369

370 pipe = i915_get_pipe(dev, plane);

371 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;

372 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;

373

374 if (!i915_pipe_enabled(dev, pipe)) {

375 printk(KERN_ERR "trying to get vblank count for disabled "

376 "pipe %d\n", pipe);

377 return 0;

378 }

379

380 /*

381 * High & low register fields aren't synchronized, so make sure

382 * we get a low value that's stable across two reads of the high

383 * register.

384 */

385 do {

386 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>

387 PIPE_FRAME_HIGH_SHIFT);

388 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>

389 PIPE_FRAME_LOW_SHIFT);

390 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>

391 PIPE_FRAME_HIGH_SHIFT);

392 } while (high1 != high2);

393

394 count = (high1 << 8) | low;

395

396 /*

397 * If we're in the middle of the vblank period, the

398 * above regs won't have been updated yet, so return

399 * an incremented count to stay accurate

400 */

401 #if 0

402 if (i915_in_vblank(dev, pipe))

403 count++;

404 #endif

405 /* count may be reset by other driver(e.g. 2D driver),

406 we have no way to know if it is wrapped or resetted

407 when count is zero. do a rough guess.

408 */

409 if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)

410 dev->last_vblank[pipe] = 0;

411

412 return count;

413 }

414

415 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)

416 {

417 struct drm_device *dev = (struct drm_device *) arg;

418 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

419 u32 iir;

420 u32 pipea_stats, pipeb_stats;

421 int vblank = 0;

422

423 iir = I915_READ(I915REG_INT_IDENTITY_R);

424 #if 0

425 DRM_DEBUG("flag=%08x\n", iir);

426 #endif

427 if (iir == 0) {

428 DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",

429 iir,

430 I915_READ(I915REG_INT_MASK_R),

431 I915_READ(I915REG_INT_ENABLE_R),

432 I915_READ(I915REG_PIPEASTAT),

433 I915_READ(I915REG_PIPEBSTAT));

434 return IRQ_NONE;

435 }

436

437 /*

438 * Clear the PIPE(A|B)STAT regs before the IIR otherwise

439 * we may get extra interrupts.

440 */

441 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {

442 pipea_stats = I915_READ(I915REG_PIPEASTAT);

443 if (pipea_stats & (I915_START_VBLANK_INTERRUPT_STATUS|

444 I915_VBLANK_INTERRUPT_STATUS))

445 {

446 vblank++;

447 drm_handle_vblank(dev, i915_get_plane(dev, 0));

448 }

449 I915_WRITE(I915REG_PIPEASTAT, pipea_stats);

450 }

451 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {

452 pipeb_stats = I915_READ(I915REG_PIPEBSTAT);

453 if (pipeb_stats & (I915_START_VBLANK_INTERRUPT_STATUS|

454 I915_VBLANK_INTERRUPT_STATUS))

455 {

456 vblank++;

457 drm_handle_vblank(dev, i915_get_plane(dev, 1));

458 }

459 I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);

460 }

461

462 if (dev_priv->sarea_priv)

463 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);

464

465 I915_WRITE(I915REG_INT_IDENTITY_R, iir);

466 (void) I915_READ(I915REG_INT_IDENTITY_R); /* Flush posted write */

467

468 if (iir & I915_USER_INTERRUPT) {

469 DRM_WAKEUP(&dev_priv->irq_queue);

470 #ifdef I915_HAVE_FENCE

471 i915_fence_handler(dev);

472 #endif

473 }

474

475 if (vblank) {

476 if (dev_priv->swaps_pending > 0)

477 drm_locked_tasklet(dev, i915_vblank_tasklet);

478 }

479

480 return IRQ_HANDLED;

481 }

482

483 int i915_emit_irq(struct drm_device *dev)

484 {

485 drm_i915_private_t *dev_priv = dev->dev_private;

486 RING_LOCALS;

487

488 i915_kernel_lost_context(dev);

489

490 DRM_DEBUG("\n");

491

492 i915_emit_breadcrumb(dev);

493

494 BEGIN_LP_RING(2);

495 OUT_RING(0);

496 OUT_RING(GFX_OP_USER_INTERRUPT);

497 ADVANCE_LP_RING();

498

499 return dev_priv->counter;

500 }

501

502 void i915_user_irq_on(drm_i915_private_t *dev_priv)

503 {

504 DRM_SPINLOCK(&dev_priv->user_irq_lock);

505 if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){

506 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;

507 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);

508 }

509 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);

510

511 }

512

513 void i915_user_irq_off(drm_i915_private_t *dev_priv)

514 {

515 DRM_SPINLOCK(&dev_priv->user_irq_lock);

516 if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {

517 // dev_priv->irq_enable_reg &= ~USER_INT_FLAG;

518 // I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);

519 }

520 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);

521 }

522

523

524 static int i915_wait_irq(struct drm_device * dev, int irq_nr)

525 {

526 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

527 int ret = 0;

528

529 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,

530 READ_BREADCRUMB(dev_priv));

531

532 if (READ_BREADCRUMB(dev_priv) >= irq_nr)

533 return 0;

534

535 i915_user_irq_on(dev_priv);

536 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,

537 READ_BREADCRUMB(dev_priv) >= irq_nr);

538 i915_user_irq_off(dev_priv);

539

540 if (ret == -EBUSY) {

541 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",

542 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);

543 }

544

545 if (dev_priv->sarea_priv)

546 dev_priv->sarea_priv->last_dispatch =

547 READ_BREADCRUMB(dev_priv);

548 return ret;

549 }

550

551 /* Needs the lock as it touches the ring.

552 */

553 int i915_irq_emit(struct drm_device *dev, void *data,

554 struct drm_file *file_priv)

555 {

556 drm_i915_private_t *dev_priv = dev->dev_private;

557 drm_i915_irq_emit_t *emit = data;

558 int result;

559

560 LOCK_TEST_WITH_RETURN(dev, file_priv);

561

562 if (!dev_priv) {

563 DRM_ERROR("called with no initialization\n");

564 return -EINVAL;

565 }

566

567 result = i915_emit_irq(dev);

568

569 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {

570 DRM_ERROR("copy_to_user\n");

571 return -EFAULT;

572 }

573

574 return 0;

575 }

576

577 /* Doesn't need the hardware lock.

578 */

579 int i915_irq_wait(struct drm_device *dev, void *data,

580 struct drm_file *file_priv)

581 {

582 drm_i915_private_t *dev_priv = dev->dev_private;

583 drm_i915_irq_wait_t *irqwait = data;

584

585 if (!dev_priv) {

586 DRM_ERROR("called with no initialization\n");

587 return -EINVAL;

588 }

589

590 return i915_wait_irq(dev, irqwait->irq_seq);

591 }

592

593 int i915_enable_vblank(struct drm_device *dev, int plane)

594 {

595 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

596 int pipe = i915_get_pipe(dev, plane);

597 u32 pipestat_reg = 0;

598 u32 pipestat;

599

600 switch (pipe) {

601 case 0:

602 pipestat_reg = I915REG_PIPEASTAT;

603 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;

604 break;

605 case 1:

606 pipestat_reg = I915REG_PIPEBSTAT;

607 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;

608 break;

609 default:

610 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",

611 pipe);

612 break;

613 }

614

615 if (pipestat_reg)

616 {

617 pipestat = I915_READ (pipestat_reg);

618 /*

619 * Older chips didn't have the start vblank interrupt,

620 * but

621 */

622 if (IS_I965G (dev))

623 pipestat |= I915_START_VBLANK_INTERRUPT_ENABLE;

624 else

625 pipestat |= I915_VBLANK_INTERRUPT_ENABLE;

626 /*

627 * Clear any pending status

628 */

629 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |

630 I915_VBLANK_INTERRUPT_STATUS);

631 I915_WRITE(pipestat_reg, pipestat);

632 }

633 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);

634

635 return 0;

636 }

637

638 void i915_disable_vblank(struct drm_device *dev, int plane)

639 {

640 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

641 int pipe = i915_get_pipe(dev, plane);

642 u32 pipestat_reg = 0;

643 u32 pipestat;

644

645 switch (pipe) {

646 case 0:

647 pipestat_reg = I915REG_PIPEASTAT;

648 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;

649 break;

650 case 1:

651 pipestat_reg = I915REG_PIPEBSTAT;

652 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;

653 break;

654 default:

655 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",

656 pipe);

657 break;

658 }

659

660 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);

661 if (pipestat_reg)

662 {

663 pipestat = I915_READ (pipestat_reg);

664 pipestat &= ~(I915_START_VBLANK_INTERRUPT_ENABLE |

665 I915_VBLANK_INTERRUPT_ENABLE);

666 /*

667 * Clear any pending status

668 */

669 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |

670 I915_VBLANK_INTERRUPT_STATUS);

671 I915_WRITE(pipestat_reg, pipestat);

672 }

673 }

674

675 static void i915_enable_interrupt (struct drm_device *dev)

676 {

677 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

678

679 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;

680

681 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);

682 dev_priv->irq_enabled = 1;

683 }

684

685 /* Set the vblank monitor pipe

686 */

687 int i915_vblank_pipe_set(struct drm_device *dev, void *data,

688 struct drm_file *file_priv)

689 {

690 drm_i915_private_t *dev_priv = dev->dev_private;

691 drm_i915_vblank_pipe_t *pipe = data;

692

693 if (!dev_priv) {

694 DRM_ERROR("called with no initialization\n");

695 return -EINVAL;

696 }

697

698 if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {

699 DRM_ERROR("called with invalid pipe 0x%x\n", pipe->pipe);

700 return -EINVAL;

701 }

702

703 dev_priv->vblank_pipe = pipe->pipe;

704

705 return 0;

706 }

707

708 int i915_vblank_pipe_get(struct drm_device *dev, void *data,

709 struct drm_file *file_priv)

710 {

711 drm_i915_private_t *dev_priv = dev->dev_private;

712 drm_i915_vblank_pipe_t *pipe = data;

713 u16 flag;

714

715 if (!dev_priv) {

716 DRM_ERROR("called with no initialization\n");

717 return -EINVAL;

718 }

719

720 flag = I915_READ(I915REG_INT_ENABLE_R);

721 pipe->pipe = 0;

722 if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)

723 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;

724 if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)

725 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;

726

727 return 0;

728 }

729

730 /**

731 * Schedule buffer swap at given vertical blank.

732 */

733 int i915_vblank_swap(struct drm_device *dev, void *data,

734 struct drm_file *file_priv)

735 {

736 drm_i915_private_t *dev_priv = dev->dev_private;

737 drm_i915_vblank_swap_t *swap = data;

738 drm_i915_vbl_swap_t *vbl_swap;

739 unsigned int pipe, seqtype, curseq, plane;

740 unsigned long irqflags;

741 struct list_head *list;

742 int ret;

743

744 if (!dev_priv) {

745 DRM_ERROR("%s called with no initialization\n", __func__);

746 return -EINVAL;

747 }

748

749 if (!dev_priv->sarea_priv || dev_priv->sarea_priv->rotation) {

750 DRM_DEBUG("Rotation not supported\n");

751 return -EINVAL;

752 }

753

754 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |

755 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |

756 _DRM_VBLANK_FLIP)) {

757 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);

758 return -EINVAL;

759 }

760

761 plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;

762 pipe = i915_get_pipe(dev, plane);

763

764 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);

765

766 if (!(dev_priv->vblank_pipe & (1 << pipe))) {

767 DRM_ERROR("Invalid pipe %d\n", pipe);

768 return -EINVAL;

769 }

770

771 DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);

772

773 /* It makes no sense to schedule a swap for a drawable that doesn't have

774 * valid information at this point. E.g. this could mean that the X

775 * server is too old to push drawable information to the DRM, in which

776 * case all such swaps would become ineffective.

777 */

778 if (!drm_get_drawable_info(dev, swap->drawable)) {

779 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);

780 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);

781 return -EINVAL;

782 }

783

784 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);

785

786 drm_update_vblank_count(dev, pipe);

787 curseq = drm_vblank_count(dev, pipe);

788

789 if (seqtype == _DRM_VBLANK_RELATIVE)

790 swap->sequence += curseq;

791

792 if ((curseq - swap->sequence) <= (1<<23)) {

793 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {

794 swap->sequence = curseq + 1;

795 } else {

796 DRM_DEBUG("Missed target sequence\n");

797 return -EINVAL;

798 }

799 }

800

801 if (swap->seqtype & _DRM_VBLANK_FLIP) {

802 swap->sequence--;

803

804 if ((curseq - swap->sequence) <= (1<<23)) {

805 struct drm_drawable_info *drw;

806

807 LOCK_TEST_WITH_RETURN(dev, file_priv);

808

809 DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);

810

811 drw = drm_get_drawable_info(dev, swap->drawable);

812

813 if (!drw) {

814 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock,

815 irqflags);

816 DRM_DEBUG("Invalid drawable ID %d\n",

817 swap->drawable);

818 return -EINVAL;

819 }

820

821 i915_dispatch_vsync_flip(dev, drw, plane);

822

823 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);

824

825 return 0;

826 }

827 }

828

829 DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);

830

831 list_for_each(list, &dev_priv->vbl_swaps.head) {

832 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);

833

834 if (vbl_swap->drw_id == swap->drawable &&

835 vbl_swap->plane == plane &&

836 vbl_swap->sequence == swap->sequence) {

837 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);

838 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);

839 DRM_DEBUG("Already scheduled\n");

840 return 0;

841 }

842 }

843

844 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);

845

846 if (dev_priv->swaps_pending >= 100) {

847 DRM_DEBUG("Too many swaps queued\n");

848 return -EBUSY;

849 }

850

851 vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);

852

853 if (!vbl_swap) {

854 DRM_ERROR("Failed to allocate memory to queue swap\n");

855 return -ENOMEM;

856 }

857

858 DRM_DEBUG("\n");

859

860 ret = drm_vblank_get(dev, pipe);

861 if (ret) {

862 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);

863 return ret;

864 }

865

866 vbl_swap->drw_id = swap->drawable;

867 vbl_swap->plane = plane;

868 vbl_swap->sequence = swap->sequence;

869 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);

870

871 if (vbl_swap->flip)

872 swap->sequence++;

873

874 DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);

875

876 list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);

877 dev_priv->swaps_pending++;

878

879 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);

880

881 return 0;

882 }

883

884 /* drm_dma.h hooks

885 */

886 void i915_driver_irq_preinstall(struct drm_device * dev)

887 {

888 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

889

890 I915_WRITE16(I915REG_HWSTAM, 0xeffe);

891 I915_WRITE16(I915REG_INT_MASK_R, 0x0);

892 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);

893 }

894

895 int i915_driver_irq_postinstall(struct drm_device * dev)

896 {

897 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

898 int ret, num_pipes = 2;

899

900 DRM_SPININIT(&dev_priv->swaps_lock, "swap");

901 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);

902 dev_priv->swaps_pending = 0;

903

904 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");

905 dev_priv->user_irq_refcount = 0;

906 dev_priv->irq_enable_reg = 0;

907

908 ret = drm_vblank_init(dev, num_pipes);

909 if (ret)

910 return ret;

911

912 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */

913

914 i915_enable_interrupt(dev);

915 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);

916

917 /*

918 * Initialize the hardware status page IRQ location.

919 */

920

921 I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));

922 return 0;

923 }

924

925 void i915_driver_irq_uninstall(struct drm_device * dev)

926 {

927 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

928 u32 temp;

929

930 if (!dev_priv)

931 return;

932

933 dev_priv->irq_enabled = 0;

934 I915_WRITE(I915REG_HWSTAM, 0xffffffff);

935 I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);

936 I915_WRITE(I915REG_INT_ENABLE_R, 0x0);

937

938 temp = I915_READ(I915REG_PIPEASTAT);

939 I915_WRITE(I915REG_PIPEASTAT, temp);

940 temp = I915_READ(I915REG_PIPEBSTAT);

941 I915_WRITE(I915REG_PIPEBSTAT, temp);

942 temp = I915_READ(I915REG_INT_IDENTITY_R);

943 I915_WRITE(I915REG_INT_IDENTITY_R, temp);

944 }