3 #define NV03_BOOT_0 0x00100000
4 # define NV03_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000
6 # define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001
7 # define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002
8 # define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003
9 # define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000
10 # define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001
11 # define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002
12 # define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003
14 #define NV04_FIFO_DATA 0x0010020c
15 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
16 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
18 #define NV_RAMIN 0x00700000
20 #define NV_RAMHT_HANDLE_OFFSET 0
21 #define NV_RAMHT_CONTEXT_OFFSET 4
22 # define NV_RAMHT_CONTEXT_VALID (1<<31)
23 # define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24
24 # define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16
25 # define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0
26 # define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1
27 # define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0
28 # define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23
29 # define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20
30 # define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0
32 /* DMA object defines */
33 #define NV_DMA_ACCESS_RW 0
34 #define NV_DMA_ACCESS_RO 1
35 #define NV_DMA_ACCESS_WO 2
36 #define NV_DMA_TARGET_VIDMEM 0
37 #define NV_DMA_TARGET_PCI 2
38 #define NV_DMA_TARGET_AGP 3
39 /*The following is not a real value used by nvidia cards, it's changed by nouveau_object_dma_create*/
40 #define NV_DMA_TARGET_PCI_NONLINEAR 8
42 /* Some object classes we care about in the drm */
43 #define NV_CLASS_DMA_FROM_MEMORY 0x00000002
44 #define NV_CLASS_DMA_TO_MEMORY 0x00000003
45 #define NV_CLASS_NULL 0x00000030
46 #define NV_CLASS_DMA_IN_MEMORY 0x0000003D
48 #define NV03_USER(i) (0x00800000+(i*NV03_USER_SIZE))
49 #define NV03_USER__SIZE 16
50 #define NV10_USER__SIZE 32
51 #define NV03_USER_SIZE 0x00010000
52 #define NV03_USER_DMA_PUT(i) (0x00800040+(i*NV03_USER_SIZE))
53 #define NV03_USER_DMA_PUT__SIZE 16
54 #define NV10_USER_DMA_PUT__SIZE 32
55 #define NV03_USER_DMA_GET(i) (0x00800044+(i*NV03_USER_SIZE))
56 #define NV03_USER_DMA_GET__SIZE 16
57 #define NV10_USER_DMA_GET__SIZE 32
58 #define NV03_USER_REF_CNT(i) (0x00800048+(i*NV03_USER_SIZE))
59 #define NV03_USER_REF_CNT__SIZE 16
60 #define NV10_USER_REF_CNT__SIZE 32
62 #define NV40_USER(i) (0x00c00000+(i*NV40_USER_SIZE))
63 #define NV40_USER_SIZE 0x00001000
64 #define NV40_USER_DMA_PUT(i) (0x00c00040+(i*NV40_USER_SIZE))
65 #define NV40_USER_DMA_PUT__SIZE 32
66 #define NV40_USER_DMA_GET(i) (0x00c00044+(i*NV40_USER_SIZE))
67 #define NV40_USER_DMA_GET__SIZE 32
68 #define NV40_USER_REF_CNT(i) (0x00c00048+(i*NV40_USER_SIZE))
69 #define NV40_USER_REF_CNT__SIZE 32
71 #define NV50_USER(i) (0x00c00000+(i*NV50_USER_SIZE))
72 #define NV50_USER_SIZE 0x00002000
73 #define NV50_USER_DMA_PUT(i) (0x00c00040+(i*NV50_USER_SIZE))
74 #define NV50_USER_DMA_PUT__SIZE 128
75 #define NV50_USER_DMA_GET(i) (0x00c00044+(i*NV50_USER_SIZE))
76 #define NV50_USER_DMA_GET__SIZE 128
77 /*XXX: I don't think this actually exists.. */
78 #define NV50_USER_REF_CNT(i) (0x00c00048+(i*NV50_USER_SIZE))
79 #define NV50_USER_REF_CNT__SIZE 128
81 #define NV03_FIFO_SIZE 0x8000UL
83 #define NV03_PMC_BOOT_0 0x00000000
84 #define NV03_PMC_BOOT_1 0x00000004
85 #define NV03_PMC_INTR_0 0x00000100
86 # define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8)
87 # define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12)
88 # define NV_PMC_INTR_0_NV50_I2C_PENDING (1<<21)
89 # define NV_PMC_INTR_0_CRTC0_PENDING (1<<24)
90 # define NV_PMC_INTR_0_CRTC1_PENDING (1<<25)
91 # define NV_PMC_INTR_0_NV50_DISPLAY_PENDING (1<<26)
92 # define NV_PMC_INTR_0_CRTCn_PENDING (3<<24)
93 #define NV03_PMC_INTR_EN_0 0x00000140
94 # define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0)
95 #define NV03_PMC_ENABLE 0x00000200
96 # define NV_PMC_ENABLE_PFIFO (1<< 8)
97 # define NV_PMC_ENABLE_PGRAPH (1<<12)
98 /* Disabling the below bit breaks newer (G7X only?) mobile chipsets,
99 * the card will hang early on in the X init process.
101 # define NV_PMC_ENABLE_UNK13 (1<<13)
102 #define NV40_PMC_1700 0x00001700
103 #define NV40_PMC_1704 0x00001704
104 #define NV40_PMC_1708 0x00001708
105 #define NV40_PMC_170C 0x0000170C
108 #define NV50_PUNK_BAR0_PRAMIN 0x00001700
109 #define NV50_PUNK_BAR_CFG_BASE 0x00001704
110 #define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30)
111 #define NV50_PUNK_BAR1_CTXDMA 0x00001708
112 #define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31)
113 #define NV50_PUNK_BAR3_CTXDMA 0x0000170C
114 #define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31)
115 #define NV50_PUNK_UNK1710 0x00001710
117 #define NV04_PBUS_PCI_NV_1 0x00001804
118 #define NV04_PBUS_PCI_NV_19 0x0000184C
120 #define NV04_PTIMER_INTR_0 0x00009100
121 #define NV04_PTIMER_INTR_EN_0 0x00009140
122 #define NV04_PTIMER_NUMERATOR 0x00009200
123 #define NV04_PTIMER_DENOMINATOR 0x00009210
124 #define NV04_PTIMER_TIME_0 0x00009400
125 #define NV04_PTIMER_TIME_1 0x00009410
126 #define NV04_PTIMER_ALARM_0 0x00009420
128 #define NV50_I2C_CONTROLLER 0x0000E054
130 #define NV04_PFB_CFG0 0x00100200
131 #define NV04_PFB_CFG1 0x00100204
132 #define NV40_PFB_020C 0x0010020C
133 #define NV10_PFB_TILE(i) (0x00100240 + (i*16))
134 #define NV10_PFB_TILE__SIZE 8
135 #define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))
136 #define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))
137 #define NV10_PFB_TSTATUS(i) (0x0010024C + (i*16))
138 #define NV10_PFB_CLOSE_PAGE2 0x0010033C
139 #define NV40_PFB_TILE(i) (0x00100600 + (i*16))
140 #define NV40_PFB_TILE__SIZE_0 12
141 #define NV40_PFB_TILE__SIZE_1 15
142 #define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))
143 #define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))
144 #define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16))
145 #define NV40_PFB_UNK_800 0x00100800
147 #define NV04_PGRAPH_DEBUG_0 0x00400080
148 #define NV04_PGRAPH_DEBUG_1 0x00400084
149 #define NV04_PGRAPH_DEBUG_2 0x00400088
150 #define NV04_PGRAPH_DEBUG_3 0x0040008c
151 #define NV10_PGRAPH_DEBUG_4 0x00400090
152 #define NV03_PGRAPH_INTR 0x00400100
153 #define NV03_PGRAPH_NSTATUS 0x00400104
154 # define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11)
155 # define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12)
156 # define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13)
157 # define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14)
158 # define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23)
159 # define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24)
160 # define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25)
161 # define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26)
162 #define NV03_PGRAPH_NSOURCE 0x00400108
163 # define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<< 0)
164 # define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<< 1)
165 # define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<< 2)
166 # define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<< 3)
167 # define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<< 4)
168 # define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<< 5)
169 # define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<< 6)
170 # define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<< 7)
171 # define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<< 8)
172 # define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<< 9)
173 # define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10)
174 # define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11)
175 # define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12)
176 # define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13)
177 # define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14)
178 # define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15)
179 # define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16)
180 # define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17)
181 # define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18)
182 #define NV03_PGRAPH_INTR_EN 0x00400140
183 #define NV40_PGRAPH_INTR_EN 0x0040013C
184 # define NV_PGRAPH_INTR_NOTIFY (1<< 0)
185 # define NV_PGRAPH_INTR_MISSING_HW (1<< 4)
186 # define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)
187 # define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)
188 # define NV_PGRAPH_INTR_ERROR (1<<20)
189 #define NV10_PGRAPH_CTX_CONTROL 0x00400144
190 #define NV10_PGRAPH_CTX_USER 0x00400148
191 #define NV10_PGRAPH_CTX_SWITCH1 0x0040014C
192 #define NV10_PGRAPH_CTX_SWITCH2 0x00400150
193 #define NV10_PGRAPH_CTX_SWITCH3 0x00400154
194 #define NV10_PGRAPH_CTX_SWITCH4 0x00400158
195 #define NV10_PGRAPH_CTX_SWITCH5 0x0040015C
196 #define NV04_PGRAPH_CTX_SWITCH1 0x00400160
197 #define NV10_PGRAPH_CTX_CACHE1 0x00400160
198 #define NV04_PGRAPH_CTX_SWITCH2 0x00400164
199 #define NV04_PGRAPH_CTX_SWITCH3 0x00400168
200 #define NV04_PGRAPH_CTX_SWITCH4 0x0040016C
201 #define NV04_PGRAPH_CTX_CONTROL 0x00400170
202 #define NV04_PGRAPH_CTX_USER 0x00400174
203 #define NV04_PGRAPH_CTX_CACHE1 0x00400180
204 #define NV10_PGRAPH_CTX_CACHE2 0x00400180
205 #define NV03_PGRAPH_CTX_CONTROL 0x00400190
206 #define NV03_PGRAPH_CTX_USER 0x00400194
207 #define NV04_PGRAPH_CTX_CACHE2 0x004001A0
208 #define NV10_PGRAPH_CTX_CACHE3 0x004001A0
209 #define NV04_PGRAPH_CTX_CACHE3 0x004001C0
210 #define NV10_PGRAPH_CTX_CACHE4 0x004001C0
211 #define NV04_PGRAPH_CTX_CACHE4 0x004001E0
212 #define NV10_PGRAPH_CTX_CACHE5 0x004001E0
213 #define NV40_PGRAPH_CTXCTL_0304 0x00400304
214 #define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001
215 #define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308
216 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000
217 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24
218 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff
219 #define NV40_PGRAPH_CTXCTL_0310 0x00400310
220 #define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020
221 #define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040
222 #define NV40_PGRAPH_CTXCTL_030C 0x0040030c
223 #define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324
224 #define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328
225 #define NV40_PGRAPH_CTXCTL_CUR 0x0040032c
226 #define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000
227 #define NV40_PGRAPH_CTXCTL_CUR_INST_MASK 0x000FFFFF
228 #define NV03_PGRAPH_ABS_X_RAM 0x00400400
229 #define NV03_PGRAPH_ABS_Y_RAM 0x00400480
230 #define NV03_PGRAPH_X_MISC 0x00400500
231 #define NV03_PGRAPH_Y_MISC 0x00400504
232 #define NV04_PGRAPH_VALID1 0x00400508
233 #define NV04_PGRAPH_SOURCE_COLOR 0x0040050C
234 #define NV04_PGRAPH_MISC24_0 0x00400510
235 #define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514
236 #define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518
237 #define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C
238 #define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520
239 #define NV03_PGRAPH_CLIPX_0 0x00400524
240 #define NV03_PGRAPH_CLIPX_1 0x00400528
241 #define NV03_PGRAPH_CLIPY_0 0x0040052C
242 #define NV03_PGRAPH_CLIPY_1 0x00400530
243 #define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534
244 #define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538
245 #define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
246 #define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540
247 #define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544
248 #define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548
249 #define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560
250 #define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564
251 #define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568
252 #define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C
253 #define NV04_PGRAPH_MISC24_1 0x00400570
254 #define NV04_PGRAPH_MISC24_2 0x00400574
255 #define NV04_PGRAPH_VALID2 0x00400578
256 #define NV04_PGRAPH_PASSTHRU_0 0x0040057C
257 #define NV04_PGRAPH_PASSTHRU_1 0x00400580
258 #define NV04_PGRAPH_PASSTHRU_2 0x00400584
259 #define NV10_PGRAPH_DIMX_TEXTURE 0x00400588
260 #define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C
261 #define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590
262 #define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594
263 #define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598
264 #define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C
265 #define NV04_PGRAPH_FORMAT_0 0x004005A8
266 #define NV04_PGRAPH_FORMAT_1 0x004005AC
267 #define NV04_PGRAPH_FILTER_0 0x004005B0
268 #define NV04_PGRAPH_FILTER_1 0x004005B4
269 #define NV03_PGRAPH_MONO_COLOR0 0x00400600
270 #define NV04_PGRAPH_ROP3 0x00400604
271 #define NV04_PGRAPH_BETA_AND 0x00400608
272 #define NV04_PGRAPH_BETA_PREMULT 0x0040060C
273 #define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610
274 #define NV04_PGRAPH_FORMATS 0x00400618
275 #define NV10_PGRAPH_DEBUG_2 0x00400620
276 #define NV04_PGRAPH_BOFFSET0 0x00400640
277 #define NV04_PGRAPH_BOFFSET1 0x00400644
278 #define NV04_PGRAPH_BOFFSET2 0x00400648
279 #define NV04_PGRAPH_BOFFSET3 0x0040064C
280 #define NV04_PGRAPH_BOFFSET4 0x00400650
281 #define NV04_PGRAPH_BOFFSET5 0x00400654
282 #define NV04_PGRAPH_BBASE0 0x00400658
283 #define NV04_PGRAPH_BBASE1 0x0040065C
284 #define NV04_PGRAPH_BBASE2 0x00400660
285 #define NV04_PGRAPH_BBASE3 0x00400664
286 #define NV04_PGRAPH_BBASE4 0x00400668
287 #define NV04_PGRAPH_BBASE5 0x0040066C
288 #define NV04_PGRAPH_BPITCH0 0x00400670
289 #define NV04_PGRAPH_BPITCH1 0x00400674
290 #define NV04_PGRAPH_BPITCH2 0x00400678
291 #define NV04_PGRAPH_BPITCH3 0x0040067C
292 #define NV04_PGRAPH_BPITCH4 0x00400680
293 #define NV04_PGRAPH_BLIMIT0 0x00400684
294 #define NV04_PGRAPH_BLIMIT1 0x00400688
295 #define NV04_PGRAPH_BLIMIT2 0x0040068C
296 #define NV04_PGRAPH_BLIMIT3 0x00400690
297 #define NV04_PGRAPH_BLIMIT4 0x00400694
298 #define NV04_PGRAPH_BLIMIT5 0x00400698
299 #define NV04_PGRAPH_BSWIZZLE2 0x0040069C
300 #define NV04_PGRAPH_BSWIZZLE5 0x004006A0
301 #define NV03_PGRAPH_STATUS 0x004006B0
302 #define NV04_PGRAPH_STATUS 0x00400700
303 #define NV04_PGRAPH_TRAPPED_ADDR 0x00400704
304 #define NV04_PGRAPH_TRAPPED_DATA 0x00400708
305 #define NV04_PGRAPH_SURFACE 0x0040070C
306 #define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C
307 #define NV04_PGRAPH_STATE 0x00400710
308 #define NV10_PGRAPH_SURFACE 0x00400710
309 #define NV04_PGRAPH_NOTIFY 0x00400714
310 #define NV10_PGRAPH_STATE 0x00400714
311 #define NV10_PGRAPH_NOTIFY 0x00400718
313 #define NV04_PGRAPH_FIFO 0x00400720
315 #define NV04_PGRAPH_BPIXEL 0x00400724
316 #define NV10_PGRAPH_RDI_INDEX 0x00400750
317 #define NV04_PGRAPH_FFINTFC_ST2 0x00400754
318 #define NV10_PGRAPH_RDI_DATA 0x00400754
319 #define NV04_PGRAPH_DMA_PITCH 0x00400760
320 #define NV10_PGRAPH_FFINTFC_ST2 0x00400764
321 #define NV04_PGRAPH_DVD_COLORFMT 0x00400764
322 #define NV04_PGRAPH_SCALED_FORMAT 0x00400768
323 #define NV10_PGRAPH_DMA_PITCH 0x00400770
324 #define NV10_PGRAPH_DVD_COLORFMT 0x00400774
325 #define NV10_PGRAPH_SCALED_FORMAT 0x00400778
326 #define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780
327 #define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784
328 #define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788
329 #define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001
330 #define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002
331 #define NV04_PGRAPH_PATT_COLOR0 0x00400800
332 #define NV04_PGRAPH_PATT_COLOR1 0x00400804
333 #define NV04_PGRAPH_PATTERN 0x00400808
334 #define NV04_PGRAPH_PATTERN_SHAPE 0x00400810
335 #define NV04_PGRAPH_CHROMA 0x00400814
336 #define NV04_PGRAPH_CONTROL0 0x00400818
337 #define NV04_PGRAPH_CONTROL1 0x0040081C
338 #define NV04_PGRAPH_CONTROL2 0x00400820
339 #define NV04_PGRAPH_BLEND 0x00400824
340 #define NV04_PGRAPH_STORED_FMT 0x00400830
341 #define NV04_PGRAPH_PATT_COLORRAM 0x00400900
342 #define NV40_PGRAPH_TILE0(i) (0x00400900 + (i*16))
343 #define NV40_PGRAPH_TLIMIT0(i) (0x00400904 + (i*16))
344 #define NV40_PGRAPH_TSIZE0(i) (0x00400908 + (i*16))
345 #define NV40_PGRAPH_TSTATUS0(i) (0x0040090C + (i*16))
346 #define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16))
347 #define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16))
348 #define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16))
349 #define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16))
350 #define NV04_PGRAPH_U_RAM 0x00400D00
351 #define NV47_PGRAPH_TILE0(i) (0x00400D00 + (i*16))
352 #define NV47_PGRAPH_TLIMIT0(i) (0x00400D04 + (i*16))
353 #define NV47_PGRAPH_TSIZE0(i) (0x00400D08 + (i*16))
354 #define NV47_PGRAPH_TSTATUS0(i) (0x00400D0C + (i*16))
355 #define NV04_PGRAPH_V_RAM 0x00400D40
356 #define NV04_PGRAPH_W_RAM 0x00400D80
357 #define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40
358 #define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44
359 #define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48
360 #define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C
361 #define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50
362 #define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54
363 #define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58
364 #define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C
365 #define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60
366 #define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64
367 #define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68
368 #define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C
369 #define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00
370 #define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20
371 #define NV10_PGRAPH_XFMODE0 0x00400F40
372 #define NV10_PGRAPH_XFMODE1 0x00400F44
373 #define NV10_PGRAPH_GLOBALSTATE0 0x00400F48
374 #define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C
375 #define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50
376 #define NV10_PGRAPH_PIPE_DATA 0x00400F54
377 #define NV04_PGRAPH_DMA_START_0 0x00401000
378 #define NV04_PGRAPH_DMA_START_1 0x00401004
379 #define NV04_PGRAPH_DMA_LENGTH 0x00401008
380 #define NV04_PGRAPH_DMA_MISC 0x0040100C
381 #define NV04_PGRAPH_DMA_DATA_0 0x00401020
382 #define NV04_PGRAPH_DMA_DATA_1 0x00401024
383 #define NV04_PGRAPH_DMA_RM 0x00401030
384 #define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040
385 #define NV04_PGRAPH_DMA_A_CONTROL 0x00401044
386 #define NV04_PGRAPH_DMA_A_LIMIT 0x00401048
387 #define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C
388 #define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050
389 #define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054
390 #define NV04_PGRAPH_DMA_A_OFFSET 0x00401058
391 #define NV04_PGRAPH_DMA_A_SIZE 0x0040105C
392 #define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060
393 #define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080
394 #define NV04_PGRAPH_DMA_B_CONTROL 0x00401084
395 #define NV04_PGRAPH_DMA_B_LIMIT 0x00401088
396 #define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C
397 #define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090
398 #define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094
399 #define NV04_PGRAPH_DMA_B_OFFSET 0x00401098
400 #define NV04_PGRAPH_DMA_B_SIZE 0x0040109C
401 #define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0
402 #define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16))
403 #define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16))
404 #define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16))
405 #define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16))
408 /* It's a guess that this works on NV03. Confirmed on NV04, though */
409 #define NV04_PFIFO_DELAY_0 0x00002040
410 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
411 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
412 #define NV03_PFIFO_INTR_0 0x00002100
413 #define NV03_PFIFO_INTR_EN_0 0x00002140
414 # define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)
415 # define NV_PFIFO_INTR_RUNOUT (1<< 4)
416 # define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8)
417 # define NV_PFIFO_INTR_DMA_PUSHER (1<<12)
418 # define NV_PFIFO_INTR_DMA_PT (1<<16)
419 # define NV_PFIFO_INTR_SEMAPHORE (1<<20)
420 # define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)
421 #define NV03_PFIFO_RAMHT 0x00002210
422 #define NV03_PFIFO_RAMFC 0x00002214
423 #define NV03_PFIFO_RAMRO 0x00002218
424 #define NV40_PFIFO_RAMFC 0x00002220
425 #define NV03_PFIFO_CACHES 0x00002500
426 #define NV04_PFIFO_MODE 0x00002504
427 #define NV04_PFIFO_DMA 0x00002508
428 #define NV04_PFIFO_SIZE 0x0000250c
429 #define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4)
430 #define NV50_PFIFO_CTX_TABLE__SIZE 128
431 #define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31)
432 #define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30)
433 #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF
434 #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF
435 #define NV03_PFIFO_CACHE0_PUSH0 0x00003000
436 #define NV03_PFIFO_CACHE0_PULL0 0x00003040
437 #define NV04_PFIFO_CACHE0_PULL0 0x00003050
438 #define NV04_PFIFO_CACHE0_PULL1 0x00003054
439 #define NV03_PFIFO_CACHE1_PUSH0 0x00003200
440 #define NV03_PFIFO_CACHE1_PUSH1 0x00003204
441 #define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8)
442 #define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16)
443 #define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f
444 #define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f
445 #define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f
446 #define NV03_PFIFO_CACHE1_PUT 0x00003210
447 #define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
448 #define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
449 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000
450 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008
451 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010
452 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018
453 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020
454 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028
455 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030
456 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038
457 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040
458 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048
459 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050
460 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058
461 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060
462 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068
463 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070
464 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078
465 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080
466 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088
467 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090
468 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098
469 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0
470 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8
471 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0
472 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8
473 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0
474 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8
475 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0
476 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8
477 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0
478 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8
479 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0
480 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8
481 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000
482 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000
483 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000
484 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000
485 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000
486 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000
487 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000
488 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000
489 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000
490 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000
491 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000
492 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000
493 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000
494 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000
495 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000
496 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000
497 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000
498 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000
499 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000
500 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000
501 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000
502 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000
503 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000
504 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000
505 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000
506 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000
507 # define NV_PFIFO_CACHE1_ENDIAN 0x80000000
508 # define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF
509 # define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000
510 #define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228
511 #define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c
512 #define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230
513 #define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240
514 #define NV04_PFIFO_CACHE1_DMA_GET 0x00003244
515 #define NV10_PFIFO_CACHE1_REF_CNT 0x00003248
516 #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C
517 #define NV03_PFIFO_CACHE1_PULL0 0x00003240
518 #define NV04_PFIFO_CACHE1_PULL0 0x00003250
519 #define NV03_PFIFO_CACHE1_PULL1 0x00003250
520 #define NV04_PFIFO_CACHE1_PULL1 0x00003254
521 #define NV04_PFIFO_CACHE1_HASH 0x00003258
522 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260
523 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264
524 #define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268
525 #define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C
526 #define NV03_PFIFO_CACHE1_GET 0x00003270
527 #define NV04_PFIFO_CACHE1_ENGINE 0x00003280
528 #define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0
529 #define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0
530 #define NV40_PFIFO_UNK32E4 0x000032E4
531 #define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))
532 #define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))
533 #define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))
534 #define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))
536 #define NV_CRTC0_INTSTAT 0x00600100
537 #define NV_CRTC0_INTEN 0x00600140
538 #define NV_CRTC1_INTSTAT 0x00602100
539 #define NV_CRTC1_INTEN 0x00602140
540 # define NV_CRTC_INTR_VBLANK (1<<0)
542 /* This name is a partial guess. */
543 #define NV50_DISPLAY_SUPERVISOR 0x00610024
545 /* Fifo commands. These are not regs, neither masks */
546 #define NV03_FIFO_CMD_JUMP 0x20000000
547 #define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc
548 #define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))
551 #define NV04_RAMFC_DMA_PUT 0x00
552 #define NV04_RAMFC_DMA_GET 0x04
553 #define NV04_RAMFC_DMA_INSTANCE 0x08
554 #define NV04_RAMFC_DMA_STATE 0x0C
555 #define NV04_RAMFC_DMA_FETCH 0x10
556 #define NV04_RAMFC_ENGINE 0x14
557 #define NV04_RAMFC_PULL1_ENGINE 0x18
559 #define NV10_RAMFC_DMA_PUT 0x00
560 #define NV10_RAMFC_DMA_GET 0x04
561 #define NV10_RAMFC_REF_CNT 0x08
562 #define NV10_RAMFC_DMA_INSTANCE 0x0C
563 #define NV10_RAMFC_DMA_STATE 0x10
564 #define NV10_RAMFC_DMA_FETCH 0x14
565 #define NV10_RAMFC_ENGINE 0x18
566 #define NV10_RAMFC_PULL1_ENGINE 0x1C
567 #define NV10_RAMFC_ACQUIRE_VALUE 0x20
568 #define NV10_RAMFC_ACQUIRE_TIMESTAMP 0x24
569 #define NV10_RAMFC_ACQUIRE_TIMEOUT 0x28
570 #define NV10_RAMFC_SEMAPHORE 0x2C
571 #define NV10_RAMFC_DMA_SUBROUTINE 0x30
573 #define NV40_RAMFC_DMA_PUT 0x00
574 #define NV40_RAMFC_DMA_GET 0x04
575 #define NV40_RAMFC_REF_CNT 0x08
576 #define NV40_RAMFC_DMA_INSTANCE 0x0C
577 #define NV40_RAMFC_DMA_DCOUNT /* ? */ 0x10
578 #define NV40_RAMFC_DMA_STATE 0x14
579 #define NV40_RAMFC_DMA_FETCH 0x18
580 #define NV40_RAMFC_ENGINE 0x1C
581 #define NV40_RAMFC_PULL1_ENGINE 0x20
582 #define NV40_RAMFC_ACQUIRE_VALUE 0x24
583 #define NV40_RAMFC_ACQUIRE_TIMESTAMP 0x28
584 #define NV40_RAMFC_ACQUIRE_TIMEOUT 0x2C
585 #define NV40_RAMFC_SEMAPHORE 0x30
586 #define NV40_RAMFC_DMA_SUBROUTINE 0x34
587 #define NV40_RAMFC_GRCTX_INSTANCE /* guess */ 0x38
588 #define NV40_RAMFC_DMA_TIMESLICE 0x3C
589 #define NV40_RAMFC_UNK_40 0x40
590 #define NV40_RAMFC_UNK_44 0x44
591 #define NV40_RAMFC_UNK_48 0x48
592 #define NV40_RAMFC_UNK_4C 0x4C
593 #define NV40_RAMFC_UNK_50 0x50