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1 /*

4 *

5 * Permission is hereby granted, free of charge, to any person obtaining

6 * a copy of this software and associated documentation files (the

7 * "Software"), to deal in the Software without restriction, including

8 * without limitation the rights to use, copy, modify, merge, publish,

9 * distribute, sublicense, and/or sell copies of the Software, and to

10 * permit persons to whom the Software is furnished to do so, subject to

11 * the following conditions:

12 *

13 * The above copyright notice and this permission notice (including the

14 * next paragraph) shall be included in all copies or substantial

15 * portions of the Software.

16 *

17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE

21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION

22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION

23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

24 *

25 */

26

27 #include "drmP.h"

28 #include "drm.h"

29 #include "nouveau_drv.h"

30

31 #define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \

32 NV04_RAMFC_##offset/4, (val))

33 #define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \

34 NV04_RAMFC_##offset/4)

35 #define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE))

36 #define NV04_RAMFC__SIZE 32

37

38 int

39 nv04_fifo_create_context(struct drm_device *dev, int channel)

40 {

41 struct drm_nouveau_private *dev_priv = dev->dev_private;

42 struct nouveau_fifo *chan = dev_priv->fifos[channel];

43 int ret;

44

45 if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(channel),

46 NV04_RAMFC__SIZE,

47 NVOBJ_FLAG_ZERO_ALLOC |

48 NVOBJ_FLAG_ZERO_FREE,

49 NULL, &chan->ramfc)))

50 return ret;

51

52 /* Setup initial state */

53 RAMFC_WR(DMA_PUT, chan->pushbuf_base);

54 RAMFC_WR(DMA_GET, chan->pushbuf_base);

55 RAMFC_WR(DMA_INSTANCE, chan->pushbuf->instance >> 4);

56 RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |

57 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |

58 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |

59 #ifdef __BIG_ENDIAN

60 NV_PFIFO_CACHE1_BIG_ENDIAN |

61 #endif

62 0));

63

64 /* enable the fifo dma operation */

65 NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<channel));

66 return 0;

67 }

68

69 void

70 nv04_fifo_destroy_context(struct drm_device *dev, int channel)

71 {

72 struct drm_nouveau_private *dev_priv = dev->dev_private;

73 struct nouveau_fifo *chan = dev_priv->fifos[channel];

74

75 NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<channel));

76

77 if (chan->ramfc)

78 nouveau_gpuobj_ref_del(dev, &chan->ramfc);

79 }

80

81 int

82 nv04_fifo_load_context(struct drm_device *dev, int channel)

83 {

84 struct drm_nouveau_private *dev_priv = dev->dev_private;

85 struct nouveau_fifo *chan = dev_priv->fifos[channel];

86 uint32_t tmp;

87

88 NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | channel);

89

90 NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));

91 NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));

92

93 tmp = RAMFC_RD(DMA_INSTANCE);

94 NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);

95 NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);

96

97 NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE));

98 NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH));

99 NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE));

100 NV_WRITE(NV04_PFIFO_CACHE1_PULL1, RAMFC_RD(PULL1_ENGINE));

101

102 /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */

103 tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);

104 NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);

105

106 return 0;

107 }

108

109 int

110 nv04_fifo_save_context(struct drm_device *dev, int channel)

111 {

112 struct drm_nouveau_private *dev_priv = dev->dev_private;

113 struct nouveau_fifo *chan = dev_priv->fifos[channel];

114 uint32_t tmp;

115

116 RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT);

117 RAMFC_WR(DMA_GET, NV04_PFIFO_CACHE1_DMA_GET);

118

119 tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;

120 tmp |= NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE);

121 RAMFC_WR(DMA_INSTANCE, tmp);

122

123 RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));

124 RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));

125 RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE));

126 RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1));

127

128 return 0;

129 }

130