3 #include "nouveau_drv.h"
6 nv04_instmem_determine_amount(struct drm_device *dev)
8 struct drm_nouveau_private *dev_priv = dev->dev_private;
11 /* Figure out how much instance memory we need */
12 if (dev_priv->card_type >= NV_40) {
13 /* We'll want more instance memory than this on some NV4x cards.
14 * There's a 16MB aperture to play with that maps onto the end
15 * of vram. For now, only reserve a small piece until we know
16 * more about what each chipset requires.
18 dev_priv->ramin_rsvd_vram = (1*1024* 1024);
20 /*XXX: what *are* the limits on <NV40 cards?
22 dev_priv->ramin_rsvd_vram = (512*1024);
24 DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram>>10);
26 /* Clear all of it, except the BIOS image that's in the first 64KiB */
27 for (i=(64*1024); i<dev_priv->ramin_rsvd_vram; i+=4)
28 NV_WI32(i, 0x00000000);
32 nv04_instmem_configure_fixed_tables(struct drm_device *dev)
34 struct drm_nouveau_private *dev_priv = dev->dev_private;
35 struct nouveau_engine *engine = &dev_priv->Engine;
37 /* FIFO hash table (RAMHT)
38 * use 4k hash table at RAMIN+0x10000
39 * TODO: extend the hash table
41 dev_priv->ramht_offset = 0x10000;
42 dev_priv->ramht_bits = 9;
43 dev_priv->ramht_size = (1 << dev_priv->ramht_bits); /* nr entries */
44 dev_priv->ramht_size *= 8; /* 2 32-bit values per entry in RAMHT */
45 DRM_DEBUG("RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset,
46 dev_priv->ramht_size);
48 /* FIFO runout table (RAMRO) - 512k at 0x11200 */
49 dev_priv->ramro_offset = 0x11200;
50 dev_priv->ramro_size = 512;
51 DRM_DEBUG("RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset,
52 dev_priv->ramro_size);
54 /* FIFO context table (RAMFC)
55 * NV40 : Not sure exactly how to position RAMFC on some cards,
56 * 0x30002 seems to position it at RAMIN+0x20000 on these
57 * cards. RAMFC is 4kb (32 fifos, 128byte entries).
58 * Others: Position RAMFC at RAMIN+0x11400
60 switch(dev_priv->card_type)
64 dev_priv->ramfc_offset = 0x20000;
65 dev_priv->ramfc_size = engine->fifo.channels *
66 nouveau_fifo_ctx_size(dev);
75 dev_priv->ramfc_offset = 0x11400;
76 dev_priv->ramfc_size = engine->fifo.channels *
77 nouveau_fifo_ctx_size(dev);
80 DRM_DEBUG("RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset,
81 dev_priv->ramfc_size);
84 int nv04_instmem_init(struct drm_device *dev)
86 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 nv04_instmem_determine_amount(dev);
91 nv04_instmem_configure_fixed_tables(dev);
93 /* Create a heap to manage RAMIN allocations, we don't allocate
94 * the space that was reserved for RAMHT/FC/RO.
96 offset = dev_priv->ramfc_offset + dev_priv->ramfc_size;
98 /* On my NV4E, there's *something* clobbering the 16KiB just after
99 * where we setup these fixed tables. No idea what it is just yet,
100 * so reserve this space on all NV4X cards for now.
102 if (dev_priv->card_type >= NV_40)
105 ret = nouveau_mem_init_heap(&dev_priv->ramin_heap,
106 offset, dev_priv->ramin_rsvd_vram - offset);
108 dev_priv->ramin_heap = NULL;
109 DRM_ERROR("Failed to init RAMIN heap\n");
116 nv04_instmem_takedown(struct drm_device *dev)
121 nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz)
123 if (gpuobj->im_backing)
130 nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
132 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 if (gpuobj && gpuobj->im_backing) {
135 if (gpuobj->im_bound)
136 dev_priv->Engine.instmem.unbind(dev, gpuobj);
137 gpuobj->im_backing = NULL;
142 nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
144 if (!gpuobj->im_pramin || gpuobj->im_bound)
147 gpuobj->im_bound = 1;
152 nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
154 if (gpuobj->im_bound == 0)
157 gpuobj->im_bound = 0;