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1 /*

4 *

5 * Permission is hereby granted, free of charge, to any person obtaining a

6 * copy of this software and associated documentation files (the "Software"),

7 * to deal in the Software without restriction, including without limitation

8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

9 * and/or sell copies of the Software, and to permit persons to whom the

10 * Software is furnished to do so, subject to the following conditions:

11 *

12 * The above copyright notice and this permission notice (including the next

13 * paragraph) shall be included in all copies or substantial portions of the

14 * Software.

15 *

16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR

20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

22 * DEALINGS IN THE SOFTWARE.

23 */

24

25 #include "drmP.h"

26 #include "drm.h"

27 #include "nouveau_drv.h"

28 #include "nouveau_drm.h"

29

30 #define NV20_GRCTX_SIZE (3529*4)

31

32 int nv20_graph_context_create(drm_device_t *dev, int channel) {

33 drm_nouveau_private_t *dev_priv =

34 (drm_nouveau_private_t *)dev->dev_private;

35 struct nouveau_fifo *chan = &dev_priv->fifos[channel];

36 unsigned int ctx_size = NV20_GRCTX_SIZE;

37 int i;

38

39 /* Alloc and clear RAMIN to store the context */

40 chan->ramin_grctx = nouveau_instmem_alloc(dev, ctx_size, 4);

41 if (!chan->ramin_grctx)

42 return DRM_ERR(ENOMEM);

43 for (i=0; i<ctx_size; i+=4)

44 INSTANCE_WR(chan->ramin_grctx, i/4, 0x00000000);

45

46 /* Initialise default context values */

47 INSTANCE_WR(chan->ramin_grctx, 10, channel << 24); /* CTX_USER */

48

49 INSTANCE_WR(dev_priv->ctx_table, channel, nouveau_chip_instance_get(dev, chan->ramin_grctx));

50

51 return 0;

52 }

53

54 static void nv20_graph_rdi(drm_device_t *dev) {

55 drm_nouveau_private_t *dev_priv =

56 (drm_nouveau_private_t *)dev->dev_private;

57 int i;

58

59 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000);

60 for (i = 0; i < 32; i++)

61 NV_WRITE(NV10_PGRAPH_RDI_DATA, 0);

62

63 nouveau_wait_for_idle(dev);

64 }

65

66 /* Save current context (from PGRAPH) into the channel's context

67 */

68 static void nv20_graph_context_save_current(drm_device_t *dev, int channel) {

69 drm_nouveau_private_t *dev_priv =

70 (drm_nouveau_private_t *)dev->dev_private;

71 uint32_t instance;

72

73 instance = INSTANCE_RD(dev_priv->ctx_table, channel);

74 if (!instance) {

75 return;

76 }

77 if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx))

78 DRM_ERROR("nv20_graph_context_save_current : bad instance\n");

79

80 NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance);

81 NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */);

82 }

83

84

85 /* Restore the context for a specific channel into PGRAPH

86 */

87 static void nv20_graph_context_restore(drm_device_t *dev, int channel) {

88 drm_nouveau_private_t *dev_priv =

89 (drm_nouveau_private_t *)dev->dev_private;

90 uint32_t instance;

91

92 instance = INSTANCE_RD(dev_priv->ctx_table, channel);

93 if (!instance) {

94 return;

95 }

96 if (instance != nouveau_chip_instance_get(dev, dev_priv->fifos[channel].ramin_grctx))

97 DRM_ERROR("nv20_graph_context_restore_current : bad instance\n");

98

99 NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24);

100 NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance);

101 NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */);

102 }

103

104 void nouveau_nv20_context_switch(drm_device_t *dev)

105 {

106 drm_nouveau_private_t *dev_priv = dev->dev_private;

107 int channel, channel_old;

108

109 channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);

110 channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);

111

112 DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);

113

114 NV_WRITE(NV04_PGRAPH_FIFO,0x0);

115

116 nv20_graph_context_save_current(dev, channel_old);

117

118 nouveau_wait_for_idle(dev);

119

120 NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000);

121

122 nv20_graph_context_restore(dev, channel);

123

124 nouveau_wait_for_idle(dev);

125

126 if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != channel)

127 DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", channel, NV_READ(NV10_PGRAPH_CTX_USER) >> 24);

128

129 NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);

130 NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);

131

132 NV_WRITE(NV04_PGRAPH_FIFO,0x1);

133 }

134

135 int nv20_graph_init(drm_device_t *dev) {

136 drm_nouveau_private_t *dev_priv =

137 (drm_nouveau_private_t *)dev->dev_private;

138 int i;

139 uint32_t tmp, vramsz;

140

141 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &

142 ~NV_PMC_ENABLE_PGRAPH);

143 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |

144 NV_PMC_ENABLE_PGRAPH);

145

146 /* Create Context Pointer Table */

147 dev_priv->ctx_table_size = 32 * 4;

148 dev_priv->ctx_table = nouveau_instmem_alloc(dev, dev_priv->ctx_table_size, 4);

149 if (!dev_priv->ctx_table)

150 return DRM_ERR(ENOMEM);

151

152 for (i=0; i< dev_priv->ctx_table_size; i+=4)

153 INSTANCE_WR(dev_priv->ctx_table, i/4, 0x00000000);

154

155 NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE, nouveau_chip_instance_get(dev, dev_priv->ctx_table));

156

157 //XXX need to be done and save/restore for each fifo ???

158 nv20_graph_rdi(dev);

159

160 NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000);

161 NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);

162

163 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);

164 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);

165 NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700);

166 NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF20E0431);

167 NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000);

168 NV_WRITE(0x40009C , 0x00000040);

169

170 if (dev_priv->chipset >= 0x25) {

171 NV_WRITE(0x400890, 0x00080000);

172 NV_WRITE(0x400610, 0x304B1FB6);

173 NV_WRITE(0x400B80, 0x18B82880);

174 NV_WRITE(0x400B84, 0x44000000);

175 NV_WRITE(0x400098, 0x40000080);

176 NV_WRITE(0x400B88, 0x000000ff);

177 } else {

178 NV_WRITE(0x400880, 0x00080000);

179 NV_WRITE(0x400094, 0x00000005);

180 NV_WRITE(0x400B80, 0x45CAA208);

181 NV_WRITE(0x400B84, 0x24000000);

182 NV_WRITE(0x400098, 0x00000040);

183 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038);

184 NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);

185 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038);

186 NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);

187 }

188

189 /* copy tile info from PFB */

190 for (i=0; i<NV10_PFB_TILE__SIZE; i++) {

191 NV_WRITE(NV10_PGRAPH_TILE(i), NV_READ(NV10_PFB_TILE(i)));

192 NV_WRITE(NV10_PGRAPH_TLIMIT(i), NV_READ(NV10_PFB_TLIMIT(i)));

193 NV_WRITE(NV10_PGRAPH_TSIZE(i), NV_READ(NV10_PFB_TSIZE(i)));

194 NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i)));

195 }

196

197 NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);

198 NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);

199 NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);

200

201 tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;

202 NV_WRITE(NV10_PGRAPH_SURFACE, tmp);

203 tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;

204 NV_WRITE(NV10_PGRAPH_SURFACE, tmp);

205

206 /* begin RAM config */

207 vramsz = drm_get_resource_len(dev, 0) - 1;

208 NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));

209 NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));

210 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000);

211 NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG0));

212 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004);

213 NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG1));

214 NV_WRITE(0x400820, 0);

215 NV_WRITE(0x400824, 0);

216 NV_WRITE(0x400864, vramsz-1);

217 NV_WRITE(0x400868, vramsz-1);

218

219 /* interesting.. the below overwrites some of the tile setup above.. */

220 NV_WRITE(0x400B20, 0x00000000);

221 NV_WRITE(0x400B04, 0xFFFFFFFF);

222

223 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);

224 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);

225 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);

226 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);

227

228 return 0;

229 }

230

231 void nv20_graph_takedown(drm_device_t *dev)

232 {

233 }

234