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1 #include "drmP.h"

2 #include "drm.h"

3 #include "nouveau_drv.h"

4 #include "nouveau_drm.h"

5

6 /* The sizes are taken from the difference between the start of two

7 * grctx addresses while running the nvidia driver. Probably slightly

8 * larger than they actually are, because of other objects being created

9 * between the contexts

10 */

11 #define NV40_GRCTX_SIZE (175*1024)

12 #define NV43_GRCTX_SIZE (70*1024)

13 #define NV46_GRCTX_SIZE (70*1024) /* probably ~64KiB */

14 #define NV4A_GRCTX_SIZE (64*1024)

15 #define NV4C_GRCTX_SIZE (25*1024)

16 #define NV4E_GRCTX_SIZE (25*1024)

17

18 /*TODO: deciper what each offset in the context represents. The below

19 * contexts are taken from dumps just after the 3D object is

20 * created.

21 */

22 static void nv40_graph_context_init(drm_device_t *dev, struct mem_block *ctx)

23 {

24 drm_nouveau_private_t *dev_priv = dev->dev_private;

25 int i;

26

27 /* Always has the "instance address" of itself at offset 0 */

28 INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx));

29 /* unknown */

30 INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);

31 INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);

32 INSTANCE_WR(ctx, 0x00030/4, 0x00000001);

33 INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);

34 INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);

35 INSTANCE_WR(ctx, 0x00128/4, 0x02008821);

36 INSTANCE_WR(ctx, 0x0016c/4, 0x00000040);

37 INSTANCE_WR(ctx, 0x00170/4, 0x00000040);

38 INSTANCE_WR(ctx, 0x00174/4, 0x00000040);

39 INSTANCE_WR(ctx, 0x0017c/4, 0x80000000);

40 INSTANCE_WR(ctx, 0x00180/4, 0x80000000);

41 INSTANCE_WR(ctx, 0x00184/4, 0x80000000);

42 INSTANCE_WR(ctx, 0x00188/4, 0x80000000);

43 INSTANCE_WR(ctx, 0x0018c/4, 0x80000000);

44 INSTANCE_WR(ctx, 0x0019c/4, 0x00000040);

45 INSTANCE_WR(ctx, 0x001a0/4, 0x80000000);

46 INSTANCE_WR(ctx, 0x001b0/4, 0x80000000);

47 INSTANCE_WR(ctx, 0x001c0/4, 0x80000000);

48 INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);

49 INSTANCE_WR(ctx, 0x00340/4, 0x00040000);

50 INSTANCE_WR(ctx, 0x00350/4, 0x55555555);

51 INSTANCE_WR(ctx, 0x00354/4, 0x55555555);

52 INSTANCE_WR(ctx, 0x00358/4, 0x55555555);

53 INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);

54 INSTANCE_WR(ctx, 0x00388/4, 0x00000008);

55 INSTANCE_WR(ctx, 0x0039c/4, 0x00000010);

56 INSTANCE_WR(ctx, 0x00480/4, 0x00000100);

57 INSTANCE_WR(ctx, 0x00494/4, 0x00000111);

58 INSTANCE_WR(ctx, 0x00498/4, 0x00080060);

59 INSTANCE_WR(ctx, 0x004b4/4, 0x00000080);

60 INSTANCE_WR(ctx, 0x004b8/4, 0xffff0000);

61 INSTANCE_WR(ctx, 0x004bc/4, 0x00000001);

62 INSTANCE_WR(ctx, 0x004d0/4, 0x46400000);

63 INSTANCE_WR(ctx, 0x004ec/4, 0xffff0000);

64 INSTANCE_WR(ctx, 0x004f8/4, 0x0fff0000);

65 INSTANCE_WR(ctx, 0x004fc/4, 0x0fff0000);

66 INSTANCE_WR(ctx, 0x00504/4, 0x00011100);

67 for (i=0x00520; i<=0x0055c; i+=4)

68 INSTANCE_WR(ctx, i/4, 0x07ff0000);

69 INSTANCE_WR(ctx, 0x00568/4, 0x4b7fffff);

70 INSTANCE_WR(ctx, 0x00594/4, 0x30201000);

71 INSTANCE_WR(ctx, 0x00598/4, 0x70605040);

72 INSTANCE_WR(ctx, 0x0059c/4, 0xb8a89888);

73 INSTANCE_WR(ctx, 0x005a0/4, 0xf8e8d8c8);

74 INSTANCE_WR(ctx, 0x005b4/4, 0x40100000);

75 INSTANCE_WR(ctx, 0x005cc/4, 0x00000004);

76 INSTANCE_WR(ctx, 0x005d8/4, 0x0000ffff);

77 INSTANCE_WR(ctx, 0x0060c/4, 0x435185d6);

78 INSTANCE_WR(ctx, 0x00610/4, 0x2155b699);

79 INSTANCE_WR(ctx, 0x00614/4, 0xfedcba98);

80 INSTANCE_WR(ctx, 0x00618/4, 0x00000098);

81 INSTANCE_WR(ctx, 0x00628/4, 0xffffffff);

82 INSTANCE_WR(ctx, 0x0062c/4, 0x00ff7000);

83 INSTANCE_WR(ctx, 0x00630/4, 0x0000ffff);

84 INSTANCE_WR(ctx, 0x00640/4, 0x00ff0000);

85 INSTANCE_WR(ctx, 0x0067c/4, 0x00ffff00);

86 /* 0x680-0x6BC - NV30_TCL_PRIMITIVE_3D_TX_ADDRESS_UNIT(0-15) */

87 /* 0x6C0-0x6FC - NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT(0-15) */

88 for (i=0x006C0; i<=0x006fc; i+=4)

89 INSTANCE_WR(ctx, i/4, 0x00018488);

90 /* 0x700-0x73C - NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT(0-15) */

91 for (i=0x00700; i<=0x0073c; i+=4)

92 INSTANCE_WR(ctx, i/4, 0x00028202);

93 /* 0x740-0x77C - NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT(0-15) */

94 /* 0x780-0x7BC - NV30_TCL_PRIMITIVE_3D_TX_SWIZZLE_UNIT(0-15) */

95 for (i=0x00780; i<=0x007bc; i+=4)

96 INSTANCE_WR(ctx, i/4, 0x0000aae4);

97 /* 0x7C0-0x7FC - NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT(0-15) */

98 for (i=0x007c0; i<=0x007fc; i+=4)

99 INSTANCE_WR(ctx, i/4, 0x01012000);

100 /* 0x800-0x83C - NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT(0-15) */

101 for (i=0x00800; i<=0x0083c; i+=4)

102 INSTANCE_WR(ctx, i/4, 0x00080008);

103 /* 0x840-0x87C - NV30_TCL_PRIMITIVE_3D_TX_UNK07_UNIT(0-15) */

104 /* 0x880-0x8BC - NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT(0-15) */

105 for (i=0x00880; i<=0x008bc; i+=4)

106 INSTANCE_WR(ctx, i/4, 0x00100008);

107 /* unknown */

108 for (i=0x00910; i<=0x0091c; i+=4)

109 INSTANCE_WR(ctx, i/4, 0x0001bc80);

110 for (i=0x00920; i<=0x0092c; i+=4)

111 INSTANCE_WR(ctx, i/4, 0x00000202);

112 for (i=0x00940; i<=0x0094c; i+=4)

113 INSTANCE_WR(ctx, i/4, 0x00000008);

114 for (i=0x00960; i<=0x0096c; i+=4)

115 INSTANCE_WR(ctx, i/4, 0x00080008);

116 INSTANCE_WR(ctx, 0x00980/4, 0x00000002);

117 INSTANCE_WR(ctx, 0x009b4/4, 0x00000001);

118 INSTANCE_WR(ctx, 0x009c0/4, 0x3e020200);

119 INSTANCE_WR(ctx, 0x009c4/4, 0x00ffffff);

120 INSTANCE_WR(ctx, 0x009c8/4, 0x60103f00);

121 INSTANCE_WR(ctx, 0x009d4/4, 0x00020000);

122 INSTANCE_WR(ctx, 0x00a08/4, 0x00008100);

123 INSTANCE_WR(ctx, 0x00aac/4, 0x00000001);

124 INSTANCE_WR(ctx, 0x00af0/4, 0x00000001);

125 INSTANCE_WR(ctx, 0x00af8/4, 0x80800001);

126 INSTANCE_WR(ctx, 0x00bcc/4, 0x00000005);

127 INSTANCE_WR(ctx, 0x00bf8/4, 0x00005555);

128 INSTANCE_WR(ctx, 0x00bfc/4, 0x00005555);

129 INSTANCE_WR(ctx, 0x00c00/4, 0x00005555);

130 INSTANCE_WR(ctx, 0x00c04/4, 0x00005555);

131 INSTANCE_WR(ctx, 0x00c08/4, 0x00005555);

132 INSTANCE_WR(ctx, 0x00c0c/4, 0x00005555);

133 INSTANCE_WR(ctx, 0x00c44/4, 0x00000001);

134 for (i=0x03008; i<=0x03080; i+=8)

135 INSTANCE_WR(ctx, i/4, 0x3f800000);

136 for (i=0x05288; i<=0x08570; i+=24)

137 INSTANCE_WR(ctx, i/4, 0x00000001);

138 for (i=0x08628; i<=0x08e18; i+=16)

139 INSTANCE_WR(ctx, i/4, 0x3f800000);

140 for (i=0x0bd28; i<=0x0f010; i+=24)

141 INSTANCE_WR(ctx, i/4, 0x00000001);

142 for (i=0x0f0c8; i<=0x0f8b8; i+=16)

143 INSTANCE_WR(ctx, i/4, 0x3f800000);

144 for (i=0x127c8; i<=0x15ab0; i+=24)

145 INSTANCE_WR(ctx, i/4, 0x00000001);

146 for (i=0x15b68; i<=0x16358; i+=16)

147 INSTANCE_WR(ctx, i/4, 0x3f800000);

148 for (i=0x19268; i<=0x1c550; i+=24)

149 INSTANCE_WR(ctx, i/4, 0x00000001);

150 for (i=0x1c608; i<=0x1cdf8; i+=16)

151 INSTANCE_WR(ctx, i/4, 0x3f800000);

152 for (i=0x1fd08; i<=0x22ff0; i+=24)

153 INSTANCE_WR(ctx, i/4, 0x00000001);

154 for (i=0x230a8; i<=0x23898; i+=16)

155 INSTANCE_WR(ctx, i/4, 0x3f800000);

156 for (i=0x267a8; i<=0x29a90; i+=24)

157 INSTANCE_WR(ctx, i/4, 0x00000001);

158 for (i=0x29b48; i<=0x2a338; i+=16)

159 INSTANCE_WR(ctx, i/4, 0x3f800000);

160 }

161

162 static void

163 nv43_graph_context_init(drm_device_t *dev, struct mem_block *ctx)

164 {

165 drm_nouveau_private_t *dev_priv = dev->dev_private;

166 int i;

167

168 INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx));

169 INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);

170 INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);

171 INSTANCE_WR(ctx, 0x00030/4, 0x00000001);

172 INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);

173 INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);

174 INSTANCE_WR(ctx, 0x00128/4, 0x02008821);

175 INSTANCE_WR(ctx, 0x00178/4, 0x00000040);

176 INSTANCE_WR(ctx, 0x0017c/4, 0x00000040);

177 INSTANCE_WR(ctx, 0x00180/4, 0x00000040);

178 INSTANCE_WR(ctx, 0x00188/4, 0x00000040);

179 INSTANCE_WR(ctx, 0x00194/4, 0x80000000);

180 INSTANCE_WR(ctx, 0x00198/4, 0x80000000);

181 INSTANCE_WR(ctx, 0x0019c/4, 0x80000000);

182 INSTANCE_WR(ctx, 0x001a0/4, 0x80000000);

183 INSTANCE_WR(ctx, 0x001a4/4, 0x80000000);

184 INSTANCE_WR(ctx, 0x001a8/4, 0x80000000);

185 INSTANCE_WR(ctx, 0x001ac/4, 0x80000000);

186 INSTANCE_WR(ctx, 0x001b0/4, 0x80000000);

187 INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);

188 INSTANCE_WR(ctx, 0x00340/4, 0x00040000);

189 INSTANCE_WR(ctx, 0x00350/4, 0x55555555);

190 INSTANCE_WR(ctx, 0x00354/4, 0x55555555);

191 INSTANCE_WR(ctx, 0x00358/4, 0x55555555);

192 INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);

193 INSTANCE_WR(ctx, 0x00388/4, 0x00000008);

194 INSTANCE_WR(ctx, 0x0039c/4, 0x00001010);

195 INSTANCE_WR(ctx, 0x003cc/4, 0x00000111);

196 INSTANCE_WR(ctx, 0x003d0/4, 0x00080060);

197 INSTANCE_WR(ctx, 0x003ec/4, 0x00000080);

198 INSTANCE_WR(ctx, 0x003f0/4, 0xffff0000);

199 INSTANCE_WR(ctx, 0x003f4/4, 0x00000001);

200 INSTANCE_WR(ctx, 0x00408/4, 0x46400000);

201 INSTANCE_WR(ctx, 0x00418/4, 0xffff0000);

202 INSTANCE_WR(ctx, 0x00424/4, 0x0fff0000);

203 INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000);

204 INSTANCE_WR(ctx, 0x00430/4, 0x00011100);

205 for (i=0x0044c; i<=0x00488; i+=4)

206 INSTANCE_WR(ctx, i/4, 0x07ff0000);

207 INSTANCE_WR(ctx, 0x00494/4, 0x4b7fffff);

208 INSTANCE_WR(ctx, 0x004bc/4, 0x30201000);

209 INSTANCE_WR(ctx, 0x004c0/4, 0x70605040);

210 INSTANCE_WR(ctx, 0x004c4/4, 0xb8a89888);

211 INSTANCE_WR(ctx, 0x004c8/4, 0xf8e8d8c8);

212 INSTANCE_WR(ctx, 0x004dc/4, 0x40100000);

213 INSTANCE_WR(ctx, 0x004f8/4, 0x0000ffff);

214 INSTANCE_WR(ctx, 0x0052c/4, 0x435185d6);

215 INSTANCE_WR(ctx, 0x00530/4, 0x2155b699);

216 INSTANCE_WR(ctx, 0x00534/4, 0xfedcba98);

217 INSTANCE_WR(ctx, 0x00538/4, 0x00000098);

218 INSTANCE_WR(ctx, 0x00548/4, 0xffffffff);

219 INSTANCE_WR(ctx, 0x0054c/4, 0x00ff7000);

220 INSTANCE_WR(ctx, 0x00550/4, 0x0000ffff);

221 INSTANCE_WR(ctx, 0x00560/4, 0x00ff0000);

222 INSTANCE_WR(ctx, 0x00598/4, 0x00ffff00);

223 for (i=0x005dc; i<=0x00618; i+=4)

224 INSTANCE_WR(ctx, i/4, 0x00018488);

225 for (i=0x0061c; i<=0x00658; i+=4)

226 INSTANCE_WR(ctx, i/4, 0x00028202);

227 for (i=0x0069c; i<=0x006d8; i+=4)

228 INSTANCE_WR(ctx, i/4, 0x0000aae4);

229 for (i=0x006dc; i<=0x00718; i+=4)

230 INSTANCE_WR(ctx, i/4, 0x01012000);

231 for (i=0x0071c; i<=0x00758; i+=4)

232 INSTANCE_WR(ctx, i/4, 0x00080008);

233 for (i=0x0079c; i<=0x007d8; i+=4)

234 INSTANCE_WR(ctx, i/4, 0x00100008);

235 for (i=0x0082c; i<=0x00838; i+=4)

236 INSTANCE_WR(ctx, i/4, 0x0001bc80);

237 for (i=0x0083c; i<=0x00848; i+=4)

238 INSTANCE_WR(ctx, i/4, 0x00000202);

239 for (i=0x0085c; i<=0x00868; i+=4)

240 INSTANCE_WR(ctx, i/4, 0x00000008);

241 for (i=0x0087c; i<=0x00888; i+=4)

242 INSTANCE_WR(ctx, i/4, 0x00080008);

243 INSTANCE_WR(ctx, 0x0089c/4, 0x00000002);

244 INSTANCE_WR(ctx, 0x008d0/4, 0x00000021);

245 INSTANCE_WR(ctx, 0x008d4/4, 0x030c30c3);

246 INSTANCE_WR(ctx, 0x008e0/4, 0x3e020200);

247 INSTANCE_WR(ctx, 0x008e4/4, 0x00ffffff);

248 INSTANCE_WR(ctx, 0x008e8/4, 0x0c103f00);

249 INSTANCE_WR(ctx, 0x008f4/4, 0x00020000);

250 INSTANCE_WR(ctx, 0x0092c/4, 0x00008100);

251 INSTANCE_WR(ctx, 0x009b8/4, 0x00000001);

252 INSTANCE_WR(ctx, 0x009fc/4, 0x00001001);

253 INSTANCE_WR(ctx, 0x00a04/4, 0x00000003);

254 INSTANCE_WR(ctx, 0x00a08/4, 0x00888001);

255 INSTANCE_WR(ctx, 0x00a8c/4, 0x00000005);

256 INSTANCE_WR(ctx, 0x00a98/4, 0x0000ffff);

257 INSTANCE_WR(ctx, 0x00ab4/4, 0x00005555);

258 INSTANCE_WR(ctx, 0x00ab8/4, 0x00005555);

259 INSTANCE_WR(ctx, 0x00abc/4, 0x00005555);

260 INSTANCE_WR(ctx, 0x00ac0/4, 0x00000001);

261 INSTANCE_WR(ctx, 0x00af8/4, 0x00000001);

262 for (i=0x02ec0; i<=0x02f38; i+=8)

263 INSTANCE_WR(ctx, i/4, 0x3f800000);

264 for (i=0x04c80; i<=0x06e70; i+=24)

265 INSTANCE_WR(ctx, i/4, 0x00000001);

266 for (i=0x06e80; i<=0x07270; i+=16)

267 INSTANCE_WR(ctx, i/4, 0x3f800000);

268 for (i=0x096c0; i<=0x0b8b0; i+=24)

269 INSTANCE_WR(ctx, i/4, 0x00000001);

270 for (i=0x0b8c0; i<=0x0bcb0; i+=16)

271 INSTANCE_WR(ctx, i/4, 0x3f800000);

272 for (i=0x0e100; i<=0x102f0; i+=24)

273 INSTANCE_WR(ctx, i/4, 0x00000001);

274 for (i=0x10300; i<=0x106f0; i+=16)

275 INSTANCE_WR(ctx, i/4, 0x3f800000);

276 };

277

278 static void nv46_graph_context_init(drm_device_t *dev, struct mem_block *ctx)

279 {

280 drm_nouveau_private_t *dev_priv = dev->dev_private;

281 int i;

282

283 INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx));

284 INSTANCE_WR(ctx, 0x00040/4, 0x0000ffff);

285 INSTANCE_WR(ctx, 0x00044/4, 0x0000ffff);

286 INSTANCE_WR(ctx, 0x0004c/4, 0x00000001);

287 INSTANCE_WR(ctx, 0x00138/4, 0x20010001);

288 INSTANCE_WR(ctx, 0x0013c/4, 0x0f73ef00);

289 INSTANCE_WR(ctx, 0x00144/4, 0x02008821);

290 INSTANCE_WR(ctx, 0x00174/4, 0x00000001);

291 INSTANCE_WR(ctx, 0x00178/4, 0x00000001);

292 INSTANCE_WR(ctx, 0x0017c/4, 0x00000001);

293 INSTANCE_WR(ctx, 0x00180/4, 0x00000001);

294 INSTANCE_WR(ctx, 0x00184/4, 0x00000001);

295 INSTANCE_WR(ctx, 0x00188/4, 0x00000001);

296 INSTANCE_WR(ctx, 0x0018c/4, 0x00000001);

297 INSTANCE_WR(ctx, 0x00190/4, 0x00000001);

298 INSTANCE_WR(ctx, 0x00194/4, 0x00000040);

299 INSTANCE_WR(ctx, 0x00198/4, 0x00000040);

300 INSTANCE_WR(ctx, 0x0019c/4, 0x00000040);

301 INSTANCE_WR(ctx, 0x001a4/4, 0x00000040);

302 INSTANCE_WR(ctx, 0x001ec/4, 0x0b0b0b0c);

303 INSTANCE_WR(ctx, 0x0035c/4, 0x00040000);

304 INSTANCE_WR(ctx, 0x0036c/4, 0x55555555);

305 INSTANCE_WR(ctx, 0x00370/4, 0x55555555);

306 INSTANCE_WR(ctx, 0x00374/4, 0x55555555);

307 INSTANCE_WR(ctx, 0x00378/4, 0x55555555);

308 INSTANCE_WR(ctx, 0x003a4/4, 0x00000008);

309 INSTANCE_WR(ctx, 0x003b8/4, 0x00003010);

310 INSTANCE_WR(ctx, 0x003dc/4, 0x00000111);

311 INSTANCE_WR(ctx, 0x003e0/4, 0x00000111);

312 INSTANCE_WR(ctx, 0x003e4/4, 0x00000111);

313 INSTANCE_WR(ctx, 0x003e8/4, 0x00000111);

314 INSTANCE_WR(ctx, 0x003ec/4, 0x00000111);

315 INSTANCE_WR(ctx, 0x003f0/4, 0x00000111);

316 INSTANCE_WR(ctx, 0x003f4/4, 0x00000111);

317 INSTANCE_WR(ctx, 0x003f8/4, 0x00000111);

318 INSTANCE_WR(ctx, 0x003fc/4, 0x00000111);

319 INSTANCE_WR(ctx, 0x00400/4, 0x00000111);

320 INSTANCE_WR(ctx, 0x00404/4, 0x00000111);

321 INSTANCE_WR(ctx, 0x00408/4, 0x00000111);

322 INSTANCE_WR(ctx, 0x0040c/4, 0x00000111);

323 INSTANCE_WR(ctx, 0x00410/4, 0x00000111);

324 INSTANCE_WR(ctx, 0x00414/4, 0x00000111);

325 INSTANCE_WR(ctx, 0x00418/4, 0x00000111);

326 INSTANCE_WR(ctx, 0x004b0/4, 0x00000111);

327 INSTANCE_WR(ctx, 0x004b4/4, 0x00080060);

328 INSTANCE_WR(ctx, 0x004d0/4, 0x00000080);

329 INSTANCE_WR(ctx, 0x004d4/4, 0xffff0000);

330 INSTANCE_WR(ctx, 0x004d8/4, 0x00000001);

331 INSTANCE_WR(ctx, 0x004ec/4, 0x46400000);

332 INSTANCE_WR(ctx, 0x004fc/4, 0xffff0000);

333 INSTANCE_WR(ctx, 0x00500/4, 0x88888888);

334 INSTANCE_WR(ctx, 0x00504/4, 0x88888888);

335 INSTANCE_WR(ctx, 0x00508/4, 0x88888888);

336 INSTANCE_WR(ctx, 0x0050c/4, 0x88888888);

337 INSTANCE_WR(ctx, 0x00510/4, 0x88888888);

338 INSTANCE_WR(ctx, 0x00514/4, 0x88888888);

339 INSTANCE_WR(ctx, 0x00518/4, 0x88888888);

340 INSTANCE_WR(ctx, 0x0051c/4, 0x88888888);

341 INSTANCE_WR(ctx, 0x00520/4, 0x88888888);

342 INSTANCE_WR(ctx, 0x00524/4, 0x88888888);

343 INSTANCE_WR(ctx, 0x00528/4, 0x88888888);

344 INSTANCE_WR(ctx, 0x0052c/4, 0x88888888);

345 INSTANCE_WR(ctx, 0x00530/4, 0x88888888);

346 INSTANCE_WR(ctx, 0x00534/4, 0x88888888);

347 INSTANCE_WR(ctx, 0x00538/4, 0x88888888);

348 INSTANCE_WR(ctx, 0x0053c/4, 0x88888888);

349 INSTANCE_WR(ctx, 0x00550/4, 0x0fff0000);

350 INSTANCE_WR(ctx, 0x00554/4, 0x0fff0000);

351 INSTANCE_WR(ctx, 0x0055c/4, 0x00011100);

352 for (i=0x00578; i<0x005b4; i+=4)

353 INSTANCE_WR(ctx, i/4, 0x07ff0000);

354 INSTANCE_WR(ctx, 0x005c0/4, 0x4b7fffff);

355 INSTANCE_WR(ctx, 0x005e8/4, 0x30201000);

356 INSTANCE_WR(ctx, 0x005ec/4, 0x70605040);

357 INSTANCE_WR(ctx, 0x005f0/4, 0xb8a89888);

358 INSTANCE_WR(ctx, 0x005f4/4, 0xf8e8d8c8);

359 INSTANCE_WR(ctx, 0x00608/4, 0x40100000);

360 INSTANCE_WR(ctx, 0x00624/4, 0x0000ffff);

361 INSTANCE_WR(ctx, 0x00658/4, 0x435185d6);

362 INSTANCE_WR(ctx, 0x0065c/4, 0x2155b699);

363 INSTANCE_WR(ctx, 0x00660/4, 0xfedcba98);

364 INSTANCE_WR(ctx, 0x00664/4, 0x00000098);

365 INSTANCE_WR(ctx, 0x00674/4, 0xffffffff);

366 INSTANCE_WR(ctx, 0x00678/4, 0x00ff7000);

367 INSTANCE_WR(ctx, 0x0067c/4, 0x0000ffff);

368 INSTANCE_WR(ctx, 0x0068c/4, 0x00ff0000);

369 INSTANCE_WR(ctx, 0x006c8/4, 0x00ffff00);

370 for (i=0x0070c; i<=0x00748; i+=4)

371 INSTANCE_WR(ctx, i/4, 0x00018488);

372 for (i=0x0074c; i<=0x00788; i+=4)

373 INSTANCE_WR(ctx, i/4, 0x00028202);

374 for (i=0x007cc; i<=0x00808; i+=4)

375 INSTANCE_WR(ctx, i/4, 0x0000aae4);

376 for (i=0x0080c; i<=0x00848; i+=4)

377 INSTANCE_WR(ctx, i/4, 0x01012000);

378 for (i=0x0084c; i<=0x00888; i+=4)

379 INSTANCE_WR(ctx, i/4, 0x00080008);

380 for (i=0x008cc; i<=0x00908; i+=4)

381 INSTANCE_WR(ctx, i/4, 0x00100008);

382 for (i=0x0095c; i<=0x00968; i+=4)

383 INSTANCE_WR(ctx, i/4, 0x0001bc80);

384 for (i=0x0096c; i<=0x00978; i+=4)

385 INSTANCE_WR(ctx, i/4, 0x00000202);

386 for (i=0x0098c; i<=0x00998; i+=4)

387 INSTANCE_WR(ctx, i/4, 0x00000008);

388 for (i=0x009ac; i<=0x009b8; i+=4)

389 INSTANCE_WR(ctx, i/4, 0x00080008);

390 INSTANCE_WR(ctx, 0x009cc/4, 0x00000002);

391 INSTANCE_WR(ctx, 0x00a00/4, 0x00000421);

392 INSTANCE_WR(ctx, 0x00a04/4, 0x030c30c3);

393 INSTANCE_WR(ctx, 0x00a08/4, 0x00011001);

394 INSTANCE_WR(ctx, 0x00a14/4, 0x3e020200);

395 INSTANCE_WR(ctx, 0x00a18/4, 0x00ffffff);

396 INSTANCE_WR(ctx, 0x00a1c/4, 0x0c103f00);

397 INSTANCE_WR(ctx, 0x00a28/4, 0x00040000);

398 INSTANCE_WR(ctx, 0x00a60/4, 0x00008100);

399 INSTANCE_WR(ctx, 0x00aec/4, 0x00000001);

400 INSTANCE_WR(ctx, 0x00b30/4, 0x00001001);

401 INSTANCE_WR(ctx, 0x00b38/4, 0x00000003);

402 INSTANCE_WR(ctx, 0x00b3c/4, 0x00888001);

403 INSTANCE_WR(ctx, 0x00bc0/4, 0x00000005);

404 INSTANCE_WR(ctx, 0x00bcc/4, 0x0000ffff);

405 INSTANCE_WR(ctx, 0x00be8/4, 0x00005555);

406 INSTANCE_WR(ctx, 0x00bec/4, 0x00005555);

407 INSTANCE_WR(ctx, 0x00bf0/4, 0x00005555);

408 INSTANCE_WR(ctx, 0x00bf4/4, 0x00000001);

409 INSTANCE_WR(ctx, 0x00c2c/4, 0x00000001);

410 INSTANCE_WR(ctx, 0x00c30/4, 0x08e00001);

411 INSTANCE_WR(ctx, 0x00c34/4, 0x000e3000);

412 for (i=0x017f8; i<=0x01870; i+=8)

413 INSTANCE_WR(ctx, i/4, 0x3f800000);

414 for (i=0x035b8; i<=0x057a8; i+=24)

415 INSTANCE_WR(ctx, i/4, 0x00000001);

416 for (i=0x057b8; i<=0x05ba8; i+=16)

417 INSTANCE_WR(ctx, i/4, 0x3f800000);

418 for (i=0x07f38; i<=0x0a128; i+=24)

419 INSTANCE_WR(ctx, i/4, 0x00000001);

420 for (i=0x0a138; i<=0x0a528; i+=16)

421 INSTANCE_WR(ctx, i/4, 0x3f800000);

422 for (i=0x0c8b8; i<=0x0eaa8; i+=24)

423 INSTANCE_WR(ctx, i/4, 0x00000001);

424 for (i=0x0eab8; i<=0x0eea8; i+=16)

425 INSTANCE_WR(ctx, i/4, 0x3f800000);

426 }

427

428 static void nv4a_graph_context_init(drm_device_t *dev, struct mem_block *ctx)

429 {

430 drm_nouveau_private_t *dev_priv = dev->dev_private;

431 int i;

432

433 INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx));

434 INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);

435 INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);

436 INSTANCE_WR(ctx, 0x00030/4, 0x00000001);

437 INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);

438 INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);

439 INSTANCE_WR(ctx, 0x00128/4, 0x02008821);

440 INSTANCE_WR(ctx, 0x00158/4, 0x00000001);

441 INSTANCE_WR(ctx, 0x0015c/4, 0x00000001);

442 INSTANCE_WR(ctx, 0x00160/4, 0x00000001);

443 INSTANCE_WR(ctx, 0x00164/4, 0x00000001);

444 INSTANCE_WR(ctx, 0x00168/4, 0x00000001);

445 INSTANCE_WR(ctx, 0x0016c/4, 0x00000001);

446 INSTANCE_WR(ctx, 0x00170/4, 0x00000001);

447 INSTANCE_WR(ctx, 0x00174/4, 0x00000001);

448 INSTANCE_WR(ctx, 0x00178/4, 0x00000040);

449 INSTANCE_WR(ctx, 0x0017c/4, 0x00000040);

450 INSTANCE_WR(ctx, 0x00180/4, 0x00000040);

451 INSTANCE_WR(ctx, 0x00188/4, 0x00000040);

452 INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);

453 INSTANCE_WR(ctx, 0x00340/4, 0x00040000);

454 INSTANCE_WR(ctx, 0x00350/4, 0x55555555);

455 INSTANCE_WR(ctx, 0x00354/4, 0x55555555);

456 INSTANCE_WR(ctx, 0x00358/4, 0x55555555);

457 INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);

458 INSTANCE_WR(ctx, 0x00388/4, 0x00000008);

459 INSTANCE_WR(ctx, 0x0039c/4, 0x00003010);

460 INSTANCE_WR(ctx, 0x003cc/4, 0x00000111);

461 INSTANCE_WR(ctx, 0x003d0/4, 0x00080060);

462 INSTANCE_WR(ctx, 0x003ec/4, 0x00000080);

463 INSTANCE_WR(ctx, 0x003f0/4, 0xffff0000);

464 INSTANCE_WR(ctx, 0x003f4/4, 0x00000001);

465 INSTANCE_WR(ctx, 0x00408/4, 0x46400000);

466 INSTANCE_WR(ctx, 0x00418/4, 0xffff0000);

467 INSTANCE_WR(ctx, 0x00424/4, 0x0fff0000);

468 INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000);

469 INSTANCE_WR(ctx, 0x00430/4, 0x00011100);

470 for (i=0x0044c; i<=0x00488; i+=4)

471 INSTANCE_WR(ctx, i/4, 0x07ff0000);

472 INSTANCE_WR(ctx, 0x00494/4, 0x4b7fffff);

473 INSTANCE_WR(ctx, 0x004bc/4, 0x30201000);

474 INSTANCE_WR(ctx, 0x004c0/4, 0x70605040);

475 INSTANCE_WR(ctx, 0x004c4/4, 0xb8a89888);

476 INSTANCE_WR(ctx, 0x004c8/4, 0xf8e8d8c8);

477 INSTANCE_WR(ctx, 0x004dc/4, 0x40100000);

478 INSTANCE_WR(ctx, 0x004f8/4, 0x0000ffff);

479 INSTANCE_WR(ctx, 0x0052c/4, 0x435185d6);

480 INSTANCE_WR(ctx, 0x00530/4, 0x2155b699);

481 INSTANCE_WR(ctx, 0x00534/4, 0xfedcba98);

482 INSTANCE_WR(ctx, 0x00538/4, 0x00000098);

483 INSTANCE_WR(ctx, 0x00548/4, 0xffffffff);

484 INSTANCE_WR(ctx, 0x0054c/4, 0x00ff7000);

485 INSTANCE_WR(ctx, 0x00550/4, 0x0000ffff);

486 INSTANCE_WR(ctx, 0x0055c/4, 0x00ff0000);

487 INSTANCE_WR(ctx, 0x00594/4, 0x00ffff00);

488 for (i=0x005d8; i<=0x00614; i+=4)

489 INSTANCE_WR(ctx, i/4, 0x00018488);

490 for (i=0x00618; i<=0x00654; i+=4)

491 INSTANCE_WR(ctx, i/4, 0x00028202);

492 for (i=0x00698; i<=0x006d4; i+=4)

493 INSTANCE_WR(ctx, i/4, 0x0000aae4);

494 for (i=0x006d8; i<=0x00714; i+=4)

495 INSTANCE_WR(ctx, i/4, 0x01012000);

496 for (i=0x00718; i<=0x00754; i+=4)

497 INSTANCE_WR(ctx, i/4, 0x00080008);

498 for (i=0x00798; i<=0x007d4; i+=4)

499 INSTANCE_WR(ctx, i/4, 0x00100008);

500 for (i=0x00828; i<=0x00834; i+=4)

501 INSTANCE_WR(ctx, i/4, 0x0001bc80);

502 for (i=0x00838; i<=0x00844; i+=4)

503 INSTANCE_WR(ctx, i/4, 0x00000202);

504 for (i=0x00858; i<=0x00864; i+=4)

505 INSTANCE_WR(ctx, i/4, 0x00000008);

506 for (i=0x00878; i<=0x00884; i+=4)

507 INSTANCE_WR(ctx, i/4, 0x00080008);

508 INSTANCE_WR(ctx, 0x00898/4, 0x00000002);

509 INSTANCE_WR(ctx, 0x008cc/4, 0x00000021);

510 INSTANCE_WR(ctx, 0x008d0/4, 0x030c30c3);

511 INSTANCE_WR(ctx, 0x008d4/4, 0x00011001);

512 INSTANCE_WR(ctx, 0x008e0/4, 0x3e020200);

513 INSTANCE_WR(ctx, 0x008e4/4, 0x00ffffff);

514 INSTANCE_WR(ctx, 0x008e8/4, 0x0c103f00);

515 INSTANCE_WR(ctx, 0x008f4/4, 0x00040000);

516 INSTANCE_WR(ctx, 0x0092c/4, 0x00008100);

517 INSTANCE_WR(ctx, 0x009b8/4, 0x00000001);

518 INSTANCE_WR(ctx, 0x009fc/4, 0x00001001);

519 INSTANCE_WR(ctx, 0x00a04/4, 0x00000003);

520 INSTANCE_WR(ctx, 0x00a08/4, 0x00888001);

521 INSTANCE_WR(ctx, 0x00a8c/4, 0x00000005);

522 INSTANCE_WR(ctx, 0x00a98/4, 0x0000ffff);

523 INSTANCE_WR(ctx, 0x00ab4/4, 0x00005555);

524 INSTANCE_WR(ctx, 0x00ab8/4, 0x00005555);

525 INSTANCE_WR(ctx, 0x00abc/4, 0x00005555);

526 INSTANCE_WR(ctx, 0x00ac0/4, 0x00000001);

527 INSTANCE_WR(ctx, 0x00af8/4, 0x00000001);

528 for (i=0x016c0; i<=0x01738; i+=8)

529 INSTANCE_WR(ctx, i/4, 0x3f800000);

530 for (i=0x03840; i<=0x05670; i+=24)

531 INSTANCE_WR(ctx, i/4, 0x00000001);

532 for (i=0x05680; i<=0x05a70; i+=16)

533 INSTANCE_WR(ctx, i/4, 0x3f800000);

534 for (i=0x07e00; i<=0x09ff0; i+=24)

535 INSTANCE_WR(ctx, i/4, 0x00000001);

536 for (i=0x0a000; i<=0x0a3f0; i+=16)

537 INSTANCE_WR(ctx, i/4, 0x3f800000);

538 for (i=0x0c780; i<=0x0e970; i+=24)

539 INSTANCE_WR(ctx, i/4, 0x00000001);

540 for (i=0x0e980; i<=0x0ed70; i+=16)

541 INSTANCE_WR(ctx, i/4, 0x3f800000);

542 }

543

544

545 static void nv4c_graph_context_init(drm_device_t *dev, struct mem_block *ctx)

546 {

547 drm_nouveau_private_t *dev_priv = dev->dev_private;

548 int i;

549

550 INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx));

551 INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);

552 INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);

553 INSTANCE_WR(ctx, 0x00030/4, 0x00000001);

554 INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);

555 INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);

556 INSTANCE_WR(ctx, 0x00128/4, 0x02008821);

557 INSTANCE_WR(ctx, 0x00158/4, 0x00000001);

558 INSTANCE_WR(ctx, 0x0015c/4, 0x00000001);

559 INSTANCE_WR(ctx, 0x00160/4, 0x00000001);

560 INSTANCE_WR(ctx, 0x00164/4, 0x00000001);

561 INSTANCE_WR(ctx, 0x00168/4, 0x00000001);

562 INSTANCE_WR(ctx, 0x0016c/4, 0x00000001);

563 INSTANCE_WR(ctx, 0x00170/4, 0x00000001);

564 INSTANCE_WR(ctx, 0x00174/4, 0x00000001);

565 INSTANCE_WR(ctx, 0x00178/4, 0x00000040);

566 INSTANCE_WR(ctx, 0x0017c/4, 0x00000040);

567 INSTANCE_WR(ctx, 0x00180/4, 0x00000040);

568 INSTANCE_WR(ctx, 0x00188/4, 0x00000040);

569 INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);

570 INSTANCE_WR(ctx, 0x00340/4, 0x00040000);

571 INSTANCE_WR(ctx, 0x00350/4, 0x55555555);

572 INSTANCE_WR(ctx, 0x00354/4, 0x55555555);

573 INSTANCE_WR(ctx, 0x00358/4, 0x55555555);

574 INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);

575 INSTANCE_WR(ctx, 0x00388/4, 0x00000008);

576 INSTANCE_WR(ctx, 0x0039c/4, 0x00001010);

577 INSTANCE_WR(ctx, 0x003d0/4, 0x00000111);

578 INSTANCE_WR(ctx, 0x003d4/4, 0x00080060);

579 INSTANCE_WR(ctx, 0x003f0/4, 0x00000080);

580 INSTANCE_WR(ctx, 0x003f4/4, 0xffff0000);

581 INSTANCE_WR(ctx, 0x003f8/4, 0x00000001);

582 INSTANCE_WR(ctx, 0x0040c/4, 0x46400000);

583 INSTANCE_WR(ctx, 0x0041c/4, 0xffff0000);

584 INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000);

585 INSTANCE_WR(ctx, 0x0042c/4, 0x0fff0000);

586 INSTANCE_WR(ctx, 0x00434/4, 0x00011100);

587 for (i=0x00450; i<0x0048c; i+=4)

588 INSTANCE_WR(ctx, i/4, 0x07ff0000);

589 INSTANCE_WR(ctx, 0x00498/4, 0x4b7fffff);

590 INSTANCE_WR(ctx, 0x004c0/4, 0x30201000);

591 INSTANCE_WR(ctx, 0x004c4/4, 0x70605040);

592 INSTANCE_WR(ctx, 0x004c8/4, 0xb8a89888);

593 INSTANCE_WR(ctx, 0x004cc/4, 0xf8e8d8c8);

594 INSTANCE_WR(ctx, 0x004e0/4, 0x40100000);

595 INSTANCE_WR(ctx, 0x004fc/4, 0x0000ffff);

596 INSTANCE_WR(ctx, 0x00530/4, 0x435185d6);

597 INSTANCE_WR(ctx, 0x00534/4, 0x2155b699);

598 INSTANCE_WR(ctx, 0x00538/4, 0xfedcba98);

599 INSTANCE_WR(ctx, 0x0053c/4, 0x00000098);

600 INSTANCE_WR(ctx, 0x0054c/4, 0xffffffff);

601 INSTANCE_WR(ctx, 0x00550/4, 0x00ff7000);

602 INSTANCE_WR(ctx, 0x00554/4, 0x0000ffff);

603 INSTANCE_WR(ctx, 0x00564/4, 0x00ff0000);

604 INSTANCE_WR(ctx, 0x0059c/4, 0x00ffff00);

605 for (i=0x005e0; i<=0x0061c; i+=4)

606 INSTANCE_WR(ctx, i/4, 0x00018488);

607 for (i=0x00620; i<=0x0065c; i+=4)

608 INSTANCE_WR(ctx, i/4, 0x00028202);

609 for (i=0x006a0; i<=0x006dc; i+=4)

610 INSTANCE_WR(ctx, i/4, 0x0000aae4);

611 for (i=0x006e0; i<=0x0071c; i+=4)

612 INSTANCE_WR(ctx, i/4, 0x01012000);

613 for (i=0x00720; i<=0x0075c; i+=4)

614 INSTANCE_WR(ctx, i/4, 0x00080008);

615 for (i=0x007a0; i<=0x007dc; i+=4)

616 INSTANCE_WR(ctx, i/4, 0x00100008);

617 for (i=0x00830; i<=0x0083c; i+=4)

618 INSTANCE_WR(ctx, i/4, 0x0001bc80);

619 for (i=0x00840; i<=0x0084c; i+=4)

620 INSTANCE_WR(ctx, i/4, 0x00000202);

621 for (i=0x00860; i<=0x0086c; i+=4)

622 INSTANCE_WR(ctx, i/4, 0x00000008);

623 for (i=0x00880; i<=0x0088c; i+=4)

624 INSTANCE_WR(ctx, i/4, 0x00080008);

625 INSTANCE_WR(ctx, 0x008a0/4, 0x00000002);

626 INSTANCE_WR(ctx, 0x008d4/4, 0x00000020);

627 INSTANCE_WR(ctx, 0x008d8/4, 0x030c30c3);

628 INSTANCE_WR(ctx, 0x008dc/4, 0x00011001);

629 INSTANCE_WR(ctx, 0x008e8/4, 0x3e020200);

630 INSTANCE_WR(ctx, 0x008ec/4, 0x00ffffff);

631 INSTANCE_WR(ctx, 0x008f0/4, 0x0c103f00);

632 INSTANCE_WR(ctx, 0x008fc/4, 0x00040000);

633 INSTANCE_WR(ctx, 0x00934/4, 0x00008100);

634 INSTANCE_WR(ctx, 0x009c0/4, 0x00000001);

635 INSTANCE_WR(ctx, 0x00a04/4, 0x00001001);

636 INSTANCE_WR(ctx, 0x00a0c/4, 0x00000003);

637 INSTANCE_WR(ctx, 0x00a10/4, 0x00888001);

638 INSTANCE_WR(ctx, 0x00a74/4, 0x00000005);

639 INSTANCE_WR(ctx, 0x00a80/4, 0x0000ffff);

640 INSTANCE_WR(ctx, 0x00a9c/4, 0x00005555);

641 INSTANCE_WR(ctx, 0x00aa0/4, 0x00000001);

642 INSTANCE_WR(ctx, 0x00ad8/4, 0x00000001);

643 for (i=0x016a0; i<0x01718; i+=8)

644 INSTANCE_WR(ctx, i/4, 0x3f800000);

645 for (i=0x03460; i<0x05650; i+=24)

646 INSTANCE_WR(ctx, i/4, 0x00000001);

647 for (i=0x05660; i<0x05a50; i+=16)

648 INSTANCE_WR(ctx, i/4, 0x3f800000);

649 }

650

651 static void nv4e_graph_context_init(drm_device_t *dev, struct mem_block *ctx)

652 {

653 drm_nouveau_private_t *dev_priv = dev->dev_private;

654 int i;

655

656 INSTANCE_WR(ctx, 0x00000/4, nouveau_chip_instance_get(dev, ctx));

657 INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);

658 INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);

659 INSTANCE_WR(ctx, 0x00030/4, 0x00000001);

660 INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);

661 INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);

662 INSTANCE_WR(ctx, 0x00128/4, 0x02008821);

663 INSTANCE_WR(ctx, 0x00158/4, 0x00000001);

664 INSTANCE_WR(ctx, 0x0015c/4, 0x00000001);

665 INSTANCE_WR(ctx, 0x00160/4, 0x00000001);

666 INSTANCE_WR(ctx, 0x00164/4, 0x00000001);

667 INSTANCE_WR(ctx, 0x00168/4, 0x00000001);

668 INSTANCE_WR(ctx, 0x0016c/4, 0x00000001);

669 INSTANCE_WR(ctx, 0x00170/4, 0x00000001);

670 INSTANCE_WR(ctx, 0x00174/4, 0x00000001);

671 INSTANCE_WR(ctx, 0x00178/4, 0x00000040);

672 INSTANCE_WR(ctx, 0x0017c/4, 0x00000040);

673 INSTANCE_WR(ctx, 0x00180/4, 0x00000040);

674 INSTANCE_WR(ctx, 0x00188/4, 0x00000040);

675 INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);

676 INSTANCE_WR(ctx, 0x00340/4, 0x00040000);

677 INSTANCE_WR(ctx, 0x00350/4, 0x55555555);

678 INSTANCE_WR(ctx, 0x00354/4, 0x55555555);

679 INSTANCE_WR(ctx, 0x00358/4, 0x55555555);

680 INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);

681 INSTANCE_WR(ctx, 0x00388/4, 0x00000008);

682 INSTANCE_WR(ctx, 0x0039c/4, 0x00001010);

683 INSTANCE_WR(ctx, 0x003cc/4, 0x00000111);

684 INSTANCE_WR(ctx, 0x003d0/4, 0x00080060);

685 INSTANCE_WR(ctx, 0x003ec/4, 0x00000080);

686 INSTANCE_WR(ctx, 0x003f0/4, 0xffff0000);

687 INSTANCE_WR(ctx, 0x003f4/4, 0x00000001);

688 INSTANCE_WR(ctx, 0x00408/4, 0x46400000);

689 INSTANCE_WR(ctx, 0x00418/4, 0xffff0000);

690 INSTANCE_WR(ctx, 0x00424/4, 0x0fff0000);

691 INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000);

692 INSTANCE_WR(ctx, 0x00430/4, 0x00011100);

693 for (i=0x0044c; i<=0x00488; i+=4)

694 INSTANCE_WR(ctx, i/4, 0x07ff0000);

695 INSTANCE_WR(ctx, 0x00494/4, 0x4b7fffff);

696 INSTANCE_WR(ctx, 0x004bc/4, 0x30201000);

697 INSTANCE_WR(ctx, 0x004c0/4, 0x70605040);

698 INSTANCE_WR(ctx, 0x004c4/4, 0xb8a89888);

699 INSTANCE_WR(ctx, 0x004c8/4, 0xf8e8d8c8);

700 INSTANCE_WR(ctx, 0x004dc/4, 0x40100000);

701 INSTANCE_WR(ctx, 0x004f8/4, 0x0000ffff);

702 INSTANCE_WR(ctx, 0x0052c/4, 0x435185d6);

703 INSTANCE_WR(ctx, 0x00530/4, 0x2155b699);

704 INSTANCE_WR(ctx, 0x00534/4, 0xfedcba98);

705 INSTANCE_WR(ctx, 0x00538/4, 0x00000098);

706 INSTANCE_WR(ctx, 0x00548/4, 0xffffffff);

707 INSTANCE_WR(ctx, 0x0054c/4, 0x00ff7000);

708 INSTANCE_WR(ctx, 0x00550/4, 0x0000ffff);

709 INSTANCE_WR(ctx, 0x0055c/4, 0x00ff0000);

710 INSTANCE_WR(ctx, 0x00594/4, 0x00ffff00);

711 for (i=0x005d8; i<=0x00614; i+=4)

712 INSTANCE_WR(ctx, i/4, 0x00018488);

713 for (i=0x00618; i<=0x00654; i+=4)

714 INSTANCE_WR(ctx, i/4, 0x00028202);

715 for (i=0x00698; i<=0x006d4; i+=4)

716 INSTANCE_WR(ctx, i/4, 0x0000aae4);

717 for (i=0x006d8; i<=0x00714; i+=4)

718 INSTANCE_WR(ctx, i/4, 0x01012000);

719 for (i=0x00718; i<=0x00754; i+=4)

720 INSTANCE_WR(ctx, i/4, 0x00080008);

721 for (i=0x00798; i<=0x007d4; i+=4)

722 INSTANCE_WR(ctx, i/4, 0x00100008);

723 for (i=0x00828; i<=0x00834; i+=4)

724 INSTANCE_WR(ctx, i/4, 0x0001bc80);

725 for (i=0x00838; i<=0x00844; i+=4)

726 INSTANCE_WR(ctx, i/4, 0x00000202);

727 for (i=0x00858; i<=0x00864; i+=4)

728 INSTANCE_WR(ctx, i/4, 0x00000008);

729 for (i=0x00878; i<=0x00884; i+=4)

730 INSTANCE_WR(ctx, i/4, 0x00080008);

731 INSTANCE_WR(ctx, 0x00898/4, 0x00000002);

732 INSTANCE_WR(ctx, 0x008cc/4, 0x00000020);

733 INSTANCE_WR(ctx, 0x008d0/4, 0x030c30c3);

734 INSTANCE_WR(ctx, 0x008d4/4, 0x00011001);

735 INSTANCE_WR(ctx, 0x008e0/4, 0x3e020200);

736 INSTANCE_WR(ctx, 0x008e4/4, 0x00ffffff);

737 INSTANCE_WR(ctx, 0x008e8/4, 0x0c103f00);

738 INSTANCE_WR(ctx, 0x008f4/4, 0x00040000);

739 INSTANCE_WR(ctx, 0x0092c/4, 0x00008100);

740 INSTANCE_WR(ctx, 0x009b8/4, 0x00000001);

741 INSTANCE_WR(ctx, 0x009fc/4, 0x00001001);

742 INSTANCE_WR(ctx, 0x00a04/4, 0x00000003);

743 INSTANCE_WR(ctx, 0x00a08/4, 0x00888001);

744 INSTANCE_WR(ctx, 0x00a6c/4, 0x00000005);

745 INSTANCE_WR(ctx, 0x00a78/4, 0x0000ffff);

746 INSTANCE_WR(ctx, 0x00a94/4, 0x00005555);

747 INSTANCE_WR(ctx, 0x00a98/4, 0x00000001);

748 INSTANCE_WR(ctx, 0x00aa4/4, 0x00000001);

749 for (i=0x01668; i<=0x016e0; i+=8)

750 INSTANCE_WR(ctx, i/4, 0x3f800000);

751 for (i=0x03428; i<=0x05618; i+=24)

752 INSTANCE_WR(ctx, i/4, 0x00000001);

753 for (i=0x05628; i<=0x05a18; i+=16)

754 INSTANCE_WR(ctx, i/4, 0x3f800000);

755 }

756

757 int

758 nv40_graph_context_create(drm_device_t *dev, int channel)

759 {

760 drm_nouveau_private_t *dev_priv =

761 (drm_nouveau_private_t *)dev->dev_private;

762 struct nouveau_fifo *chan = &dev_priv->fifos[channel];

763 void (*ctx_init)(drm_device_t *, struct mem_block *);

764 unsigned int ctx_size;

765 int i;

766

767 switch (dev_priv->chipset) {

768 case 0x40:

769 ctx_size = NV40_GRCTX_SIZE;

770 ctx_init = nv40_graph_context_init;

771 break;

772 case 0x43:

773 ctx_size = NV43_GRCTX_SIZE;

774 ctx_init = nv43_graph_context_init;

775 break;

776 case 0x46:

777 ctx_size = NV46_GRCTX_SIZE;

778 ctx_init = nv46_graph_context_init;

779 break;

780 case 0x4a:

781 ctx_size = NV4A_GRCTX_SIZE;

782 ctx_init = nv4a_graph_context_init;

783 break;

784 case 0x4c:

785 ctx_size = NV4C_GRCTX_SIZE;

786 ctx_init = nv4c_graph_context_init;

787 break;

788 case 0x4e:

789 ctx_size = NV4E_GRCTX_SIZE;

790 ctx_init = nv4e_graph_context_init;

791 break;

792 default:

793 ctx_size = NV40_GRCTX_SIZE;

794 ctx_init = nv40_graph_context_init;

795 break;

796 }

797

798 /* Alloc and clear RAMIN to store the context */

799 chan->ramin_grctx = nouveau_instmem_alloc(dev, ctx_size, 4);

800 if (!chan->ramin_grctx)

801 return DRM_ERR(ENOMEM);

802 for (i=0; i<ctx_size; i+=4)

803 INSTANCE_WR(chan->ramin_grctx, i/4, 0x00000000);

804

805 /* Initialise default context values */

806 ctx_init(dev, chan->ramin_grctx);

807

808 return 0;

809 }

810

811 /* Save current context (from PGRAPH) into the channel's context

812 *XXX: fails sometimes, not sure why..

813 */

814 void

815 nv40_graph_context_save_current(drm_device_t *dev)

816 {

817 drm_nouveau_private_t *dev_priv =

818 (drm_nouveau_private_t *)dev->dev_private;

819 uint32_t instance;

820 int i;

821

822 NV_WRITE(NV04_PGRAPH_FIFO, 0);

823

824 instance = NV_READ(0x40032C) & 0xFFFFF;

825 if (!instance) {

826 NV_WRITE(NV04_PGRAPH_FIFO, 1);

827 return;

828 }

829

830 NV_WRITE(0x400784, instance);

831 NV_WRITE(0x400310, NV_READ(0x400310) | 0x20);

832 NV_WRITE(0x400304, 1);

833 /* just in case, we don't want to spin in-kernel forever */

834 for (i=0; i<1000; i++) {

835 if (NV_READ(0x40030C) == 0)

836 break;

837 }

838 if (i==1000) {

839 DRM_ERROR("failed to save current grctx to ramin\n");

840 DRM_ERROR("instance = 0x%08x\n", NV_READ(0x40032C));

841 DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));

842 NV_WRITE(NV04_PGRAPH_FIFO, 1);

843 return;

844 }

845

846 NV_WRITE(NV04_PGRAPH_FIFO, 1);

847 }

848

849 /* Restore the context for a specific channel into PGRAPH

850 * XXX: fails sometimes.. not sure why

851 */

852 void

853 nv40_graph_context_restore(drm_device_t *dev, int channel)

854 {

855 drm_nouveau_private_t *dev_priv =

856 (drm_nouveau_private_t *)dev->dev_private;

857 struct nouveau_fifo *chan = &dev_priv->fifos[channel];

858 uint32_t instance;

859 int i;

860

861 instance = nouveau_chip_instance_get(dev, chan->ramin_grctx);

862

863 NV_WRITE(NV04_PGRAPH_FIFO, 0);

864 NV_WRITE(0x400784, instance);

865 NV_WRITE(0x400310, NV_READ(0x400310) | 0x40);

866 NV_WRITE(0x400304, 1);

867 /* just in case, we don't want to spin in-kernel forever */

868 for (i=0; i<1000; i++) {

869 if (NV_READ(0x40030C) == 0)

870 break;

871 }

872 if (i==1000) {

873 DRM_ERROR("failed to restore grctx for ch%d to PGRAPH\n",

874 channel);

875 DRM_ERROR("instance = 0x%08x\n", instance);

876 DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030C));

877 NV_WRITE(NV04_PGRAPH_FIFO, 1);

878 return;

879 }

880

881

882 /* 0x40032C, no idea of it's exact function. Could simply be a

883 * record of the currently active PGRAPH context. It's currently

884 * unknown as to what bit 24 does. The nv ddx has it set, so we will

885 * set it here too.

886 */

887 NV_WRITE(0x40032C, instance | 0x01000000);

888 /* 0x32E0 records the instance address of the active FIFO's PGRAPH

889 * context. If at any time this doesn't match 0x40032C, you will

890 * recieve PGRAPH_INTR_CONTEXT_SWITCH

891 */

892 NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, instance);

893 NV_WRITE(NV04_PGRAPH_FIFO, 1);

894 }

895

896 /* Some voodoo that makes context switching work without the binary driver

897 * initialising the card first.

898 *

899 * It is possible to effect how the context is saved from PGRAPH into a block

900 * of instance memory by altering the values in these tables. This may mean

901 * that the context layout of each chipset is slightly different (at least

902 * NV40 and C51 are different). It would also be possible for chipsets to

903 * have an identical context layout, but pull the data from different PGRAPH

904 * registers.

905 *

906 * TODO: decode the meaning of the magic values, may provide clues about the

907 * differences between the various NV40 chipsets.

908 * TODO: one we have a better idea of how each chipset differs, perhaps think

909 * about unifying these instead of providing a separate table for each

910 * chip.

911 *

912 * mmio-trace dumps from other nv4x/g7x/c5x cards very welcome :)

913 */

914 static uint32_t nv40_ctx_voodoo[] = {

915 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,

916 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409406,

917 0x0040a268, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,

918 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,

919 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,

920 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,

921 0x001041c9, 0x0010c1dc, 0x00110205, 0x0011420a, 0x00114210, 0x00110216,

922 0x0012421b, 0x00120270, 0x001242c0, 0x00200040, 0x00100280, 0x00128100,

923 0x00128120, 0x00128143, 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029,

924 0x00110400, 0x00104d10, 0x00500060, 0x00403b87, 0x0060000d, 0x004076e6,

925 0x002000f0, 0x0060000a, 0x00200045, 0x00100620, 0x00108668, 0x0011466b,

926 0x00120682, 0x0011068b, 0x00168691, 0x0010c6ae, 0x001206b4, 0x0020002a,

927 0x001006c4, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, 0x001043e1,

928 0x00500060, 0x00405600, 0x00405684, 0x00600003, 0x00500067, 0x00600008,

929 0x00500060, 0x00700082, 0x0020026c, 0x0060000a, 0x00104800, 0x00104901,

930 0x00120920, 0x00200035, 0x00100940, 0x00148a00, 0x00104a14, 0x00200038,

931 0x00100b00, 0x00138d00, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06,

932 0x0020031a, 0x0060000a, 0x00300000, 0x00200680, 0x00406c00, 0x00200684,

933 0x00800001, 0x00200b62, 0x0060000a, 0x0020a0b0, 0x0040728a, 0x00201b68,

934 0x00800041, 0x00407684, 0x00203e60, 0x00800002, 0x00408700, 0x00600006,

935 0x00700003, 0x004080e6, 0x00700080, 0x0020031a, 0x0060000a, 0x00200004,

936 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a284,

937 0x00700002, 0x00600004, 0x0040a268, 0x00700000, 0x00200000, 0x0060000a,

938 0x00106002, 0x00700080, 0x00400a84, 0x00700002, 0x00400a68, 0x00500060,

939 0x00600007, 0x00409388, 0x0060000f, 0x00000000, 0x00500060, 0x00200000,

940 0x0060000a, 0x00700000, 0x00106001, 0x00700083, 0x00910880, 0x00901ffe,

941 0x00940400, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68,

942 0x0040a406, 0x0040a505, 0x00600009, 0x00700005, 0x00700006, 0x0060000e,

943 ~0

944 };

945

946 static uint32_t nv43_ctx_voodoo[] = {

947 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,

948 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06,

949 0x0040a868, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,

950 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,

951 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,

952 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,

953 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,

954 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,

955 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,

956 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407ce6, 0x002000f1,

957 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,

958 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,

959 0x00200020, 0x001006cc, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,

960 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003,

961 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200233, 0x0060000a,

962 0x00104800, 0x00108901, 0x00124920, 0x0020001f, 0x00100940, 0x00140965,

963 0x00148a00, 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04,

964 0x0010cd08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06,

965 0x002002c8, 0x0060000a, 0x00300000, 0x00200680, 0x00407200, 0x00200684,

966 0x00800001, 0x00200b10, 0x0060000a, 0x00203870, 0x0040788a, 0x00201350,

967 0x00800041, 0x00407c84, 0x00201560, 0x00800002, 0x00408d00, 0x00600006,

968 0x00700003, 0x004086e6, 0x00700080, 0x002002c8, 0x0060000a, 0x00200004,

969 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a884,

970 0x00700002, 0x00600004, 0x0040a868, 0x00700000, 0x00200000, 0x0060000a,

971 0x00106002, 0x00700080, 0x00400a84, 0x00700002, 0x00400a68, 0x00500060,

972 0x00600007, 0x00409988, 0x0060000f, 0x00000000, 0x00500060, 0x00200000,

973 0x0060000a, 0x00700000, 0x00106001, 0x00700083, 0x00910880, 0x00901ffe,

974 0x00940400, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68,

975 0x0040aa06, 0x0040ab05, 0x00600009, 0x00700005, 0x00700006, 0x0060000e,

976 ~0

977 };

978

979 static uint32_t nv46_ctx_voodoo[] = {

980 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,

981 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306,

982 0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,

983 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968,

984 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,

985 0x004020e6, 0x007000a0, 0x00500060, 0x00200008, 0x0060000a, 0x0011814d,

986 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,

987 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,

988 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,

989 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,

990 0x00500060, 0x00403f87, 0x0060000d, 0x004079e6, 0x002000f7, 0x0060000a,

991 0x00200045, 0x00100620, 0x00104668, 0x0017466d, 0x0011068b, 0x00168691,

992 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, 0x00200022,

993 0x001006cc, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, 0x001043e1,

994 0x00500060, 0x0020027f, 0x0060000a, 0x00104800, 0x00108901, 0x00104910,

995 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00, 0x00108a14,

996 0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, 0x0010cd08, 0x00104d80,

997 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, 0x00105406, 0x00105709,

998 0x00200316, 0x0060000a, 0x00300000, 0x00200080, 0x00407200, 0x00200084,

999 0x00800001, 0x0020055e, 0x0060000a, 0x002037e0, 0x0040788a, 0x00201320,

1000 0x00800029, 0x00408900, 0x00600006, 0x004085e6, 0x00700080, 0x00200081,

1001 0x0060000a, 0x00104280, 0x00200316, 0x0060000a, 0x00200004, 0x00800001,

1002 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a068, 0x00700000,

1003 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060,

1004 0x00600007, 0x00409388, 0x0060000f, 0x00500060, 0x00200000, 0x0060000a,

1005 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020,

1006 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a206, 0x0040a305,

1007 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0

1008 };

1009

1010 static uint32_t nv4a_ctx_voodoo[] = {

1011 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,

1012 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06,

1013 0x0040ac68, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,

1014 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,

1015 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,

1016 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,

1017 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,

1018 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,

1019 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,

1020 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407de6, 0x002000f1,

1021 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,

1022 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,

1023 0x001646cc, 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,

1024 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003,

1025 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200232, 0x0060000a,

1026 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940,

1027 0x00140965, 0x00148a00, 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00,

1028 0x0010cd04, 0x0010cd08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00,

1029 0x00104f06, 0x002002c8, 0x0060000a, 0x00300000, 0x00200080, 0x00407300,

1030 0x00200084, 0x00800001, 0x00200510, 0x0060000a, 0x002037e0, 0x0040798a,

1031 0x00201320, 0x00800029, 0x00407d84, 0x00201560, 0x00800002, 0x00409100,

1032 0x00600006, 0x00700003, 0x00408ae6, 0x00700080, 0x0020007a, 0x0060000a,

1033 0x00104280, 0x002002c8, 0x0060000a, 0x00200004, 0x00800001, 0x00700000,

1034 0x00200000, 0x0060000a, 0x00106002, 0x0040ac84, 0x00700002, 0x00600004,

1035 0x0040ac68, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x00700080,

1036 0x00400a84, 0x00700002, 0x00400a68, 0x00500060, 0x00600007, 0x00409d88,

1037 0x0060000f, 0x00000000, 0x00500060, 0x00200000, 0x0060000a, 0x00700000,

1038 0x00106001, 0x00700083, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020,

1039 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68, 0x0040ae06, 0x0040af05,

1040 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0

1041 };

1042

1043 static uint32_t nv4e_ctx_voodoo[] = {

1044 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,

1045 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06,

1046 0x0040a868, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,

1047 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,

1048 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,

1049 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,

1050 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,

1051 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,

1052 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,

1053 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407ce6, 0x002000f1,

1054 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,

1055 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,

1056 0x001646cc, 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,

1057 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003,

1058 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200232, 0x0060000a,

1059 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940,

1060 0x00140965, 0x00148a00, 0x00108a14, 0x00140b00, 0x00134b2c, 0x0010cd00,

1061 0x0010cd04, 0x00104d08, 0x00104d80, 0x00104e00, 0x00105c00, 0x00104f06,

1062 0x002002b2, 0x0060000a, 0x00300000, 0x00200080, 0x00407200, 0x00200084,

1063 0x00800001, 0x002004fa, 0x0060000a, 0x00201320, 0x0040788a, 0xfffffb06,

1064 0x00800029, 0x00407c84, 0x00200b20, 0x00800002, 0x00408d00, 0x00600006,

1065 0x00700003, 0x004086e6, 0x00700080, 0x002002b2, 0x0060000a, 0x00200004,

1066 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a884,

1067 0x00700002, 0x00600004, 0x0040a868, 0x00700000, 0x00200000, 0x0060000a,

1068 0x00106002, 0x00700080, 0x00400a84, 0x00700002, 0x00400a68, 0x00500060,

1069 0x00600007, 0x00409988, 0x0060000f, 0x00000000, 0x00500060, 0x00200000,

1070 0x0060000a, 0x00700000, 0x00106001, 0x00700083, 0x00910880, 0x00901ffe,

1071 0x01940000, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68,

1072 0x0040aa06, 0x0040ab05, 0x00600009, 0x00700005, 0x00700006, 0x0060000e,

1073 ~0

1074 };

1075

1076 /*

1077 * G70 0x47

1078 * G71 0x49

1079 * NV45 0x48

1080 * G72[M] 0x46

1081 * G73 0x4b

1082 * C51_G7X 0x4c

1083 * C51 0x4e

1084 */

1085 int

1086 nv40_graph_init(drm_device_t *dev)

1087 {

1088 drm_nouveau_private_t *dev_priv =

1089 (drm_nouveau_private_t *)dev->dev_private;

1090 uint32_t *ctx_voodoo;

1091 uint32_t vramsz, tmp;

1092 int i, j;

1093

1094 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &

1095 ~NV_PMC_ENABLE_PGRAPH);

1096 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |

1097 NV_PMC_ENABLE_PGRAPH);

1098

1099 switch (dev_priv->chipset) {

1100 case 0x40: ctx_voodoo = nv40_ctx_voodoo; break;

1101 case 0x43: ctx_voodoo = nv43_ctx_voodoo; break;

1102 case 0x46: ctx_voodoo = nv46_ctx_voodoo; break;

1103 case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break;

1104 case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break;

1105 default:

1106 DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n",

1107 dev_priv->chipset);

1108 ctx_voodoo = NULL;

1109 break;

1110 }

1111

1112 /* Load the context voodoo onto the card */

1113 if (ctx_voodoo) {

1114 DRM_DEBUG("Loading context-switch voodoo\n");

1115 i = 0;

1116

1117 NV_WRITE(0x400324, 0);

1118 while (ctx_voodoo[i] != ~0) {

1119 NV_WRITE(0x400328, ctx_voodoo[i]);

1120 i++;

1121 }

1122 }

1123

1124 /* No context present currently */

1125 NV_WRITE(0x40032C, 0x00000000);

1126

1127 NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000);

1128 NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);

1129

1130 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);

1131 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);

1132 NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0);

1133 NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xe0de8055);

1134 NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000);

1135 NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);

1136

1137 NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);

1138 NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);

1139 NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);

1140

1141 j = NV_READ(0x1540) & 0xff;

1142 if (j) {

1143 for (i=0; !(j&1); j>>=1, i++);

1144 NV_WRITE(0x405000, i);

1145 }

1146

1147 if (dev_priv->chipset == 0x40) {

1148 NV_WRITE(0x4009b0, 0x83280fff);

1149 NV_WRITE(0x4009b4, 0x000000a0);

1150 } else {

1151 NV_WRITE(0x400820, 0x83280eff);

1152 NV_WRITE(0x400824, 0x000000a0);

1153 }

1154

1155 switch (dev_priv->chipset) {

1156 case 0x40:

1157 case 0x45:

1158 NV_WRITE(0x4009b8, 0x0078e366);

1159 NV_WRITE(0x4009bc, 0x0000014c);

1160 break;

1161 case 0x41:

1162 case 0x42: /* pciid also 0x00Cx */

1163 // case 0x0120: //XXX (pciid)

1164 NV_WRITE(0x400828, 0x007596ff);

1165 NV_WRITE(0x40082c, 0x00000108);

1166 break;

1167 case 0x43:

1168 NV_WRITE(0x400828, 0x0072cb77);

1169 NV_WRITE(0x40082c, 0x00000108);

1170 break;

1171 case 0x44:

1172 case 0x46: /* G72 */

1173 case 0x4a:

1174 case 0x4c: /* G7x-based C51 */

1175 case 0x4e:

1176 NV_WRITE(0x400860, 0);

1177 NV_WRITE(0x400864, 0);

1178 break;

1179 case 0x47: /* G70 */

1180 case 0x49: /* G71 */

1181 case 0x4b: /* G73 */

1182 NV_WRITE(0x400828, 0x07830610);

1183 NV_WRITE(0x40082c, 0x0000016A);

1184 break;

1185 default:

1186 break;

1187 }

1188

1189 NV_WRITE(0x400b38, 0x2ffff800);

1190 NV_WRITE(0x400b3c, 0x00006000);

1191

1192 /* copy tile info from PFB */

1193 switch (dev_priv->chipset) {

1194 case 0x40: /* vanilla NV40 */

1195 for (i=0; i<NV10_PFB_TILE__SIZE; i++) {

1196 tmp = NV_READ(NV10_PFB_TILE(i));

1197 NV_WRITE(NV40_PGRAPH_TILE0(i), tmp);

1198 NV_WRITE(NV40_PGRAPH_TILE1(i), tmp);

1199 tmp = NV_READ(NV10_PFB_TLIMIT(i));

1200 NV_WRITE(NV40_PGRAPH_TLIMIT0(i), tmp);

1201 NV_WRITE(NV40_PGRAPH_TLIMIT1(i), tmp);

1202 tmp = NV_READ(NV10_PFB_TSIZE(i));

1203 NV_WRITE(NV40_PGRAPH_TSIZE0(i), tmp);

1204 NV_WRITE(NV40_PGRAPH_TSIZE1(i), tmp);

1205 tmp = NV_READ(NV10_PFB_TSTATUS(i));

1206 NV_WRITE(NV40_PGRAPH_TSTATUS0(i), tmp);

1207 NV_WRITE(NV40_PGRAPH_TSTATUS1(i), tmp);

1208 }

1209 break;

1210 case 0x44:

1211 case 0x4a:

1212 case 0x4e: /* NV44-based cores don't have 0x406900? */

1213 for (i=0; i<NV40_PFB_TILE__SIZE_0; i++) {

1214 tmp = NV_READ(NV40_PFB_TILE(i));

1215 NV_WRITE(NV40_PGRAPH_TILE0(i), tmp);

1216 tmp = NV_READ(NV40_PFB_TLIMIT(i));

1217 NV_WRITE(NV40_PGRAPH_TLIMIT0(i), tmp);

1218 tmp = NV_READ(NV40_PFB_TSIZE(i));

1219 NV_WRITE(NV40_PGRAPH_TSIZE0(i), tmp);

1220 tmp = NV_READ(NV40_PFB_TSTATUS(i));

1221 NV_WRITE(NV40_PGRAPH_TSTATUS0(i), tmp);

1222 }

1223 break;

1224 case 0x46:

1225 case 0x47:

1226 case 0x49:

1227 case 0x4b: /* G7X-based cores */

1228 for (i=0; i<NV40_PFB_TILE__SIZE_1; i++) {

1229 tmp = NV_READ(NV40_PFB_TILE(i));

1230 NV_WRITE(NV47_PGRAPH_TILE0(i), tmp);

1231 NV_WRITE(NV40_PGRAPH_TILE1(i), tmp);

1232 tmp = NV_READ(NV40_PFB_TLIMIT(i));

1233 NV_WRITE(NV47_PGRAPH_TLIMIT0(i), tmp);

1234 NV_WRITE(NV40_PGRAPH_TLIMIT1(i), tmp);

1235 tmp = NV_READ(NV40_PFB_TSIZE(i));

1236 NV_WRITE(NV47_PGRAPH_TSIZE0(i), tmp);

1237 NV_WRITE(NV40_PGRAPH_TSIZE1(i), tmp);

1238 tmp = NV_READ(NV40_PFB_TSTATUS(i));

1239 NV_WRITE(NV47_PGRAPH_TSTATUS0(i), tmp);

1240 NV_WRITE(NV40_PGRAPH_TSTATUS1(i), tmp);

1241 }

1242 break;

1243 default: /* everything else */

1244 for (i=0; i<NV40_PFB_TILE__SIZE_0; i++) {

1245 tmp = NV_READ(NV40_PFB_TILE(i));

1246 NV_WRITE(NV40_PGRAPH_TILE0(i), tmp);

1247 NV_WRITE(NV40_PGRAPH_TILE1(i), tmp);

1248 tmp = NV_READ(NV40_PFB_TLIMIT(i));

1249 NV_WRITE(NV40_PGRAPH_TLIMIT0(i), tmp);

1250 NV_WRITE(NV40_PGRAPH_TLIMIT1(i), tmp);

1251 tmp = NV_READ(NV40_PFB_TSIZE(i));

1252 NV_WRITE(NV40_PGRAPH_TSIZE0(i), tmp);

1253 NV_WRITE(NV40_PGRAPH_TSIZE1(i), tmp);

1254 tmp = NV_READ(NV40_PFB_TSTATUS(i));

1255 NV_WRITE(NV40_PGRAPH_TSTATUS0(i), tmp);

1256 NV_WRITE(NV40_PGRAPH_TSTATUS1(i), tmp);

1257 }

1258 break;

1259 }

1260

1261 /* begin RAM config */

1262 vramsz = drm_get_resource_len(dev, 0) - 1;

1263 switch (dev_priv->chipset) {

1264 case 0x40:

1265 NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));

1266 NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));

1267 NV_WRITE(0x4069A4, NV_READ(NV04_PFB_CFG0));

1268 NV_WRITE(0x4069A8, NV_READ(NV04_PFB_CFG1));

1269 NV_WRITE(0x400820, 0);

1270 NV_WRITE(0x400824, 0);

1271 NV_WRITE(0x400864, vramsz);

1272 NV_WRITE(0x400868, vramsz);

1273 break;

1274 default:

1275 switch (dev_priv->chipset) {

1276 case 0x46:

1277 case 0x47:

1278 case 0x49:

1279 case 0x4b:

1280 NV_WRITE(0x400DF0, NV_READ(NV04_PFB_CFG0));

1281 NV_WRITE(0x400DF4, NV_READ(NV04_PFB_CFG1));

1282 break;

1283 default:

1284 NV_WRITE(0x4009F0, NV_READ(NV04_PFB_CFG0));

1285 NV_WRITE(0x4009F4, NV_READ(NV04_PFB_CFG1));

1286 break;

1287 }

1288 NV_WRITE(0x4069F0, NV_READ(NV04_PFB_CFG0));

1289 NV_WRITE(0x4069F4, NV_READ(NV04_PFB_CFG1));

1290 NV_WRITE(0x400840, 0);

1291 NV_WRITE(0x400844, 0);

1292 NV_WRITE(0x4008A0, vramsz);

1293 NV_WRITE(0x4008A4, vramsz);

1294 break;

1295 }

1296

1297 /* per-context state, doesn't belong here */

1298 NV_WRITE(0x400B20, 0x00000000);

1299 NV_WRITE(0x400B04, 0xFFFFFFFF);

1300

1301 tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;

1302 NV_WRITE(NV10_PGRAPH_SURFACE, tmp);

1303 tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;

1304 NV_WRITE(NV10_PGRAPH_SURFACE, tmp);

1305

1306 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);

1307 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);

1308 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);

1309 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);

1310

1311 return 0;

1312 }

1313

1314 void nv40_graph_takedown(drm_device_t *dev)

1315 {

1316 }

1317