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1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-

2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com

3 */

4 /*

8 *

9 * Permission is hereby granted, free of charge, to any person obtaining a

10 * copy of this software and associated documentation files (the "Software"),

11 * to deal in the Software without restriction, including without limitation

12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

13 * and/or sell copies of the Software, and to permit persons to whom the

14 * Software is furnished to do so, subject to the following conditions:

15 *

16 * The above copyright notice and this permission notice (including the next

17 * paragraph) shall be included in all copies or substantial portions of the

18 * Software.

19 *

20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR

24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

26 * DEALINGS IN THE SOFTWARE.

27 *

28 * Authors:

29 * Gareth Hughes <gareth@valinux.com>

30 */

32 #include "drmP.h"

33 #include "drm.h"

34 #include "r128_drm.h"

35 #include "r128_drv.h"

37 #define R128_FIFO_DEBUG 0

39 /* CCE microcode (from ATI) */

40 static u32 r128_cce_microcode[] = {

41 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,

42 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,

43 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,

44 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,

45 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,

46 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,

47 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,

48 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,

49 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,

50 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,

51 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,

52 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,

53 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,

54 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,

55 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,

56 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,

57 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,

58 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,

59 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,

60 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,

61 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,

62 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,

63 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,

64 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,

65 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,

66 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,

67 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,

68 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,

69 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,

70 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,

71 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,

72 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,

73 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,

74 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,

75 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

76 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

77 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0

82 };

84 static int R128_READ_PLL(drm_device_t * dev, int addr)

85 {

86 drm_r128_private_t *dev_priv = dev->dev_private;

88 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);

89 return R128_READ(R128_CLOCK_CNTL_DATA);

90 }

92 #if R128_FIFO_DEBUG

93 static void r128_status(drm_r128_private_t * dev_priv)

94 {

95 printk("GUI_STAT = 0x%08x\n",

96 (unsigned int)R128_READ(R128_GUI_STAT));

97 printk("PM4_STAT = 0x%08x\n",

98 (unsigned int)R128_READ(R128_PM4_STAT));

99 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",

100 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));

101 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",

102 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));

103 printk("PM4_MICRO_CNTL = 0x%08x\n",

104 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));

105 printk("PM4_BUFFER_CNTL = 0x%08x\n",

106 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));

107 }

108 #endif

109

110 /* ================================================================

111 * Engine, FIFO control

112 */

113

114 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)

115 {

116 u32 tmp;

117 int i;

118

119 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;

120 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);

121

122 for (i = 0; i < dev_priv->usec_timeout; i++) {

123 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {

124 return 0;

125 }

126 DRM_UDELAY(1);

127 }

128

129 #if R128_FIFO_DEBUG

130 DRM_ERROR("failed!\n");

131 #endif

132 return DRM_ERR(EBUSY);

133 }

134

135 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)

136 {

137 int i;

138

139 for (i = 0; i < dev_priv->usec_timeout; i++) {

140 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;

141 if (slots >= entries)

142 return 0;

143 DRM_UDELAY(1);

144 }

145

146 #if R128_FIFO_DEBUG

147 DRM_ERROR("failed!\n");

148 #endif

149 return DRM_ERR(EBUSY);

150 }

151

152 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)

153 {

154 int i, ret;

155

156 ret = r128_do_wait_for_fifo(dev_priv, 64);

157 if (ret)

158 return ret;

159

160 for (i = 0; i < dev_priv->usec_timeout; i++) {

161 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {

162 r128_do_pixcache_flush(dev_priv);

163 return 0;

164 }

165 DRM_UDELAY(1);

166 }

167

168 #if R128_FIFO_DEBUG

169 DRM_ERROR("failed!\n");

170 #endif

171 return DRM_ERR(EBUSY);

172 }

173

174 /* ================================================================

175 * CCE control, initialization

176 */

177

178 /* Load the microcode for the CCE */

179 static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)

180 {

181 int i;

182

183 DRM_DEBUG("\n");

184

185 r128_do_wait_for_idle(dev_priv);

186

187 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);

188 for (i = 0; i < 256; i++) {

189 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);

190 R128_WRITE(R128_PM4_MICROCODE_DATAL,

191 r128_cce_microcode[i * 2 + 1]);

192 }

193 }

194

195 /* Flush any pending commands to the CCE. This should only be used just

196 * prior to a wait for idle, as it informs the engine that the command

197 * stream is ending.

198 */

199 static void r128_do_cce_flush(drm_r128_private_t * dev_priv)

200 {

201 u32 tmp;

202

203 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;

204 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);

205 }

206

207 /* Wait for the CCE to go idle.

208 */

209 int r128_do_cce_idle(drm_r128_private_t * dev_priv)

210 {

211 int i;

212

213 for (i = 0; i < dev_priv->usec_timeout; i++) {

214 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {

215 int pm4stat = R128_READ(R128_PM4_STAT);

216 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=

217 dev_priv->cce_fifo_size) &&

218 !(pm4stat & (R128_PM4_BUSY |

219 R128_PM4_GUI_ACTIVE))) {

220 return r128_do_pixcache_flush(dev_priv);

221 }

222 }

223 DRM_UDELAY(1);

224 }

225

226 #if R128_FIFO_DEBUG

227 DRM_ERROR("failed!\n");

228 r128_status(dev_priv);

229 #endif

230 return DRM_ERR(EBUSY);

231 }

232

233 /* Start the Concurrent Command Engine.

234 */

235 static void r128_do_cce_start(drm_r128_private_t * dev_priv)

236 {

237 r128_do_wait_for_idle(dev_priv);

238

239 R128_WRITE(R128_PM4_BUFFER_CNTL,

240 dev_priv->cce_mode | dev_priv->ring.size_l2qw

241 | R128_PM4_BUFFER_CNTL_NOUPDATE);

242 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */

243 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);

244

245 dev_priv->cce_running = 1;

246 }

247

248 /* Reset the Concurrent Command Engine. This will not flush any pending

249 * commands, so you must wait for the CCE command stream to complete

250 * before calling this routine.

251 */

252 static void r128_do_cce_reset(drm_r128_private_t * dev_priv)

253 {

254 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);

255 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);

256 dev_priv->ring.tail = 0;

257 }

258

259 /* Stop the Concurrent Command Engine. This will not flush any pending

260 * commands, so you must flush the command stream and wait for the CCE

261 * to go idle before calling this routine.

262 */

263 static void r128_do_cce_stop(drm_r128_private_t * dev_priv)

264 {

265 R128_WRITE(R128_PM4_MICRO_CNTL, 0);

266 R128_WRITE(R128_PM4_BUFFER_CNTL,

267 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);

268

269 dev_priv->cce_running = 0;

270 }

271

272 /* Reset the engine. This will stop the CCE if it is running.

273 */

274 static int r128_do_engine_reset(drm_device_t * dev)

275 {

276 drm_r128_private_t *dev_priv = dev->dev_private;

277 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;

278

279 r128_do_pixcache_flush(dev_priv);

280

281 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);

282 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);

283

284 R128_WRITE_PLL(R128_MCLK_CNTL,

285 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);

286

287 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);

288

289 /* Taken from the sample code - do not change */

290 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);

291 R128_READ(R128_GEN_RESET_CNTL);

292 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);

293 R128_READ(R128_GEN_RESET_CNTL);

294

295 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);

296 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);

297 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);

298

299 /* Reset the CCE ring */

300 r128_do_cce_reset(dev_priv);

301

302 /* The CCE is no longer running after an engine reset */

303 dev_priv->cce_running = 0;

304

305 /* Reset any pending vertex, indirect buffers */

306 r128_freelist_reset(dev);

307

308 return 0;

309 }

310

311 static void r128_cce_init_ring_buffer(drm_device_t * dev,

312 drm_r128_private_t * dev_priv)

313 {

314 u32 ring_start;

315 u32 tmp;

316

317 DRM_DEBUG("\n");

318

319 /* The manual (p. 2) says this address is in "VM space". This

320 * means it's an offset from the start of AGP space.

321 */

322 #if __OS_HAS_AGP

323 if (!dev_priv->is_pci)

324 ring_start = dev_priv->cce_ring->offset - dev->agp->base;

325 else

326 #endif

327 ring_start = dev_priv->cce_ring->offset -

328 (unsigned long)dev->sg->virtual;

329

330 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);

331

332 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);

333 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);

334

335 /* Set watermark control */

336 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,

337 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)

338 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)

339 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)

340 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));

341

342 /* Force read. Why? Because it's in the examples... */

343 R128_READ(R128_PM4_BUFFER_ADDR);

344

345 /* Turn on bus mastering */

346 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;

347 R128_WRITE(R128_BUS_CNTL, tmp);

348 }

349

350 static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)

351 {

352 drm_r128_private_t *dev_priv;

353

354 DRM_DEBUG("\n");

355

356 dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);

357 if (dev_priv == NULL)

358 return DRM_ERR(ENOMEM);

359

360 memset(dev_priv, 0, sizeof(drm_r128_private_t));

361

362 dev_priv->is_pci = init->is_pci;

363

364 if (dev_priv->is_pci && !dev->sg) {

365 DRM_ERROR("PCI GART memory not allocated!\n");

366 dev->dev_private = (void *)dev_priv;

367 r128_do_cleanup_cce(dev);

368 return DRM_ERR(EINVAL);

369 }

370

371 dev_priv->usec_timeout = init->usec_timeout;

372 if (dev_priv->usec_timeout < 1 ||

373 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {

374 DRM_DEBUG("TIMEOUT problem!\n");

375 dev->dev_private = (void *)dev_priv;

376 r128_do_cleanup_cce(dev);

377 return DRM_ERR(EINVAL);

378 }

379

380 dev_priv->cce_mode = init->cce_mode;

381

382 /* GH: Simple idle check.

383 */

384 atomic_set(&dev_priv->idle_count, 0);

385

386 /* We don't support anything other than bus-mastering ring mode,

387 * but the ring can be in either AGP or PCI space for the ring

388 * read pointer.

389 */

390 if ((init->cce_mode != R128_PM4_192BM) &&

391 (init->cce_mode != R128_PM4_128BM_64INDBM) &&

392 (init->cce_mode != R128_PM4_64BM_128INDBM) &&

393 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {

394 DRM_DEBUG("Bad cce_mode!\n");

395 dev->dev_private = (void *)dev_priv;

396 r128_do_cleanup_cce(dev);

397 return DRM_ERR(EINVAL);

398 }

399

400 switch (init->cce_mode) {

401 case R128_PM4_NONPM4:

402 dev_priv->cce_fifo_size = 0;

403 break;

404 case R128_PM4_192PIO:

405 case R128_PM4_192BM:

406 dev_priv->cce_fifo_size = 192;

407 break;

408 case R128_PM4_128PIO_64INDBM:

409 case R128_PM4_128BM_64INDBM:

410 dev_priv->cce_fifo_size = 128;

411 break;

412 case R128_PM4_64PIO_128INDBM:

413 case R128_PM4_64BM_128INDBM:

414 case R128_PM4_64PIO_64VCBM_64INDBM:

415 case R128_PM4_64BM_64VCBM_64INDBM:

416 case R128_PM4_64PIO_64VCPIO_64INDPIO:

417 dev_priv->cce_fifo_size = 64;

418 break;

419 }

420

421 switch (init->fb_bpp) {

422 case 16:

423 dev_priv->color_fmt = R128_DATATYPE_RGB565;

424 break;

425 case 32:

426 default:

427 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;

428 break;

429 }

430 dev_priv->front_offset = init->front_offset;

431 dev_priv->front_pitch = init->front_pitch;

432 dev_priv->back_offset = init->back_offset;

433 dev_priv->back_pitch = init->back_pitch;

434

435 switch (init->depth_bpp) {

436 case 16:

437 dev_priv->depth_fmt = R128_DATATYPE_RGB565;

438 break;

439 case 24:

440 case 32:

441 default:

442 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;

443 break;

444 }

445 dev_priv->depth_offset = init->depth_offset;

446 dev_priv->depth_pitch = init->depth_pitch;

447 dev_priv->span_offset = init->span_offset;

448

449 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |

450 (dev_priv->front_offset >> 5));

451 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |

452 (dev_priv->back_offset >> 5));

453 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |

454 (dev_priv->depth_offset >> 5) |

455 R128_DST_TILE);

456 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |

457 (dev_priv->span_offset >> 5));

458

459 DRM_GETSAREA();

460

461 if (!dev_priv->sarea) {

462 DRM_ERROR("could not find sarea!\n");

463 dev->dev_private = (void *)dev_priv;

464 r128_do_cleanup_cce(dev);

465 return DRM_ERR(EINVAL);

466 }

467

468 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);

469 if (!dev_priv->mmio) {

470 DRM_ERROR("could not find mmio region!\n");

471 dev->dev_private = (void *)dev_priv;

472 r128_do_cleanup_cce(dev);

473 return DRM_ERR(EINVAL);

474 }

475 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);

476 if (!dev_priv->cce_ring) {

477 DRM_ERROR("could not find cce ring region!\n");

478 dev->dev_private = (void *)dev_priv;

479 r128_do_cleanup_cce(dev);

480 return DRM_ERR(EINVAL);

481 }

482 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);

483 if (!dev_priv->ring_rptr) {

484 DRM_ERROR("could not find ring read pointer!\n");

485 dev->dev_private = (void *)dev_priv;

486 r128_do_cleanup_cce(dev);

487 return DRM_ERR(EINVAL);

488 }

489 dev->agp_buffer_token = init->buffers_offset;

490 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);

491 if (!dev->agp_buffer_map) {

492 DRM_ERROR("could not find dma buffer region!\n");

493 dev->dev_private = (void *)dev_priv;

494 r128_do_cleanup_cce(dev);

495 return DRM_ERR(EINVAL);

496 }

497

498 if (!dev_priv->is_pci) {

499 dev_priv->agp_textures =

500 drm_core_findmap(dev, init->agp_textures_offset);

501 if (!dev_priv->agp_textures) {

502 DRM_ERROR("could not find agp texture region!\n");

503 dev->dev_private = (void *)dev_priv;

504 r128_do_cleanup_cce(dev);

505 return DRM_ERR(EINVAL);

506 }

507 }

508

509 dev_priv->sarea_priv =

510 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +

511 init->sarea_priv_offset);

512

513 #if __OS_HAS_AGP

514 if (!dev_priv->is_pci) {

515 drm_core_ioremap(dev_priv->cce_ring, dev);

516 drm_core_ioremap(dev_priv->ring_rptr, dev);

517 drm_core_ioremap(dev->agp_buffer_map, dev);

518 if (!dev_priv->cce_ring->handle ||

519 !dev_priv->ring_rptr->handle ||

520 !dev->agp_buffer_map->handle) {

521 DRM_ERROR("Could not ioremap agp regions!\n");

522 dev->dev_private = (void *)dev_priv;

523 r128_do_cleanup_cce(dev);

524 return DRM_ERR(ENOMEM);

525 }

526 } else

527 #endif

528 {

529 dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset;

530 dev_priv->ring_rptr->handle =

531 (void *)dev_priv->ring_rptr->offset;

532 dev->agp_buffer_map->handle =

533 (void *)dev->agp_buffer_map->offset;

534 }

535

536 #if __OS_HAS_AGP

537 if (!dev_priv->is_pci)

538 dev_priv->cce_buffers_offset = dev->agp->base;

539 else

540 #endif

541 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;

542

543 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;

544 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle

545 + init->ring_size / sizeof(u32));

546 dev_priv->ring.size = init->ring_size;

547 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);

548

549 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;

550

551 dev_priv->ring.high_mark = 128;

552

553 dev_priv->sarea_priv->last_frame = 0;

554 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);

555

556 dev_priv->sarea_priv->last_dispatch = 0;

557 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);

558

559 #if __OS_HAS_AGP

560 if (dev_priv->is_pci) {

561 #endif

562 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;

563 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;

564 dev_priv->gart_info.addr = NULL;

565 dev_priv->gart_info.bus_addr = 0;

566 dev_priv->gart_info.is_pcie = 0;

567 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {

568 DRM_ERROR("failed to init PCI GART!\n");

569 dev->dev_private = (void *)dev_priv;

570 r128_do_cleanup_cce(dev);

571 return DRM_ERR(ENOMEM);

572 }

573 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);

574 #if __OS_HAS_AGP

575 }

576 #endif

577

578 r128_cce_init_ring_buffer(dev, dev_priv);

579 r128_cce_load_microcode(dev_priv);

580

581 dev->dev_private = (void *)dev_priv;

582

583 r128_do_engine_reset(dev);

584

585 return 0;

586 }

587

588 int r128_do_cleanup_cce(drm_device_t * dev)

589 {

590

591 /* Make sure interrupts are disabled here because the uninstall ioctl

592 * may not have been called from userspace and after dev_private

593 * is freed, it's too late.

594 */

595 if (dev->irq_enabled)

596 drm_irq_uninstall(dev);

597

598 if (dev->dev_private) {

599 drm_r128_private_t *dev_priv = dev->dev_private;

600

601 #if __OS_HAS_AGP

602 if (!dev_priv->is_pci) {

603 if (dev_priv->cce_ring != NULL)

604 drm_core_ioremapfree(dev_priv->cce_ring, dev);

605 if (dev_priv->ring_rptr != NULL)

606 drm_core_ioremapfree(dev_priv->ring_rptr, dev);

607 if (dev->agp_buffer_map != NULL) {

608 drm_core_ioremapfree(dev->agp_buffer_map, dev);

609 dev->agp_buffer_map = NULL;

610 }

611 } else

612 #endif

613 {

614 if (dev_priv->gart_info.bus_addr)

615 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))

616 DRM_ERROR("failed to cleanup PCI GART!\n");

617 }

618

619 drm_free(dev->dev_private, sizeof(drm_r128_private_t),

620 DRM_MEM_DRIVER);

621 dev->dev_private = NULL;

622 }

623

624 return 0;

625 }

626

627 int r128_cce_init(DRM_IOCTL_ARGS)

628 {

629 DRM_DEVICE;

630 drm_r128_init_t init;

631

632 DRM_DEBUG("\n");

633

634 LOCK_TEST_WITH_RETURN(dev, filp);

635

636 DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data,

637 sizeof(init));

638

639 switch (init.func) {

640 case R128_INIT_CCE:

641 return r128_do_init_cce(dev, &init);

642 case R128_CLEANUP_CCE:

643 return r128_do_cleanup_cce(dev);

644 }

645

646 return DRM_ERR(EINVAL);

647 }

648

649 int r128_cce_start(DRM_IOCTL_ARGS)

650 {

651 DRM_DEVICE;

652 drm_r128_private_t *dev_priv = dev->dev_private;

653 DRM_DEBUG("\n");

654

655 LOCK_TEST_WITH_RETURN(dev, filp);

656

657 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {

658 DRM_DEBUG("%s while CCE running\n", __FUNCTION__);

659 return 0;

660 }

661

662 r128_do_cce_start(dev_priv);

663

664 return 0;

665 }

666

667 /* Stop the CCE. The engine must have been idled before calling this

668 * routine.

669 */

670 int r128_cce_stop(DRM_IOCTL_ARGS)

671 {

672 DRM_DEVICE;

673 drm_r128_private_t *dev_priv = dev->dev_private;

674 drm_r128_cce_stop_t stop;

675 int ret;

676 DRM_DEBUG("\n");

677

678 LOCK_TEST_WITH_RETURN(dev, filp);

679

680 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data,

681 sizeof(stop));

682

683 /* Flush any pending CCE commands. This ensures any outstanding

684 * commands are exectuted by the engine before we turn it off.

685 */

686 if (stop.flush) {

687 r128_do_cce_flush(dev_priv);

688 }

689

690 /* If we fail to make the engine go idle, we return an error

691 * code so that the DRM ioctl wrapper can try again.

692 */

693 if (stop.idle) {

694 ret = r128_do_cce_idle(dev_priv);

695 if (ret)

696 return ret;

697 }

698

699 /* Finally, we can turn off the CCE. If the engine isn't idle,

700 * we will get some dropped triangles as they won't be fully

701 * rendered before the CCE is shut down.

702 */

703 r128_do_cce_stop(dev_priv);

704

705 /* Reset the engine */

706 r128_do_engine_reset(dev);

707

708 return 0;

709 }

710

711 /* Just reset the CCE ring. Called as part of an X Server engine reset.

712 */

713 int r128_cce_reset(DRM_IOCTL_ARGS)

714 {

715 DRM_DEVICE;

716 drm_r128_private_t *dev_priv = dev->dev_private;

717 DRM_DEBUG("\n");

718

719 LOCK_TEST_WITH_RETURN(dev, filp);

720

721 if (!dev_priv) {

722 DRM_DEBUG("%s called before init done\n", __FUNCTION__);

723 return DRM_ERR(EINVAL);

724 }

725

726 r128_do_cce_reset(dev_priv);

727

728 /* The CCE is no longer running after an engine reset */

729 dev_priv->cce_running = 0;

730

731 return 0;

732 }

733

734 int r128_cce_idle(DRM_IOCTL_ARGS)

735 {

736 DRM_DEVICE;

737 drm_r128_private_t *dev_priv = dev->dev_private;

738 DRM_DEBUG("\n");

739

740 LOCK_TEST_WITH_RETURN(dev, filp);

741

742 if (dev_priv->cce_running) {

743 r128_do_cce_flush(dev_priv);

744 }

745

746 return r128_do_cce_idle(dev_priv);

747 }

748

749 int r128_engine_reset(DRM_IOCTL_ARGS)

750 {

751 DRM_DEVICE;

752 DRM_DEBUG("\n");

753

754 LOCK_TEST_WITH_RETURN(dev, filp);

755

756 return r128_do_engine_reset(dev);

757 }

758

759 int r128_fullscreen(DRM_IOCTL_ARGS)

760 {

761 return DRM_ERR(EINVAL);

762 }

763

764 /* ================================================================

765 * Freelist management

766 */

767 #define R128_BUFFER_USED 0xffffffff

768 #define R128_BUFFER_FREE 0

769

770 #if 0

771 static int r128_freelist_init(drm_device_t * dev)

772 {

773 drm_device_dma_t *dma = dev->dma;

774 drm_r128_private_t *dev_priv = dev->dev_private;

775 drm_buf_t *buf;

776 drm_r128_buf_priv_t *buf_priv;

777 drm_r128_freelist_t *entry;

778 int i;

779

780 dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);

781 if (dev_priv->head == NULL)

782 return DRM_ERR(ENOMEM);

783

784 memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));

785 dev_priv->head->age = R128_BUFFER_USED;

786

787 for (i = 0; i < dma->buf_count; i++) {

788 buf = dma->buflist[i];

789 buf_priv = buf->dev_private;

790

791 entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);

792 if (!entry)

793 return DRM_ERR(ENOMEM);

794

795 entry->age = R128_BUFFER_FREE;

796 entry->buf = buf;

797 entry->prev = dev_priv->head;

798 entry->next = dev_priv->head->next;

799 if (!entry->next)

800 dev_priv->tail = entry;

801

802 buf_priv->discard = 0;

803 buf_priv->dispatched = 0;

804 buf_priv->list_entry = entry;

805

806 dev_priv->head->next = entry;

807

808 if (dev_priv->head->next)

809 dev_priv->head->next->prev = entry;

810 }

811

812 return 0;

813

814 }

815 #endif

816

817 static drm_buf_t *r128_freelist_get(drm_device_t * dev)

818 {

819 drm_device_dma_t *dma = dev->dma;

820 drm_r128_private_t *dev_priv = dev->dev_private;

821 drm_r128_buf_priv_t *buf_priv;

822 drm_buf_t *buf;

823 int i, t;

824

825 /* FIXME: Optimize -- use freelist code */

826

827 for (i = 0; i < dma->buf_count; i++) {

828 buf = dma->buflist[i];

829 buf_priv = buf->dev_private;

830 if (buf->filp == 0)

831 return buf;

832 }

833

834 for (t = 0; t < dev_priv->usec_timeout; t++) {

835 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);

836

837 for (i = 0; i < dma->buf_count; i++) {

838 buf = dma->buflist[i];

839 buf_priv = buf->dev_private;

840 if (buf->pending && buf_priv->age <= done_age) {

841 /* The buffer has been processed, so it

842 * can now be used.

843 */

844 buf->pending = 0;

845 return buf;

846 }

847 }

848 DRM_UDELAY(1);

849 }

850

851 DRM_DEBUG("returning NULL!\n");

852 return NULL;

853 }

854

855 void r128_freelist_reset(drm_device_t * dev)

856 {

857 drm_device_dma_t *dma = dev->dma;

858 int i;

859

860 for (i = 0; i < dma->buf_count; i++) {

861 drm_buf_t *buf = dma->buflist[i];

862 drm_r128_buf_priv_t *buf_priv = buf->dev_private;

863 buf_priv->age = 0;

864 }

865 }

866

867 /* ================================================================

868 * CCE command submission

869 */

870

871 int r128_wait_ring(drm_r128_private_t * dev_priv, int n)

872 {

873 drm_r128_ring_buffer_t *ring = &dev_priv->ring;

874 int i;

875

876 for (i = 0; i < dev_priv->usec_timeout; i++) {

877 r128_update_ring_snapshot(dev_priv);

878 if (ring->space >= n)

879 return 0;

880 DRM_UDELAY(1);

881 }

882

883 /* FIXME: This is being ignored... */

884 DRM_ERROR("failed!\n");

885 return DRM_ERR(EBUSY);

886 }

887

888 static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)

889 {

890 int i;

891 drm_buf_t *buf;

892

893 for (i = d->granted_count; i < d->request_count; i++) {

894 buf = r128_freelist_get(dev);

895 if (!buf)

896 return DRM_ERR(EAGAIN);

897

898 buf->filp = filp;

899

900 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,

901 sizeof(buf->idx)))

902 return DRM_ERR(EFAULT);

903 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,

904 sizeof(buf->total)))

905 return DRM_ERR(EFAULT);

906

907 d->granted_count++;

908 }

909 return 0;

910 }

911

912 int r128_cce_buffers(DRM_IOCTL_ARGS)

913 {

914 DRM_DEVICE;

915 drm_device_dma_t *dma = dev->dma;

916 int ret = 0;

917 drm_dma_t __user *argp = (void __user *)data;

918 drm_dma_t d;

919

920 LOCK_TEST_WITH_RETURN(dev, filp);

921

922 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));

923

924 /* Please don't send us buffers.

925 */

926 if (d.send_count != 0) {

927 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",

928 DRM_CURRENTPID, d.send_count);

929 return DRM_ERR(EINVAL);

930 }

931

932 /* We'll send you buffers.

933 */

934 if (d.request_count < 0 || d.request_count > dma->buf_count) {

935 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",

936 DRM_CURRENTPID, d.request_count, dma->buf_count);

937 return DRM_ERR(EINVAL);

938 }

939

940 d.granted_count = 0;

941

942 if (d.request_count) {

943 ret = r128_cce_get_buffers(filp, dev, &d);

944 }

945

946 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));

947

948 return ret;

949 }