1 /**************************************************************************
3 Copyright (C) 2004-2005 Nicolai Haehnle et al.
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 on the rights to use, copy, modify, merge, publish, distribute, sub
9 license, and/or sell copies of the Software, and to permit persons to whom
10 the Software is furnished to do so, subject to the following conditions:
12 The above copyright notice and this permission notice (including the next
13 paragraph) shall be included in all copies or substantial portions of the
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 USE OR OTHER DEALINGS IN THE SOFTWARE.
24 **************************************************************************/
31 #define R300_MC_INIT_MISC_LAT_TIMER 0x180
32 # define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0
33 # define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4
34 # define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8
35 # define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12
36 # define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16
37 # define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20
38 # define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24
39 # define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28
42 #define R300_MC_INIT_GFX_LAT_TIMER 0x154
43 # define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0
44 # define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4
45 # define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8
46 # define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12
47 # define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16
48 # define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20
49 # define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24
50 # define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28
53 * This file contains registers and constants for the R300. They have been
54 * found mostly by examining command buffers captured using glxtest, as well
55 * as by extrapolating some known registers and constants from the R200.
56 * I am fairly certain that they are correct unless stated otherwise
60 #define R300_SE_VPORT_XSCALE 0x1D98
61 #define R300_SE_VPORT_XOFFSET 0x1D9C
62 #define R300_SE_VPORT_YSCALE 0x1DA0
63 #define R300_SE_VPORT_YOFFSET 0x1DA4
64 #define R300_SE_VPORT_ZSCALE 0x1DA8
65 #define R300_SE_VPORT_ZOFFSET 0x1DAC
69 * Vertex Array Processing (VAP) Control
70 * Stolen from r200 code from Christoph Brill (It's a guess!)
72 #define R300_VAP_CNTL 0x2080
74 /* This register is written directly and also starts data section
75 * in many 3d CP_PACKET3's
77 #define R300_VAP_VF_CNTL 0x2084
78 # define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
79 # define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)
80 # define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)
81 # define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)
82 # define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
83 # define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
84 # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
85 # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
86 # define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
87 # define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)
88 # define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
89 # define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
91 # define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
92 /* State based - direct writes to registers trigger vertex
94 # define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
95 # define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
96 # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
97 # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
99 /* I don't think I saw these three used.. */
100 # define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
101 # define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
102 # define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
104 /* index size - when not set the indices are assumed to be 16 bit */
105 # define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
106 /* number of vertices */
107 # define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
109 /* BEGIN: Wild guesses */
110 #define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
111 # define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
112 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1)
113 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */
114 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */
115 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */
116 # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */
118 #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
119 /* each of the following is 3 bits wide, specifies number
121 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
122 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
123 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
124 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
125 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
126 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
127 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
128 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
129 /* END: Wild guesses */
131 #define R300_SE_VTE_CNTL 0x20b0
132 # define R300_VTX_W0_NORMALIZE 0x00000800
133 # define R300_VTX_ST_DENORMALIZED 0x00001000
135 /* BEGIN: Vertex data assembly - lots of uncertainties */
139 #define R300_VAP_CNTL_STATUS 0x2140
140 # define R300_VC_NO_SWAP (0 << 0)
141 # define R300_VC_16BIT_SWAP (1 << 0)
142 # define R300_VC_32BIT_SWAP (2 << 0)
143 # define R300_VAP_TCL_BYPASS (1 << 8)
147 /* Where do we get our vertex data?
149 * Vertex data either comes either from immediate mode registers or from
151 * There appears to be no mixed mode (though we can force the pitch of
152 * vertex arrays to 0, effectively reusing the same element over and over
155 * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
156 * if these registers influence vertex array processing.
158 * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
160 * In both cases, vertex attributes are then passed through INPUT_ROUTE.
162 * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
163 * into the vertex processor's input registers.
164 * The first word routes the first input, the second word the second, etc.
165 * The corresponding input is routed into the register with the given index.
166 * The list is ended by a word with INPUT_ROUTE_END set.
168 * Always set COMPONENTS_4 in immediate mode.
171 #define R300_VAP_INPUT_ROUTE_0_0 0x2150
172 # define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0)
173 # define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0)
174 # define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0)
175 # define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0)
176 # define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */
177 # define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8
178 # define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */
179 # define R300_VAP_INPUT_ROUTE_END (1 << 13)
180 # define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */
181 # define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */
182 # define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */
183 # define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */
184 #define R300_VAP_INPUT_ROUTE_0_1 0x2154
185 #define R300_VAP_INPUT_ROUTE_0_2 0x2158
186 #define R300_VAP_INPUT_ROUTE_0_3 0x215C
187 #define R300_VAP_INPUT_ROUTE_0_4 0x2160
188 #define R300_VAP_INPUT_ROUTE_0_5 0x2164
189 #define R300_VAP_INPUT_ROUTE_0_6 0x2168
190 #define R300_VAP_INPUT_ROUTE_0_7 0x216C
195 * - always set up to produce at least two attributes:
196 * if vertex program uses only position, fglrx will set normal, too
197 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
199 #define R300_VAP_INPUT_CNTL_0 0x2180
200 # define R300_INPUT_CNTL_0_COLOR 0x00000001
201 #define R300_VAP_INPUT_CNTL_1 0x2184
202 # define R300_INPUT_CNTL_POS 0x00000001
203 # define R300_INPUT_CNTL_NORMAL 0x00000002
204 # define R300_INPUT_CNTL_COLOR 0x00000004
205 # define R300_INPUT_CNTL_TC0 0x00000400
206 # define R300_INPUT_CNTL_TC1 0x00000800
207 # define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */
208 # define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */
209 # define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */
210 # define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */
211 # define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */
212 # define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */
216 /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
217 * are set to a swizzling bit pattern, other words are 0.
219 * In immediate mode, the pattern is always set to xyzw. In vertex array
220 * mode, the swizzling pattern is e.g. used to set zw components in texture
221 * coordinates with only tweo components.
223 #define R300_VAP_INPUT_ROUTE_1_0 0x21E0
224 # define R300_INPUT_ROUTE_SELECT_X 0
225 # define R300_INPUT_ROUTE_SELECT_Y 1
226 # define R300_INPUT_ROUTE_SELECT_Z 2
227 # define R300_INPUT_ROUTE_SELECT_W 3
228 # define R300_INPUT_ROUTE_SELECT_ZERO 4
229 # define R300_INPUT_ROUTE_SELECT_ONE 5
230 # define R300_INPUT_ROUTE_SELECT_MASK 7
231 # define R300_INPUT_ROUTE_X_SHIFT 0
232 # define R300_INPUT_ROUTE_Y_SHIFT 3
233 # define R300_INPUT_ROUTE_Z_SHIFT 6
234 # define R300_INPUT_ROUTE_W_SHIFT 9
235 # define R300_INPUT_ROUTE_ENABLE (15 << 12)
236 #define R300_VAP_INPUT_ROUTE_1_1 0x21E4
237 #define R300_VAP_INPUT_ROUTE_1_2 0x21E8
238 #define R300_VAP_INPUT_ROUTE_1_3 0x21EC
239 #define R300_VAP_INPUT_ROUTE_1_4 0x21F0
240 #define R300_VAP_INPUT_ROUTE_1_5 0x21F4
241 #define R300_VAP_INPUT_ROUTE_1_6 0x21F8
242 #define R300_VAP_INPUT_ROUTE_1_7 0x21FC
244 /* END: Vertex data assembly */
248 /* BEGIN: Upload vertex program and data */
251 * The programmable vertex shader unit has a memory bank of unknown size
252 * that can be written to in 16 byte units by writing the address into
253 * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
255 * Pointers into the memory bank are always in multiples of 16 bytes.
257 * The memory bank is divided into areas with fixed meaning.
259 * Starting at address UPLOAD_PROGRAM: Vertex program instructions.
260 * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
261 * whereas the difference between known addresses suggests size 512.
263 * Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
264 * Native reported limits and the VPI layout suggest size 256, whereas
265 * difference between known addresses suggests size 512.
267 * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
268 * floating point pointsize. The exact purpose of this state is uncertain,
269 * as there is also the R300_RE_POINTSIZE register.
271 * Multiple vertex programs and parameter sets can be loaded at once,
272 * which could explain the size discrepancy.
274 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
275 # define R300_PVS_UPLOAD_PROGRAM 0x00000000
276 # define R300_PVS_UPLOAD_PARAMETERS 0x00000200
277 # define R300_PVS_UPLOAD_POINTSIZE 0x00000406
281 #define R300_VAP_PVS_UPLOAD_DATA 0x2208
283 /* END: Upload vertex program and data */
287 /* I do not know the purpose of this register. However, I do know that
288 * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
289 * for normal rendering.
291 #define R300_VAP_UNKNOWN_221C 0x221C
292 # define R300_221C_NORMAL 0x00000000
293 # define R300_221C_CLEAR 0x0001C000
295 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
296 * plane is per-pixel and the second plane is per-vertex.
298 * This was determined by experimentation alone but I believe it is correct.
300 * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.
302 #define R300_VAP_CLIP_X_0 0x2220
303 #define R300_VAP_CLIP_X_1 0x2224
304 #define R300_VAP_CLIP_Y_0 0x2228
305 #define R300_VAP_CLIP_Y_1 0x2230
309 /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
310 * rendering commands and overwriting vertex program parameters.
311 * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
312 * avoids bugs caused by still running shaders reading bad data from memory.
314 #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
316 /* Absolutely no clue what this register is about. */
317 #define R300_VAP_UNKNOWN_2288 0x2288
318 # define R300_2288_R300 0x00750000 /* -- nh */
319 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
323 /* Addresses are relative to the vertex program instruction area of the
324 * memory bank. PROGRAM_END points to the last instruction of the active
327 * The meaning of the two UNKNOWN fields is obviously not known. However,
328 * experiments so far have shown that both *must* point to an instruction
329 * inside the vertex program, otherwise the GPU locks up.
331 * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
332 * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
333 * position takes place.
335 * Most likely this is used to ignore rest of the program in cases
336 * where group of verts arent visible. For some reason this "section"
337 * is sometimes accepted other instruction that have no relationship with
338 * position calculations.
340 #define R300_VAP_PVS_CNTL_1 0x22D0
341 # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0
342 # define R300_PVS_CNTL_1_POS_END_SHIFT 10
343 # define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20
344 /* Addresses are relative the the vertex program parameters area. */
345 #define R300_VAP_PVS_CNTL_2 0x22D4
346 # define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
347 # define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16
348 #define R300_VAP_PVS_CNTL_3 0x22D8
349 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10
350 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0
352 /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
355 #define R300_VAP_VTX_COLOR_R 0x2464
356 #define R300_VAP_VTX_COLOR_G 0x2468
357 #define R300_VAP_VTX_COLOR_B 0x246C
358 #define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
359 #define R300_VAP_VTX_POS_0_Y_1 0x2494
360 #define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */
361 #define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
362 #define R300_VAP_VTX_POS_0_Y_2 0x24A4
363 #define R300_VAP_VTX_POS_0_Z_2 0x24A8
364 /* write 0 to indicate end of packet? */
365 #define R300_VAP_VTX_END_OF_PKT 0x24AC
369 /* These are values from r300_reg/r300_reg.h - they are known to be correct
370 * and are here so we can use one register file instead of several
373 #define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000
374 # define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
375 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
376 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
377 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
378 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
379 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5)
380 # define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16)
382 #define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004
383 /* each of the following is 3 bits wide, specifies number
385 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
386 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
387 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
388 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
389 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
390 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
391 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
392 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
394 /* UNK30 seems to enables point to quad transformation on textures
395 * (or something closely related to that).
396 * This bit is rather fatal at the time being due to lackings at pixel
399 #define R300_GB_ENABLE 0x4008
400 # define R300_GB_POINT_STUFF_ENABLE (1<<0)
401 # define R300_GB_LINE_STUFF_ENABLE (1<<1)
402 # define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2)
403 # define R300_GB_STENCIL_AUTO_ENABLE (1<<4)
404 # define R300_GB_UNK31 (1<<31)
405 /* each of the following is 2 bits wide */
406 #define R300_GB_TEX_REPLICATE 0
407 #define R300_GB_TEX_ST 1
408 #define R300_GB_TEX_STR 2
409 # define R300_GB_TEX0_SOURCE_SHIFT 16
410 # define R300_GB_TEX1_SOURCE_SHIFT 18
411 # define R300_GB_TEX2_SOURCE_SHIFT 20
412 # define R300_GB_TEX3_SOURCE_SHIFT 22
413 # define R300_GB_TEX4_SOURCE_SHIFT 24
414 # define R300_GB_TEX5_SOURCE_SHIFT 26
415 # define R300_GB_TEX6_SOURCE_SHIFT 28
416 # define R300_GB_TEX7_SOURCE_SHIFT 30
418 /* MSPOS - positions for multisample antialiasing (?) */
419 #define R300_GB_MSPOS0 0x4010
420 /* shifts - each of the fields is 4 bits */
421 # define R300_GB_MSPOS0__MS_X0_SHIFT 0
422 # define R300_GB_MSPOS0__MS_Y0_SHIFT 4
423 # define R300_GB_MSPOS0__MS_X1_SHIFT 8
424 # define R300_GB_MSPOS0__MS_Y1_SHIFT 12
425 # define R300_GB_MSPOS0__MS_X2_SHIFT 16
426 # define R300_GB_MSPOS0__MS_Y2_SHIFT 20
427 # define R300_GB_MSPOS0__MSBD0_Y 24
428 # define R300_GB_MSPOS0__MSBD0_X 28
430 #define R300_GB_MSPOS1 0x4014
431 # define R300_GB_MSPOS1__MS_X3_SHIFT 0
432 # define R300_GB_MSPOS1__MS_Y3_SHIFT 4
433 # define R300_GB_MSPOS1__MS_X4_SHIFT 8
434 # define R300_GB_MSPOS1__MS_Y4_SHIFT 12
435 # define R300_GB_MSPOS1__MS_X5_SHIFT 16
436 # define R300_GB_MSPOS1__MS_Y5_SHIFT 20
437 # define R300_GB_MSPOS1__MSBD1 24
440 #define R300_GB_TILE_CONFIG 0x4018
441 # define R300_GB_TILE_ENABLE (1<<0)
442 # define R300_GB_TILE_PIPE_COUNT_RV300 0
443 # define R300_GB_TILE_PIPE_COUNT_R300 (3<<1)
444 # define R300_GB_TILE_PIPE_COUNT_R420 (7<<1)
445 # define R300_GB_TILE_PIPE_COUNT_RV410 (3<<1)
446 # define R300_GB_TILE_SIZE_8 0
447 # define R300_GB_TILE_SIZE_16 (1<<4)
448 # define R300_GB_TILE_SIZE_32 (2<<4)
449 # define R300_GB_SUPER_SIZE_1 (0<<6)
450 # define R300_GB_SUPER_SIZE_2 (1<<6)
451 # define R300_GB_SUPER_SIZE_4 (2<<6)
452 # define R300_GB_SUPER_SIZE_8 (3<<6)
453 # define R300_GB_SUPER_SIZE_16 (4<<6)
454 # define R300_GB_SUPER_SIZE_32 (5<<6)
455 # define R300_GB_SUPER_SIZE_64 (6<<6)
456 # define R300_GB_SUPER_SIZE_128 (7<<6)
457 # define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */
458 # define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */
459 # define R300_GB_SUPER_TILE_A 0
460 # define R300_GB_SUPER_TILE_B (1<<15)
461 # define R300_GB_SUBPIXEL_1_12 0
462 # define R300_GB_SUBPIXEL_1_16 (1<<16)
464 #define R300_GB_FIFO_SIZE 0x4024
465 /* each of the following is 2 bits wide */
466 #define R300_GB_FIFO_SIZE_32 0
467 #define R300_GB_FIFO_SIZE_64 1
468 #define R300_GB_FIFO_SIZE_128 2
469 #define R300_GB_FIFO_SIZE_256 3
470 # define R300_SC_IFIFO_SIZE_SHIFT 0
471 # define R300_SC_TZFIFO_SIZE_SHIFT 2
472 # define R300_SC_BFIFO_SIZE_SHIFT 4
474 # define R300_US_OFIFO_SIZE_SHIFT 12
475 # define R300_US_WFIFO_SIZE_SHIFT 14
476 /* the following use the same constants as above, but meaning is
477 is times 2 (i.e. instead of 32 words it means 64 */
478 # define R300_RS_TFIFO_SIZE_SHIFT 6
479 # define R300_RS_CFIFO_SIZE_SHIFT 8
480 # define R300_US_RAM_SIZE_SHIFT 10
481 /* watermarks, 3 bits wide */
482 # define R300_RS_HIGHWATER_COL_SHIFT 16
483 # define R300_RS_HIGHWATER_TEX_SHIFT 19
484 # define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */
485 # define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24
488 # define R300_GB_FOG_SELECT_C0A 0
489 # define R300_GB_FOG_SELECT_C1A 1
490 # define R300_GB_FOG_SELECT_C2A 2
491 # define R300_GB_FOG_SELECT_C3A 3
492 # define R300_GB_FOG_SELECT_1_1_W 4
493 # define R300_GB_FOG_SELECT_Z 5
494 # define R300_GB_DEPTH_SELECT_Z 0
495 # define R300_GB_DEPTH_SELECT_1_1_W (1<<3)
496 # define R300_GB_W_SELECT_1_W 0
497 # define R300_GB_W_SELECT_1 (1<<4)
499 #define R300_GB_AA_CONFIG 0x4020
500 # define R300_AA_DISABLE 0x00
501 # define R300_AA_ENABLE 0x01
502 # define R300_AA_SUBSAMPLES_2 0
503 # define R300_AA_SUBSAMPLES_3 (1<<1)
504 # define R300_AA_SUBSAMPLES_4 (2<<1)
505 # define R300_AA_SUBSAMPLES_6 (3<<1)
509 /* Zero to flush caches. */
510 #define R300_TX_INVALTAGS 0x4100
511 #define R300_TX_FLUSH 0x0
513 /* The upper enable bits are guessed, based on fglrx reported limits. */
514 #define R300_TX_ENABLE 0x4104
515 # define R300_TX_ENABLE_0 (1 << 0)
516 # define R300_TX_ENABLE_1 (1 << 1)
517 # define R300_TX_ENABLE_2 (1 << 2)
518 # define R300_TX_ENABLE_3 (1 << 3)
519 # define R300_TX_ENABLE_4 (1 << 4)
520 # define R300_TX_ENABLE_5 (1 << 5)
521 # define R300_TX_ENABLE_6 (1 << 6)
522 # define R300_TX_ENABLE_7 (1 << 7)
523 # define R300_TX_ENABLE_8 (1 << 8)
524 # define R300_TX_ENABLE_9 (1 << 9)
525 # define R300_TX_ENABLE_10 (1 << 10)
526 # define R300_TX_ENABLE_11 (1 << 11)
527 # define R300_TX_ENABLE_12 (1 << 12)
528 # define R300_TX_ENABLE_13 (1 << 13)
529 # define R300_TX_ENABLE_14 (1 << 14)
530 # define R300_TX_ENABLE_15 (1 << 15)
532 /* The pointsize is given in multiples of 6. The pointsize can be
533 * enormous: Clear() renders a single point that fills the entire
536 #define R300_RE_POINTSIZE 0x421C
537 # define R300_POINTSIZE_Y_SHIFT 0
538 # define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */
539 # define R300_POINTSIZE_X_SHIFT 16
540 # define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */
541 # define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)
543 /* The line width is given in multiples of 6.
544 * In default mode lines are classified as vertical lines.
546 * VE: vertical or horizontal
547 * HO & VE: no classification
549 #define R300_RE_LINE_CNT 0x4234
550 # define R300_LINESIZE_SHIFT 0
551 # define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */
552 # define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6)
553 # define R300_LINE_CNT_HO (1 << 16)
554 # define R300_LINE_CNT_VE (1 << 17)
556 /* Some sort of scale or clamp value for texcoordless textures. */
557 #define R300_RE_UNK4238 0x4238
559 /* Something shade related */
560 #define R300_RE_SHADE 0x4274
562 #define R300_RE_SHADE_MODEL 0x4278
563 # define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa
564 # define R300_RE_SHADE_MODEL_FLAT 0x39595
567 #define R300_RE_POLYGON_MODE 0x4288
568 # define R300_PM_ENABLED (1 << 0)
569 # define R300_PM_FRONT_POINT (0 << 0)
570 # define R300_PM_BACK_POINT (0 << 0)
571 # define R300_PM_FRONT_LINE (1 << 4)
572 # define R300_PM_FRONT_FILL (1 << 5)
573 # define R300_PM_BACK_LINE (1 << 7)
574 # define R300_PM_BACK_FILL (1 << 8)
577 #define R300_RE_FOG_SCALE 0x4294
578 #define R300_RE_FOG_START 0x4298
580 /* Not sure why there are duplicate of factor and constant values.
581 * My best guess so far is that there are seperate zbiases for test and write.
582 * Ordering might be wrong.
583 * Some of the tests indicate that fgl has a fallback implementation of zbias
586 #define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */
587 #define R300_RE_ZBIAS_T_FACTOR 0x42A4
588 #define R300_RE_ZBIAS_T_CONSTANT 0x42A8
589 #define R300_RE_ZBIAS_W_FACTOR 0x42AC
590 #define R300_RE_ZBIAS_W_CONSTANT 0x42B0
592 /* This register needs to be set to (1<<1) for RV350 to correctly
593 * perform depth test (see --vb-triangles in r300_demo)
594 * Don't know about other chips. - Vladimir
595 * This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
596 * My guess is that there are two bits for each zbias primitive
597 * (FILL, LINE, POINT).
598 * One to enable depth test and one for depth write.
599 * Yet this doesnt explain why depth writes work ...
601 #define R300_RE_OCCLUSION_CNTL 0x42B4
602 # define R300_OCCLUSION_ON (1<<1)
604 #define R300_RE_CULL_CNTL 0x42B8
605 # define R300_CULL_FRONT (1 << 0)
606 # define R300_CULL_BACK (1 << 1)
607 # define R300_FRONT_FACE_CCW (0 << 2)
608 # define R300_FRONT_FACE_CW (1 << 2)
611 /* BEGIN: Rasterization / Interpolators - many guesses */
613 /* 0_UNKNOWN_18 has always been set except for clear operations.
614 * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
615 * on the vertex program, *not* the fragment program)
617 #define R300_RS_CNTL_0 0x4300
618 # define R300_RS_CNTL_TC_CNT_SHIFT 2
619 # define R300_RS_CNTL_TC_CNT_MASK (7 << 2)
620 /* number of color interpolators used */
621 # define R300_RS_CNTL_CI_CNT_SHIFT 7
622 # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18)
623 /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n
625 #define R300_RS_CNTL_1 0x4304
629 /* Only used for texture coordinates.
630 * Use the source field to route texture coordinate input from the
631 * vertex program to the desired interpolator. Note that the source
632 * field is relative to the outputs the vertex program *actually*
633 * writes. If a vertex program only writes texcoord[1], this will
635 * Set INTERP_USED on all interpolators that produce data used by
636 * the fragment program. INTERP_USED looks like a swizzling mask,
637 * but I haven't seen it used that way.
639 * Note: The _UNKNOWN constants are always set in their respective
640 * register. I don't know if this is necessary.
642 #define R300_RS_INTERP_0 0x4310
643 #define R300_RS_INTERP_1 0x4314
644 # define R300_RS_INTERP_1_UNKNOWN 0x40
645 #define R300_RS_INTERP_2 0x4318
646 # define R300_RS_INTERP_2_UNKNOWN 0x80
647 #define R300_RS_INTERP_3 0x431C
648 # define R300_RS_INTERP_3_UNKNOWN 0xC0
649 #define R300_RS_INTERP_4 0x4320
650 #define R300_RS_INTERP_5 0x4324
651 #define R300_RS_INTERP_6 0x4328
652 #define R300_RS_INTERP_7 0x432C
653 # define R300_RS_INTERP_SRC_SHIFT 2
654 # define R300_RS_INTERP_SRC_MASK (7 << 2)
655 # define R300_RS_INTERP_USED 0x00D10000
657 /* These DWORDs control how vertex data is routed into fragment program
658 * registers, after interpolators.
660 #define R300_RS_ROUTE_0 0x4330
661 #define R300_RS_ROUTE_1 0x4334
662 #define R300_RS_ROUTE_2 0x4338
663 #define R300_RS_ROUTE_3 0x433C /* GUESS */
664 #define R300_RS_ROUTE_4 0x4340 /* GUESS */
665 #define R300_RS_ROUTE_5 0x4344 /* GUESS */
666 #define R300_RS_ROUTE_6 0x4348 /* GUESS */
667 #define R300_RS_ROUTE_7 0x434C /* GUESS */
668 # define R300_RS_ROUTE_SOURCE_INTERP_0 0
669 # define R300_RS_ROUTE_SOURCE_INTERP_1 1
670 # define R300_RS_ROUTE_SOURCE_INTERP_2 2
671 # define R300_RS_ROUTE_SOURCE_INTERP_3 3
672 # define R300_RS_ROUTE_SOURCE_INTERP_4 4
673 # define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */
674 # define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */
675 # define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */
676 # define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */
677 # define R300_RS_ROUTE_DEST_SHIFT 6
678 # define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */
680 /* Special handling for color: When the fragment program uses color,
681 * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
682 * color register index.
684 * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any
685 * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state.
686 * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly
687 * correct or not. - Oliver.
689 # define R300_RS_ROUTE_0_COLOR (1 << 14)
690 # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17
691 # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */
692 /* As above, but for secondary color */
693 # define R300_RS_ROUTE_1_COLOR1 (1 << 14)
694 # define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17
695 # define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17)
696 # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
697 /* END: Rasterization / Interpolators - many guesses */
699 /* Hierarchical Z Enable */
700 #define R300_SC_HYPERZ 0x43a4
701 # define R300_SC_HYPERZ_DISABLE (0 << 0)
702 # define R300_SC_HYPERZ_ENABLE (1 << 0)
703 # define R300_SC_HYPERZ_MIN (0 << 1)
704 # define R300_SC_HYPERZ_MAX (1 << 1)
705 # define R300_SC_HYPERZ_ADJ_256 (0 << 2)
706 # define R300_SC_HYPERZ_ADJ_128 (1 << 2)
707 # define R300_SC_HYPERZ_ADJ_64 (2 << 2)
708 # define R300_SC_HYPERZ_ADJ_32 (3 << 2)
709 # define R300_SC_HYPERZ_ADJ_16 (4 << 2)
710 # define R300_SC_HYPERZ_ADJ_8 (5 << 2)
711 # define R300_SC_HYPERZ_ADJ_4 (6 << 2)
712 # define R300_SC_HYPERZ_ADJ_2 (7 << 2)
713 # define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
714 # define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
715 # define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
716 # define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
718 #define R300_SC_EDGERULE 0x43a8
720 /* BEGIN: Scissors and cliprects */
722 /* There are four clipping rectangles. Their corner coordinates are inclusive.
723 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
724 * on whether the pixel is inside cliprects 0-3, respectively. For example,
725 * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
726 * the number 3 (binary 0011).
727 * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
728 * the pixel is rasterized.
730 * In addition to this, there is a scissors rectangle. Only pixels inside the
731 * scissors rectangle are drawn. (coordinates are inclusive)
733 * For some reason, the top-left corner of the framebuffer is at (1440, 1440)
734 * for the purpose of clipping and scissors.
736 #define R300_RE_CLIPRECT_TL_0 0x43B0
737 #define R300_RE_CLIPRECT_BR_0 0x43B4
738 #define R300_RE_CLIPRECT_TL_1 0x43B8
739 #define R300_RE_CLIPRECT_BR_1 0x43BC
740 #define R300_RE_CLIPRECT_TL_2 0x43C0
741 #define R300_RE_CLIPRECT_BR_2 0x43C4
742 #define R300_RE_CLIPRECT_TL_3 0x43C8
743 #define R300_RE_CLIPRECT_BR_3 0x43CC
744 # define R300_CLIPRECT_OFFSET 1440
745 # define R300_CLIPRECT_MASK 0x1FFF
746 # define R300_CLIPRECT_X_SHIFT 0
747 # define R300_CLIPRECT_X_MASK (0x1FFF << 0)
748 # define R300_CLIPRECT_Y_SHIFT 13
749 # define R300_CLIPRECT_Y_MASK (0x1FFF << 13)
750 #define R300_RE_CLIPRECT_CNTL 0x43D0
751 # define R300_CLIP_OUT (1 << 0)
752 # define R300_CLIP_0 (1 << 1)
753 # define R300_CLIP_1 (1 << 2)
754 # define R300_CLIP_10 (1 << 3)
755 # define R300_CLIP_2 (1 << 4)
756 # define R300_CLIP_20 (1 << 5)
757 # define R300_CLIP_21 (1 << 6)
758 # define R300_CLIP_210 (1 << 7)
759 # define R300_CLIP_3 (1 << 8)
760 # define R300_CLIP_30 (1 << 9)
761 # define R300_CLIP_31 (1 << 10)
762 # define R300_CLIP_310 (1 << 11)
763 # define R300_CLIP_32 (1 << 12)
764 # define R300_CLIP_320 (1 << 13)
765 # define R300_CLIP_321 (1 << 14)
766 # define R300_CLIP_3210 (1 << 15)
770 #define R300_RE_SCISSORS_TL 0x43E0
771 #define R300_RE_SCISSORS_BR 0x43E4
772 # define R300_SCISSORS_OFFSET 1440
773 # define R300_SCISSORS_X_SHIFT 0
774 # define R300_SCISSORS_X_MASK (0x1FFF << 0)
775 # define R300_SCISSORS_Y_SHIFT 13
776 # define R300_SCISSORS_Y_MASK (0x1FFF << 13)
777 /* END: Scissors and cliprects */
779 /* BEGIN: Texture specification */
782 * The texture specification dwords are grouped by meaning and not by texture
783 * unit. This means that e.g. the offset for texture image unit N is found in
784 * register TX_OFFSET_0 + (4*N)
786 #define R300_TX_FILTER_0 0x4400
787 # define R300_TX_REPEAT 0
788 # define R300_TX_MIRRORED 1
789 # define R300_TX_CLAMP 4
790 # define R300_TX_CLAMP_TO_EDGE 2
791 # define R300_TX_CLAMP_TO_BORDER 6
792 # define R300_TX_WRAP_S_SHIFT 0
793 # define R300_TX_WRAP_S_MASK (7 << 0)
794 # define R300_TX_WRAP_T_SHIFT 3
795 # define R300_TX_WRAP_T_MASK (7 << 3)
796 # define R300_TX_WRAP_Q_SHIFT 6
797 # define R300_TX_WRAP_Q_MASK (7 << 6)
798 # define R300_TX_MAG_FILTER_NEAREST (1 << 9)
799 # define R300_TX_MAG_FILTER_LINEAR (2 << 9)
800 # define R300_TX_MAG_FILTER_MASK (3 << 9)
801 # define R300_TX_MIN_FILTER_NEAREST (1 << 11)
802 # define R300_TX_MIN_FILTER_LINEAR (2 << 11)
803 # define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11)
804 # define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11)
805 # define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11)
806 # define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11)
808 /* NOTE: NEAREST doesnt seem to exist.
809 * Im not seting MAG_FILTER_MASK and (3 << 11) on for all
810 * anisotropy modes because that would void selected mag filter
812 # define R300_TX_MIN_FILTER_ANISO_NEAREST (0 << 13)
813 # define R300_TX_MIN_FILTER_ANISO_LINEAR (0 << 13)
814 # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13)
815 # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (2 << 13)
816 # define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) )
817 # define R300_TX_MAX_ANISO_1_TO_1 (0 << 21)
818 # define R300_TX_MAX_ANISO_2_TO_1 (2 << 21)
819 # define R300_TX_MAX_ANISO_4_TO_1 (4 << 21)
820 # define R300_TX_MAX_ANISO_8_TO_1 (6 << 21)
821 # define R300_TX_MAX_ANISO_16_TO_1 (8 << 21)
822 # define R300_TX_MAX_ANISO_MASK (14 << 21)
824 #define R300_TX_FILTER1_0 0x4440
825 # define R300_CHROMA_KEY_MODE_DISABLE 0
826 # define R300_CHROMA_KEY_FORCE 1
827 # define R300_CHROMA_KEY_BLEND 2
828 # define R300_MC_ROUND_NORMAL (0<<2)
829 # define R300_MC_ROUND_MPEG4 (1<<2)
830 # define R300_LOD_BIAS_MASK 0x1fff
831 # define R300_EDGE_ANISO_EDGE_DIAG (0<<13)
832 # define R300_EDGE_ANISO_EDGE_ONLY (1<<13)
833 # define R300_MC_COORD_TRUNCATE_DISABLE (0<<14)
834 # define R300_MC_COORD_TRUNCATE_MPEG (1<<14)
835 # define R300_TX_TRI_PERF_0_8 (0<<15)
836 # define R300_TX_TRI_PERF_1_8 (1<<15)
837 # define R300_TX_TRI_PERF_1_4 (2<<15)
838 # define R300_TX_TRI_PERF_3_8 (3<<15)
839 # define R300_ANISO_THRESHOLD_MASK (7<<17)
841 #define R300_TX_SIZE_0 0x4480
842 # define R300_TX_WIDTHMASK_SHIFT 0
843 # define R300_TX_WIDTHMASK_MASK (2047 << 0)
844 # define R300_TX_HEIGHTMASK_SHIFT 11
845 # define R300_TX_HEIGHTMASK_MASK (2047 << 11)
846 # define R300_TX_UNK23 (1 << 23)
847 # define R300_TX_MAX_MIP_LEVEL_SHIFT 26
848 # define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26)
849 # define R300_TX_SIZE_PROJECTED (1<<30)
850 # define R300_TX_SIZE_TXPITCH_EN (1<<31)
851 #define R300_TX_FORMAT_0 0x44C0
852 /* The interpretation of the format word by Wladimir van der Laan */
853 /* The X, Y, Z and W refer to the layout of the components.
854 They are given meanings as R, G, B and Alpha by the swizzle
856 # define R300_TX_FORMAT_X8 0x0
857 # define R300_TX_FORMAT_X16 0x1
858 # define R300_TX_FORMAT_Y4X4 0x2
859 # define R300_TX_FORMAT_Y8X8 0x3
860 # define R300_TX_FORMAT_Y16X16 0x4
861 # define R300_TX_FORMAT_Z3Y3X2 0x5
862 # define R300_TX_FORMAT_Z5Y6X5 0x6
863 # define R300_TX_FORMAT_Z6Y5X5 0x7
864 # define R300_TX_FORMAT_Z11Y11X10 0x8
865 # define R300_TX_FORMAT_Z10Y11X11 0x9
866 # define R300_TX_FORMAT_W4Z4Y4X4 0xA
867 # define R300_TX_FORMAT_W1Z5Y5X5 0xB
868 # define R300_TX_FORMAT_W8Z8Y8X8 0xC
869 # define R300_TX_FORMAT_W2Z10Y10X10 0xD
870 # define R300_TX_FORMAT_W16Z16Y16X16 0xE
871 # define R300_TX_FORMAT_DXT1 0xF
872 # define R300_TX_FORMAT_DXT3 0x10
873 # define R300_TX_FORMAT_DXT5 0x11
874 # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
875 # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
876 # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
877 # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
878 /* 0x16 - some 16 bit green format.. ?? */
879 # define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */
880 # define R300_TX_FORMAT_CUBIC_MAP (1 << 26)
883 /* Floating point formats */
884 /* Note - hardware supports both 16 and 32 bit floating point */
885 # define R300_TX_FORMAT_FL_I16 0x18
886 # define R300_TX_FORMAT_FL_I16A16 0x19
887 # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
888 # define R300_TX_FORMAT_FL_I32 0x1B
889 # define R300_TX_FORMAT_FL_I32A32 0x1C
890 # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
891 /* alpha modes, convenience mostly */
892 /* if you have alpha, pick constant appropriate to the
893 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
894 # define R300_TX_FORMAT_ALPHA_1CH 0x000
895 # define R300_TX_FORMAT_ALPHA_2CH 0x200
896 # define R300_TX_FORMAT_ALPHA_4CH 0x600
897 # define R300_TX_FORMAT_ALPHA_NONE 0xA00
900 # define R300_TX_FORMAT_X 0
901 # define R300_TX_FORMAT_Y 1
902 # define R300_TX_FORMAT_Z 2
903 # define R300_TX_FORMAT_W 3
904 # define R300_TX_FORMAT_ZERO 4
905 # define R300_TX_FORMAT_ONE 5
906 /* 2.0*Z, everything above 1.0 is set to 0.0 */
907 # define R300_TX_FORMAT_CUT_Z 6
908 /* 2.0*W, everything above 1.0 is set to 0.0 */
909 # define R300_TX_FORMAT_CUT_W 7
911 # define R300_TX_FORMAT_B_SHIFT 18
912 # define R300_TX_FORMAT_G_SHIFT 15
913 # define R300_TX_FORMAT_R_SHIFT 12
914 # define R300_TX_FORMAT_A_SHIFT 9
915 /* Convenience macro to take care of layout and swizzling */
916 # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
917 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
918 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
919 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
920 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
921 | (R300_TX_FORMAT_##FMT) \
923 /* These can be ORed with result of R300_EASY_TX_FORMAT()
924 We don't really know what they do. Take values from a
926 # define R300_TX_FORMAT_CONST_X (1<<5)
927 # define R300_TX_FORMAT_CONST_Y (2<<5)
928 # define R300_TX_FORMAT_CONST_Z (4<<5)
929 # define R300_TX_FORMAT_CONST_W (8<<5)
931 # define R300_TX_FORMAT_YUV_MODE 0x00800000
933 #define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */
934 #define R300_TX_OFFSET_0 0x4540
935 /* BEGIN: Guess from R200 */
936 # define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
937 # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)
938 # define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)
939 # define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
940 # define R300_TXO_MACRO_TILE (1 << 2)
941 # define R300_TXO_MICRO_TILE (1 << 3)
942 # define R300_TXO_OFFSET_MASK 0xffffffe0
943 # define R300_TXO_OFFSET_SHIFT 5
944 /* END: Guess from R200 */
946 /* 32 bit chroma key */
947 #define R300_TX_CHROMA_KEY_0 0x4580
948 /* ff00ff00 == { 0, 1.0, 0, 1.0 } */
950 /* END: Texture specification */
952 /* BEGIN: Fragment program instruction set */
954 /* Fragment programs are written directly into register space.
955 * There are separate instruction streams for texture instructions and ALU
957 * In order to synchronize these streams, the program is divided into up
958 * to 4 nodes. Each node begins with a number of TEX operations, followed
959 * by a number of ALU operations.
960 * The first node can have zero TEX ops, all subsequent nodes must have at
963 * All nodes must have at least one ALU op.
965 * The index of the last node is stored in PFS_CNTL_0: A value of 0 means
966 * 1 node, a value of 3 means 4 nodes.
967 * The total amount of instructions is defined in PFS_CNTL_2. The offsets are
968 * offsets into the respective instruction streams, while *_END points to the
969 * last instruction relative to this offset.
971 #define R300_PFS_CNTL_0 0x4600
972 # define R300_PFS_CNTL_LAST_NODES_SHIFT 0
973 # define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)
974 # define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
975 #define R300_PFS_CNTL_1 0x4604
976 /* There is an unshifted value here which has so far always been equal to the
977 * index of the highest used temporary register.
979 #define R300_PFS_CNTL_2 0x4608
980 # define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0
981 # define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
982 # define R300_PFS_CNTL_ALU_END_SHIFT 6
983 # define R300_PFS_CNTL_ALU_END_MASK (63 << 6)
984 # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12
985 # define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */
986 # define R300_PFS_CNTL_TEX_END_SHIFT 18
987 # define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */
991 /* Nodes are stored backwards. The last active node is always stored in
993 * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
994 * first node is stored in NODE_2, the second node is stored in NODE_3.
996 * Offsets are relative to the master offset from PFS_CNTL_2.
998 #define R300_PFS_NODE_0 0x4610
999 #define R300_PFS_NODE_1 0x4614
1000 #define R300_PFS_NODE_2 0x4618
1001 #define R300_PFS_NODE_3 0x461C
1002 # define R300_PFS_NODE_ALU_OFFSET_SHIFT 0
1003 # define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0)
1004 # define R300_PFS_NODE_ALU_END_SHIFT 6
1005 # define R300_PFS_NODE_ALU_END_MASK (63 << 6)
1006 # define R300_PFS_NODE_TEX_OFFSET_SHIFT 12
1007 # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12)
1008 # define R300_PFS_NODE_TEX_END_SHIFT 17
1009 # define R300_PFS_NODE_TEX_END_MASK (31 << 17)
1010 # define R300_PFS_NODE_OUTPUT_COLOR (1 << 22)
1011 # define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23)
1014 * As far as I can tell, texture instructions cannot write into output
1015 * registers directly. A subsequent ALU instruction is always necessary,
1016 * even if it's just MAD o0, r0, 1, 0
1018 #define R300_PFS_TEXI_0 0x4620
1019 # define R300_FPITX_SRC_SHIFT 0
1020 # define R300_FPITX_SRC_MASK (31 << 0)
1022 # define R300_FPITX_SRC_CONST (1 << 5)
1023 # define R300_FPITX_DST_SHIFT 6
1024 # define R300_FPITX_DST_MASK (31 << 6)
1025 # define R300_FPITX_IMAGE_SHIFT 11
1026 /* GUESS based on layout and native limits */
1027 # define R300_FPITX_IMAGE_MASK (15 << 11)
1028 /* Unsure if these are opcodes, or some kind of bitfield, but this is how
1029 * they were set when I checked
1031 # define R300_FPITX_OPCODE_SHIFT 15
1032 # define R300_FPITX_OP_TEX 1
1033 # define R300_FPITX_OP_KIL 2
1034 # define R300_FPITX_OP_TXP 3
1035 # define R300_FPITX_OP_TXB 4
1036 # define R300_FPITX_OPCODE_MASK (7 << 15)
1039 * The ALU instructions register blocks are enumerated according to the order
1040 * in which fglrx. I assume there is space for 64 instructions, since
1041 * each block has space for a maximum of 64 DWORDs, and this matches reported
1044 * The basic functional block seems to be one MAD for each color and alpha,
1045 * and an adder that adds all components after the MUL.
1046 * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
1047 * - DP4: Use OUTC_DP4, OUTA_DP4
1048 * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
1049 * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
1050 * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1
1051 * - CMP: If ARG2 < 0, return ARG1, else return ARG0
1052 * - FLR: use FRC+MAD
1053 * - XPD: use MAD+MAD
1054 * - SGE, SLT: use MAD+CMP
1055 * - RSQ: use ABS modifier for argument
1056 * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation
1057 * (e.g. RCP) into color register
1058 * - apparently, there's no quick DST operation
1059 * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
1060 * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
1061 * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
1064 * First stage selects three sources from the available registers and
1065 * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
1066 * fglrx sorts the three source fields: Registers before constants,
1067 * lower indices before higher indices; I do not know whether this is
1070 * fglrx fills unused sources with "read constant 0"
1071 * According to specs, you cannot select more than two different constants.
1073 * Second stage selects the operands from the sources. This is defined in
1074 * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
1076 * Swizzling and negation happens in this stage, as well.
1078 * Important: Color and alpha seem to be mostly separate, i.e. their sources
1079 * selection appears to be fully independent (the register storage is probably
1080 * physically split into a color and an alpha section).
1081 * However (because of the apparent physical split), there is some interaction
1082 * WRT swizzling. If, for example, you want to load an R component into an
1083 * Alpha operand, this R component is taken from a *color* source, not from
1084 * an alpha source. The corresponding register doesn't even have to appear in
1085 * the alpha sources list. (I hope this all makes sense to you)
1087 * Destination selection
1088 * The destination register index is in FPI1 (color) and FPI3 (alpha)
1089 * together with enable bits.
1090 * There are separate enable bits for writing into temporary registers
1091 * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
1092 * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
1093 * same index must be used for both).
1095 * Note: There is a special form for LRP
1096 * - Argument order is the same as in ARB_fragment_program.
1097 * - Operation is MAD
1098 * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
1099 * - Set FPI0/FPI2_SPECIAL_LRP
1100 * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
1102 #define R300_PFS_INSTR1_0 0x46C0
1103 # define R300_FPI1_SRC0C_SHIFT 0
1104 # define R300_FPI1_SRC0C_MASK (31 << 0)
1105 # define R300_FPI1_SRC0C_CONST (1 << 5)
1106 # define R300_FPI1_SRC1C_SHIFT 6
1107 # define R300_FPI1_SRC1C_MASK (31 << 6)
1108 # define R300_FPI1_SRC1C_CONST (1 << 11)
1109 # define R300_FPI1_SRC2C_SHIFT 12
1110 # define R300_FPI1_SRC2C_MASK (31 << 12)
1111 # define R300_FPI1_SRC2C_CONST (1 << 17)
1112 # define R300_FPI1_SRC_MASK 0x0003ffff
1113 # define R300_FPI1_DSTC_SHIFT 18
1114 # define R300_FPI1_DSTC_MASK (31 << 18)
1115 # define R300_FPI1_DSTC_REG_MASK_SHIFT 23
1116 # define R300_FPI1_DSTC_REG_X (1 << 23)
1117 # define R300_FPI1_DSTC_REG_Y (1 << 24)
1118 # define R300_FPI1_DSTC_REG_Z (1 << 25)
1119 # define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT 26
1120 # define R300_FPI1_DSTC_OUTPUT_X (1 << 26)
1121 # define R300_FPI1_DSTC_OUTPUT_Y (1 << 27)
1122 # define R300_FPI1_DSTC_OUTPUT_Z (1 << 28)
1124 #define R300_PFS_INSTR3_0 0x47C0
1125 # define R300_FPI3_SRC0A_SHIFT 0
1126 # define R300_FPI3_SRC0A_MASK (31 << 0)
1127 # define R300_FPI3_SRC0A_CONST (1 << 5)
1128 # define R300_FPI3_SRC1A_SHIFT 6
1129 # define R300_FPI3_SRC1A_MASK (31 << 6)
1130 # define R300_FPI3_SRC1A_CONST (1 << 11)
1131 # define R300_FPI3_SRC2A_SHIFT 12
1132 # define R300_FPI3_SRC2A_MASK (31 << 12)
1133 # define R300_FPI3_SRC2A_CONST (1 << 17)
1134 # define R300_FPI3_SRC_MASK 0x0003ffff
1135 # define R300_FPI3_DSTA_SHIFT 18
1136 # define R300_FPI3_DSTA_MASK (31 << 18)
1137 # define R300_FPI3_DSTA_REG (1 << 23)
1138 # define R300_FPI3_DSTA_OUTPUT (1 << 24)
1139 # define R300_FPI3_DSTA_DEPTH (1 << 27)
1141 #define R300_PFS_INSTR0_0 0x48C0
1142 # define R300_FPI0_ARGC_SRC0C_XYZ 0
1143 # define R300_FPI0_ARGC_SRC0C_XXX 1
1144 # define R300_FPI0_ARGC_SRC0C_YYY 2
1145 # define R300_FPI0_ARGC_SRC0C_ZZZ 3
1146 # define R300_FPI0_ARGC_SRC1C_XYZ 4
1147 # define R300_FPI0_ARGC_SRC1C_XXX 5
1148 # define R300_FPI0_ARGC_SRC1C_YYY 6
1149 # define R300_FPI0_ARGC_SRC1C_ZZZ 7
1150 # define R300_FPI0_ARGC_SRC2C_XYZ 8
1151 # define R300_FPI0_ARGC_SRC2C_XXX 9
1152 # define R300_FPI0_ARGC_SRC2C_YYY 10
1153 # define R300_FPI0_ARGC_SRC2C_ZZZ 11
1154 # define R300_FPI0_ARGC_SRC0A 12
1155 # define R300_FPI0_ARGC_SRC1A 13
1156 # define R300_FPI0_ARGC_SRC2A 14
1157 # define R300_FPI0_ARGC_SRC1C_LRP 15
1158 # define R300_FPI0_ARGC_ZERO 20
1159 # define R300_FPI0_ARGC_ONE 21
1161 # define R300_FPI0_ARGC_HALF 22
1162 # define R300_FPI0_ARGC_SRC0C_YZX 23
1163 # define R300_FPI0_ARGC_SRC1C_YZX 24
1164 # define R300_FPI0_ARGC_SRC2C_YZX 25
1165 # define R300_FPI0_ARGC_SRC0C_ZXY 26
1166 # define R300_FPI0_ARGC_SRC1C_ZXY 27
1167 # define R300_FPI0_ARGC_SRC2C_ZXY 28
1168 # define R300_FPI0_ARGC_SRC0CA_WZY 29
1169 # define R300_FPI0_ARGC_SRC1CA_WZY 30
1170 # define R300_FPI0_ARGC_SRC2CA_WZY 31
1172 # define R300_FPI0_ARG0C_SHIFT 0
1173 # define R300_FPI0_ARG0C_MASK (31 << 0)
1174 # define R300_FPI0_ARG0C_NEG (1 << 5)
1175 # define R300_FPI0_ARG0C_ABS (1 << 6)
1176 # define R300_FPI0_ARG1C_SHIFT 7
1177 # define R300_FPI0_ARG1C_MASK (31 << 7)
1178 # define R300_FPI0_ARG1C_NEG (1 << 12)
1179 # define R300_FPI0_ARG1C_ABS (1 << 13)
1180 # define R300_FPI0_ARG2C_SHIFT 14
1181 # define R300_FPI0_ARG2C_MASK (31 << 14)
1182 # define R300_FPI0_ARG2C_NEG (1 << 19)
1183 # define R300_FPI0_ARG2C_ABS (1 << 20)
1184 # define R300_FPI0_SPECIAL_LRP (1 << 21)
1185 # define R300_FPI0_OUTC_MAD (0 << 23)
1186 # define R300_FPI0_OUTC_DP3 (1 << 23)
1187 # define R300_FPI0_OUTC_DP4 (2 << 23)
1188 # define R300_FPI0_OUTC_MIN (4 << 23)
1189 # define R300_FPI0_OUTC_MAX (5 << 23)
1190 # define R300_FPI0_OUTC_CMPH (7 << 23)
1191 # define R300_FPI0_OUTC_CMP (8 << 23)
1192 # define R300_FPI0_OUTC_FRC (9 << 23)
1193 # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
1194 # define R300_FPI0_OUTC_SAT (1 << 30)
1195 # define R300_FPI0_INSERT_NOP (1 << 31)
1197 #define R300_PFS_INSTR2_0 0x49C0
1198 # define R300_FPI2_ARGA_SRC0C_X 0
1199 # define R300_FPI2_ARGA_SRC0C_Y 1
1200 # define R300_FPI2_ARGA_SRC0C_Z 2
1201 # define R300_FPI2_ARGA_SRC1C_X 3
1202 # define R300_FPI2_ARGA_SRC1C_Y 4
1203 # define R300_FPI2_ARGA_SRC1C_Z 5
1204 # define R300_FPI2_ARGA_SRC2C_X 6
1205 # define R300_FPI2_ARGA_SRC2C_Y 7
1206 # define R300_FPI2_ARGA_SRC2C_Z 8
1207 # define R300_FPI2_ARGA_SRC0A 9
1208 # define R300_FPI2_ARGA_SRC1A 10
1209 # define R300_FPI2_ARGA_SRC2A 11
1210 # define R300_FPI2_ARGA_SRC1A_LRP 15
1211 # define R300_FPI2_ARGA_ZERO 16
1212 # define R300_FPI2_ARGA_ONE 17
1214 # define R300_FPI2_ARGA_HALF 18
1215 # define R300_FPI2_ARG0A_SHIFT 0
1216 # define R300_FPI2_ARG0A_MASK (31 << 0)
1217 # define R300_FPI2_ARG0A_NEG (1 << 5)
1219 # define R300_FPI2_ARG0A_ABS (1 << 6)
1220 # define R300_FPI2_ARG1A_SHIFT 7
1221 # define R300_FPI2_ARG1A_MASK (31 << 7)
1222 # define R300_FPI2_ARG1A_NEG (1 << 12)
1224 # define R300_FPI2_ARG1A_ABS (1 << 13)
1225 # define R300_FPI2_ARG2A_SHIFT 14
1226 # define R300_FPI2_ARG2A_MASK (31 << 14)
1227 # define R300_FPI2_ARG2A_NEG (1 << 19)
1229 # define R300_FPI2_ARG2A_ABS (1 << 20)
1230 # define R300_FPI2_SPECIAL_LRP (1 << 21)
1231 # define R300_FPI2_OUTA_MAD (0 << 23)
1232 # define R300_FPI2_OUTA_DP4 (1 << 23)
1233 # define R300_FPI2_OUTA_MIN (2 << 23)
1234 # define R300_FPI2_OUTA_MAX (3 << 23)
1235 # define R300_FPI2_OUTA_CMP (6 << 23)
1236 # define R300_FPI2_OUTA_FRC (7 << 23)
1237 # define R300_FPI2_OUTA_EX2 (8 << 23)
1238 # define R300_FPI2_OUTA_LG2 (9 << 23)
1239 # define R300_FPI2_OUTA_RCP (10 << 23)
1240 # define R300_FPI2_OUTA_RSQ (11 << 23)
1241 # define R300_FPI2_OUTA_SAT (1 << 30)
1242 # define R300_FPI2_UNKNOWN_31 (1 << 31)
1243 /* END: Fragment program instruction set */
1245 /* Fog state and color */
1246 #define R300_RE_FOG_STATE 0x4BC0
1247 # define R300_FOG_ENABLE (1 << 0)
1248 # define R300_FOG_MODE_LINEAR (0 << 1)
1249 # define R300_FOG_MODE_EXP (1 << 1)
1250 # define R300_FOG_MODE_EXP2 (2 << 1)
1251 # define R300_FOG_MODE_MASK (3 << 1)
1252 #define R300_FOG_COLOR_R 0x4BC8
1253 #define R300_FOG_COLOR_G 0x4BCC
1254 #define R300_FOG_COLOR_B 0x4BD0
1256 #define R300_PP_ALPHA_TEST 0x4BD4
1257 # define R300_REF_ALPHA_MASK 0x000000ff
1258 # define R300_ALPHA_TEST_FAIL (0 << 8)
1259 # define R300_ALPHA_TEST_LESS (1 << 8)
1260 # define R300_ALPHA_TEST_LEQUAL (3 << 8)
1261 # define R300_ALPHA_TEST_EQUAL (2 << 8)
1262 # define R300_ALPHA_TEST_GEQUAL (6 << 8)
1263 # define R300_ALPHA_TEST_GREATER (4 << 8)
1264 # define R300_ALPHA_TEST_NEQUAL (5 << 8)
1265 # define R300_ALPHA_TEST_PASS (7 << 8)
1266 # define R300_ALPHA_TEST_OP_MASK (7 << 8)
1267 # define R300_ALPHA_TEST_ENABLE (1 << 11)
1271 /* Fragment program parameters in 7.16 floating point */
1272 #define R300_PFS_PARAM_0_X 0x4C00
1273 #define R300_PFS_PARAM_0_Y 0x4C04
1274 #define R300_PFS_PARAM_0_Z 0x4C08
1275 #define R300_PFS_PARAM_0_W 0x4C0C
1276 /* GUESS: PARAM_31 is last, based on native limits reported by fglrx */
1277 #define R300_PFS_PARAM_31_X 0x4DF0
1278 #define R300_PFS_PARAM_31_Y 0x4DF4
1279 #define R300_PFS_PARAM_31_Z 0x4DF8
1280 #define R300_PFS_PARAM_31_W 0x4DFC
1283 * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in
1285 * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND
1286 * are set to the same
1287 * function (both registers are always set up completely in any case)
1288 * - Most blend flags are simply copied from R200 and not tested yet
1290 #define R300_RB3D_CBLEND 0x4E04
1291 #define R300_RB3D_ABLEND 0x4E08
1292 /* the following only appear in CBLEND */
1293 # define R300_BLEND_ENABLE (1 << 0)
1294 # define R300_BLEND_UNKNOWN (3 << 1)
1295 # define R300_BLEND_NO_SEPARATE (1 << 3)
1296 /* the following are shared between CBLEND and ABLEND */
1297 # define R300_FCN_MASK (3 << 12)
1298 # define R300_COMB_FCN_ADD_CLAMP (0 << 12)
1299 # define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)
1300 # define R300_COMB_FCN_SUB_CLAMP (2 << 12)
1301 # define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)
1302 # define R300_COMB_FCN_MIN (4 << 12)
1303 # define R300_COMB_FCN_MAX (5 << 12)
1304 # define R300_COMB_FCN_RSUB_CLAMP (6 << 12)
1305 # define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12)
1306 # define R300_BLEND_GL_ZERO (32)
1307 # define R300_BLEND_GL_ONE (33)
1308 # define R300_BLEND_GL_SRC_COLOR (34)
1309 # define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35)
1310 # define R300_BLEND_GL_DST_COLOR (36)
1311 # define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37)
1312 # define R300_BLEND_GL_SRC_ALPHA (38)
1313 # define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39)
1314 # define R300_BLEND_GL_DST_ALPHA (40)
1315 # define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41)
1316 # define R300_BLEND_GL_SRC_ALPHA_SATURATE (42)
1317 # define R300_BLEND_GL_CONST_COLOR (43)
1318 # define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44)
1319 # define R300_BLEND_GL_CONST_ALPHA (45)
1320 # define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46)
1321 # define R300_BLEND_MASK (63)
1322 # define R300_SRC_BLEND_SHIFT (16)
1323 # define R300_DST_BLEND_SHIFT (24)
1324 #define R300_RB3D_BLEND_COLOR 0x4E10
1325 #define R300_RB3D_COLORMASK 0x4E0C
1326 # define R300_COLORMASK0_B (1<<0)
1327 # define R300_COLORMASK0_G (1<<1)
1328 # define R300_COLORMASK0_R (1<<2)
1329 # define R300_COLORMASK0_A (1<<3)
1333 # define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */
1334 #define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */
1335 #define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */
1336 #define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */
1340 /* Bit 16: Larger tiles
1342 * Bit 18: Extremely weird tile like, but some pixels duplicated?
1344 # define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */
1345 # define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */
1346 # define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */
1347 # define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
1348 # define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
1349 # define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
1350 # define R300_COLOR_FORMAT_RGB565 (2 << 22)
1351 # define R300_COLOR_FORMAT_ARGB8888 (3 << 22)
1352 #define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */
1353 #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */
1354 #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */
1356 #define R300_RB3D_AARESOLVE_CTL 0x4E88
1359 /* Guess by Vladimir.
1360 * Set to 0A before 3D operations, set to 02 afterwards.
1362 /*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/
1363 # define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
1364 # define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A
1367 /* There seems to be no "write only" setting, so use Z-test = ALWAYS
1369 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
1371 #define R300_ZB_CNTL 0x4F00
1372 # define R300_STENCIL_ENABLE (1 << 0)
1373 # define R300_Z_ENABLE (1 << 1)
1374 # define R300_Z_WRITE_ENABLE (1 << 2)
1375 # define R300_Z_SIGNED_COMPARE (1 << 3)
1376 # define R300_STENCIL_FRONT_BACK (1 << 4)
1378 #define R300_ZB_ZSTENCILCNTL 0x4f04
1380 # define R300_ZS_NEVER 0
1381 # define R300_ZS_LESS 1
1382 # define R300_ZS_LEQUAL 2
1383 # define R300_ZS_EQUAL 3
1384 # define R300_ZS_GEQUAL 4
1385 # define R300_ZS_GREATER 5
1386 # define R300_ZS_NOTEQUAL 6
1387 # define R300_ZS_ALWAYS 7
1388 # define R300_ZS_MASK 7
1390 # define R300_ZS_KEEP 0
1391 # define R300_ZS_ZERO 1
1392 # define R300_ZS_REPLACE 2
1393 # define R300_ZS_INCR 3
1394 # define R300_ZS_DECR 4
1395 # define R300_ZS_INVERT 5
1396 # define R300_ZS_INCR_WRAP 6
1397 # define R300_ZS_DECR_WRAP 7
1398 # define R300_Z_FUNC_SHIFT 0
1399 /* front and back refer to operations done for front
1400 and back faces, i.e. separate stencil function support */
1401 # define R300_S_FRONT_FUNC_SHIFT 3
1402 # define R300_S_FRONT_SFAIL_OP_SHIFT 6
1403 # define R300_S_FRONT_ZPASS_OP_SHIFT 9
1404 # define R300_S_FRONT_ZFAIL_OP_SHIFT 12
1405 # define R300_S_BACK_FUNC_SHIFT 15
1406 # define R300_S_BACK_SFAIL_OP_SHIFT 18
1407 # define R300_S_BACK_ZPASS_OP_SHIFT 21
1408 # define R300_S_BACK_ZFAIL_OP_SHIFT 24
1410 #define R300_ZB_STENCILREFMASK 0x4f08
1411 # define R300_STENCILREF_SHIFT 0
1412 # define R300_STENCILREF_MASK 0x000000ff
1413 # define R300_STENCILMASK_SHIFT 8
1414 # define R300_STENCILMASK_MASK 0x0000ff00
1415 # define R300_STENCILWRITEMASK_SHIFT 16
1416 # define R300_STENCILWRITEMASK_MASK 0x00ff0000
1420 #define R300_ZB_FORMAT 0x4f10
1421 # define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
1422 # define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
1423 # define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
1424 /* reserved up to (15 << 0) */
1425 # define R300_INVERT_13E3_LEADING_ONES (0 << 4)
1426 # define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
1428 #define R300_ZB_ZTOP 0x4F14
1429 # define R300_ZTOP_DISABLE (0 << 0)
1430 # define R300_ZTOP_ENABLE (1 << 0)
1434 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
1435 # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
1436 # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
1437 # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
1438 # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
1439 # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
1440 # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
1442 #define R300_ZB_BW_CNTL 0x4f1c
1443 # define R300_HIZ_DISABLE (0 << 0)
1444 # define R300_HIZ_ENABLE (1 << 0)
1445 # define R300_HIZ_MIN (0 << 1)
1446 # define R300_HIZ_MAX (1 << 1)
1447 # define R300_FAST_FILL_DISABLE (0 << 2)
1448 # define R300_FAST_FILL_ENABLE (1 << 2)
1449 # define R300_RD_COMP_DISABLE (0 << 3)
1450 # define R300_RD_COMP_ENABLE (1 << 3)
1451 # define R300_WR_COMP_DISABLE (0 << 4)
1452 # define R300_WR_COMP_ENABLE (1 << 4)
1453 # define R300_ZB_CB_CLEAR_RMW (0 << 5)
1454 # define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
1455 # define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
1456 # define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
1458 # define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
1459 # define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
1460 # define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
1461 # define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
1463 # define R500_BMASK_ENABLE (0 << 10)
1464 # define R500_BMASK_DISABLE (1 << 10)
1465 # define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
1466 # define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
1467 # define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
1468 # define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
1469 # define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
1470 # define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
1471 # define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
1472 # define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
1473 # define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
1474 # define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
1475 # define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
1476 # define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
1477 # define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
1478 # define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
1479 # define R500_PEQ_PACKING_DISABLE (0 << 18)
1480 # define R500_PEQ_PACKING_ENABLE (1 << 18)
1481 # define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
1482 # define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
1487 /* Z Buffer Address Offset.
1488 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
1490 #define R300_ZB_DEPTHOFFSET 0x4f20
1492 /* Z Buffer Pitch and Endian Control */
1493 #define R300_ZB_DEPTHPITCH 0x4f24
1494 # define R300_DEPTHPITCH_MASK 0x00003FFC
1495 # define R300_DEPTHMACROTILE_DISABLE (0 << 16)
1496 # define R300_DEPTHMACROTILE_ENABLE (1 << 16)
1497 # define R300_DEPTHMICROTILE_LINEAR (0 << 17)
1498 # define R300_DEPTHMICROTILE_TILED (1 << 17)
1499 # define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
1500 # define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
1501 # define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
1502 # define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
1503 # define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
1505 /* Z Buffer Clear Value */
1506 #define R300_ZB_DEPTHCLEARVALUE 0x4f28
1508 #define R300_ZB_ZMASK_OFFSET 0x4f30
1509 #define R300_ZB_ZMASK_PITCH 0x4f34
1510 #define R300_ZB_ZMASK_WRINDEX 0x4f38
1511 #define R300_ZB_ZMASK_DWORD 0x4f3c
1512 #define R300_ZB_ZMASK_RDINDEX 0x4f40
1514 /* Hierarchical Z Memory Offset */
1515 #define R300_ZB_HIZ_OFFSET 0x4f44
1517 /* Hierarchical Z Write Index */
1518 #define R300_ZB_HIZ_WRINDEX 0x4f48
1520 /* Hierarchical Z Data */
1521 #define R300_ZB_HIZ_DWORD 0x4f4c
1523 /* Hierarchical Z Read Index */
1524 #define R300_ZB_HIZ_RDINDEX 0x4f50
1526 /* Hierarchical Z Pitch */
1527 #define R300_ZB_HIZ_PITCH 0x4f54
1529 /* Z Buffer Z Pass Counter Data */
1530 #define R300_ZB_ZPASS_DATA 0x4f58
1532 /* Z Buffer Z Pass Counter Address */
1533 #define R300_ZB_ZPASS_ADDR 0x4f5c
1535 /* Depth buffer X and Y coordinate offset */
1536 #define R300_ZB_DEPTHXY_OFFSET 0x4f60
1537 # define R300_DEPTHX_OFFSET_SHIFT 1
1538 # define R300_DEPTHX_OFFSET_MASK 0x000007FE
1539 # define R300_DEPTHY_OFFSET_SHIFT 17
1540 # define R300_DEPTHY_OFFSET_MASK 0x07FE0000
1542 /* Sets the fifo sizes */
1543 #define R500_ZB_FIFO_SIZE 0x4fd0
1544 # define R500_OP_FIFO_SIZE_FULL (0 << 0)
1545 # define R500_OP_FIFO_SIZE_HALF (1 << 0)
1546 # define R500_OP_FIFO_SIZE_QUATER (2 << 0)
1547 # define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
1549 /* Stencil Reference Value and Mask for backfacing quads */
1550 /* R300_ZB_STENCILREFMASK handles front face */
1551 #define R500_ZB_STENCILREFMASK_BF 0x4fd4
1552 # define R500_STENCILREF_SHIFT 0
1553 # define R500_STENCILREF_MASK 0x000000ff
1554 # define R500_STENCILMASK_SHIFT 8
1555 # define R500_STENCILMASK_MASK 0x0000ff00
1556 # define R500_STENCILWRITEMASK_SHIFT 16
1557 # define R500_STENCILWRITEMASK_MASK 0x00ff0000
1559 /* BEGIN: Vertex program instruction set */
1561 /* Every instruction is four dwords long:
1562 * DWORD 0: output and opcode
1563 * DWORD 1: first argument
1564 * DWORD 2: second argument
1565 * DWORD 3: third argument
1568 * - ABS r, a is implemented as MAX r, a, -a
1569 * - MOV is implemented as ADD to zero
1570 * - XPD is implemented as MUL + MAD
1571 * - FLR is implemented as FRC + ADD
1572 * - apparently, fglrx tries to schedule instructions so that there is at
1573 * least one instruction between the write to a temporary and the first
1574 * read from said temporary; however, violations of this scheduling are
1576 * - register indices seem to be unrelated with OpenGL aliasing to
1577 * conventional state
1578 * - only one attribute and one parameter can be loaded at a time; however,
1579 * the same attribute/parameter can be used for more than one argument
1580 * - the second software argument for POW is the third hardware argument
1582 * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
1584 * There is some magic surrounding LIT:
1585 * The single argument is replicated across all three inputs, but swizzled:
1586 * First argument: xyzy
1587 * Second argument: xyzx
1588 * Third argument: xyzw
1589 * Whenever the result is used later in the fragment program, fglrx forces
1590 * x and w to be 1.0 in the input selection; I don't know whether this is
1591 * strictly necessary
1593 #define R300_VPI_OUT_OP_DOT (1 << 0)
1594 #define R300_VPI_OUT_OP_MUL (2 << 0)
1595 #define R300_VPI_OUT_OP_ADD (3 << 0)
1596 #define R300_VPI_OUT_OP_MAD (4 << 0)
1597 #define R300_VPI_OUT_OP_DST (5 << 0)
1598 #define R300_VPI_OUT_OP_FRC (6 << 0)
1599 #define R300_VPI_OUT_OP_MAX (7 << 0)
1600 #define R300_VPI_OUT_OP_MIN (8 << 0)
1601 #define R300_VPI_OUT_OP_SGE (9 << 0)
1602 #define R300_VPI_OUT_OP_SLT (10 << 0)
1603 /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */
1604 #define R300_VPI_OUT_OP_UNK12 (12 << 0)
1605 #define R300_VPI_OUT_OP_ARL (13 << 0)
1606 #define R300_VPI_OUT_OP_EXP (65 << 0)
1607 #define R300_VPI_OUT_OP_LOG (66 << 0)
1608 /* Used in fog computations, scalar(scalar) */
1609 #define R300_VPI_OUT_OP_UNK67 (67 << 0)
1610 #define R300_VPI_OUT_OP_LIT (68 << 0)
1611 #define R300_VPI_OUT_OP_POW (69 << 0)
1612 #define R300_VPI_OUT_OP_RCP (70 << 0)
1613 #define R300_VPI_OUT_OP_RSQ (72 << 0)
1614 /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */
1615 #define R300_VPI_OUT_OP_UNK73 (73 << 0)
1616 #define R300_VPI_OUT_OP_EX2 (75 << 0)
1617 #define R300_VPI_OUT_OP_LG2 (76 << 0)
1618 #define R300_VPI_OUT_OP_MAD_2 (128 << 0)
1619 /* all temps, vector(scalar, vector, vector) */
1620 #define R300_VPI_OUT_OP_UNK129 (129 << 0)
1622 #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8)
1623 #define R300_VPI_OUT_REG_CLASS_ADDR (1 << 8)
1624 #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8)
1625 #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8)
1627 #define R300_VPI_OUT_REG_INDEX_SHIFT 13
1628 /* GUESS based on fglrx native limits */
1629 #define R300_VPI_OUT_REG_INDEX_MASK (31 << 13)
1631 #define R300_VPI_OUT_WRITE_X (1 << 20)
1632 #define R300_VPI_OUT_WRITE_Y (1 << 21)
1633 #define R300_VPI_OUT_WRITE_Z (1 << 22)
1634 #define R300_VPI_OUT_WRITE_W (1 << 23)
1636 #define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0)
1637 #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0)
1638 #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0)
1639 #define R300_VPI_IN_REG_CLASS_NONE (9 << 0)
1640 #define R300_VPI_IN_REG_CLASS_MASK (31 << 0)
1642 #define R300_VPI_IN_REG_INDEX_SHIFT 5
1643 /* GUESS based on fglrx native limits */
1644 #define R300_VPI_IN_REG_INDEX_MASK (255 << 5)
1646 /* The R300 can select components from the input register arbitrarily.
1647 * Use the following constants, shifted by the component shift you
1650 #define R300_VPI_IN_SELECT_X 0
1651 #define R300_VPI_IN_SELECT_Y 1
1652 #define R300_VPI_IN_SELECT_Z 2
1653 #define R300_VPI_IN_SELECT_W 3
1654 #define R300_VPI_IN_SELECT_ZERO 4
1655 #define R300_VPI_IN_SELECT_ONE 5
1656 #define R300_VPI_IN_SELECT_MASK 7
1658 #define R300_VPI_IN_X_SHIFT 13
1659 #define R300_VPI_IN_Y_SHIFT 16
1660 #define R300_VPI_IN_Z_SHIFT 19
1661 #define R300_VPI_IN_W_SHIFT 22
1663 #define R300_VPI_IN_NEG_X (1 << 25)
1664 #define R300_VPI_IN_NEG_Y (1 << 26)
1665 #define R300_VPI_IN_NEG_Z (1 << 27)
1666 #define R300_VPI_IN_NEG_W (1 << 28)
1667 /* END: Vertex program instruction set */
1669 /* BEGIN: Packet 3 commands */
1671 /* A primitive emission dword. */
1672 #define R300_PRIM_TYPE_NONE (0 << 0)
1673 #define R300_PRIM_TYPE_POINT (1 << 0)
1674 #define R300_PRIM_TYPE_LINE (2 << 0)
1675 #define R300_PRIM_TYPE_LINE_STRIP (3 << 0)
1676 #define R300_PRIM_TYPE_TRI_LIST (4 << 0)
1677 #define R300_PRIM_TYPE_TRI_FAN (5 << 0)
1678 #define R300_PRIM_TYPE_TRI_STRIP (6 << 0)
1679 #define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1680 #define R300_PRIM_TYPE_RECT_LIST (8 << 0)
1681 #define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1682 #define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1683 /* GUESS (based on r200) */
1684 #define R300_PRIM_TYPE_POINT_SPRITES (11 << 0)
1685 #define R300_PRIM_TYPE_LINE_LOOP (12 << 0)
1686 #define R300_PRIM_TYPE_QUADS (13 << 0)
1687 #define R300_PRIM_TYPE_QUAD_STRIP (14 << 0)
1688 #define R300_PRIM_TYPE_POLYGON (15 << 0)
1689 #define R300_PRIM_TYPE_MASK 0xF
1690 #define R300_PRIM_WALK_IND (1 << 4)
1691 #define R300_PRIM_WALK_LIST (2 << 4)
1692 #define R300_PRIM_WALK_RING (3 << 4)
1693 #define R300_PRIM_WALK_MASK (3 << 4)
1694 /* GUESS (based on r200) */
1695 #define R300_PRIM_COLOR_ORDER_BGRA (0 << 6)
1696 #define R300_PRIM_COLOR_ORDER_RGBA (1 << 6)
1697 #define R300_PRIM_NUM_VERTICES_SHIFT 16
1698 #define R300_PRIM_NUM_VERTICES_MASK 0xffff
1700 /* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
1701 * Two parameter dwords:
1702 * 0. The first parameter appears to be always 0
1703 * 1. The second parameter is a standard primitive emission dword.
1705 #define R300_PACKET3_3D_DRAW_VBUF 0x00002800
1707 /* Specify the full set of vertex arrays as (address, stride).
1708 * The first parameter is the number of vertex arrays specified.
1709 * The rest of the command is a variable length list of blocks, where
1710 * each block is three dwords long and specifies two arrays.
1711 * The first dword of a block is split into two words, the lower significant
1712 * word refers to the first array, the more significant word to the second
1713 * array in the block.
1714 * The low byte of each word contains the size of an array entry in dwords,
1715 * the high byte contains the stride of the array.
1716 * The second dword of a block contains the pointer to the first array,
1717 * the third dword of a block contains the pointer to the second array.
1718 * Note that if the total number of arrays is odd, the third dword of
1719 * the last block is omitted.
1721 #define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00
1723 #define R300_PACKET3_INDX_BUFFER 0x00003300
1724 # define R300_EB_UNK1_SHIFT 24
1725 # define R300_EB_UNK1 (0x80<<24)
1726 # define R300_EB_UNK2 0x0810
1727 #define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400
1728 #define R300_PACKET3_3D_DRAW_INDX_2 0x00003600
1730 /* END: Packet 3 commands */
1733 /* Color formats for 2d packets
1735 #define R300_CP_COLOR_FORMAT_CI8 2
1736 #define R300_CP_COLOR_FORMAT_ARGB1555 3
1737 #define R300_CP_COLOR_FORMAT_RGB565 4
1738 #define R300_CP_COLOR_FORMAT_ARGB8888 6
1739 #define R300_CP_COLOR_FORMAT_RGB332 7
1740 #define R300_CP_COLOR_FORMAT_RGB8 9
1741 #define R300_CP_COLOR_FORMAT_ARGB4444 15
1746 #define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
1748 #define R500_VAP_INDEX_OFFSET 0x208c
1750 #define R500_GA_US_VECTOR_INDEX 0x4250
1751 #define R500_GA_US_VECTOR_DATA 0x4254
1753 #define R500_RS_IP_0 0x4074
1754 #define R500_RS_INST_0 0x4320
1756 #define R500_US_CONFIG 0x4600
1758 #define R500_US_FC_CTRL 0x4624
1759 #define R500_US_CODE_ADDR 0x4630
1761 #define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0
1762 #define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8
1764 #endif /* _R300_REG_H */
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