1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef __RADEON_DRM_H__
34 #define __RADEON_DRM_H__
36 /* WARNING: If you change any of these defines, make sure to change the
37 * defines in the X server file (radeon_sarea.h)
39 #ifndef __RADEON_SAREA_DEFINES__
40 #define __RADEON_SAREA_DEFINES__
42 /* Old style state flags, required for sarea interface (1.1 and 1.2
43 * clears) and 1.2 drm_vertex2 ioctl.
45 #define RADEON_UPLOAD_CONTEXT 0x00000001
46 #define RADEON_UPLOAD_VERTFMT 0x00000002
47 #define RADEON_UPLOAD_LINE 0x00000004
48 #define RADEON_UPLOAD_BUMPMAP 0x00000008
49 #define RADEON_UPLOAD_MASKS 0x00000010
50 #define RADEON_UPLOAD_VIEWPORT 0x00000020
51 #define RADEON_UPLOAD_SETUP 0x00000040
52 #define RADEON_UPLOAD_TCL 0x00000080
53 #define RADEON_UPLOAD_MISC 0x00000100
54 #define RADEON_UPLOAD_TEX0 0x00000200
55 #define RADEON_UPLOAD_TEX1 0x00000400
56 #define RADEON_UPLOAD_TEX2 0x00000800
57 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000
58 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000
59 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000
60 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
61 #define RADEON_REQUIRE_QUIESCENCE 0x00010000
62 #define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
63 #define RADEON_UPLOAD_ALL 0x003effff
64 #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
66 /* New style per-packet identifiers for use in cmd_buffer ioctl with
67 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
68 * state bits and the packet size:
70 #define RADEON_EMIT_PP_MISC 0 /* context/7 */
71 #define RADEON_EMIT_PP_CNTL 1 /* context/3 */
72 #define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
73 #define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
74 #define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
75 #define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
76 #define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
77 #define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
78 #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
79 #define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
80 #define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
81 #define RADEON_EMIT_RE_MISC 11 /* misc/1 */
82 #define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
83 #define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
84 #define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
85 #define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
86 #define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
87 #define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
88 #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
89 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
90 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
91 #define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
92 #define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
93 #define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
94 #define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
95 #define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
96 #define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
97 #define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
98 #define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
99 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
100 #define R200_EMIT_TFACTOR_0 30 /* tf/7 */
101 #define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
102 #define R200_EMIT_VAP_CTL 32 /* vap/1 */
103 #define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
104 #define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
105 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
106 #define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
107 #define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
108 #define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
109 #define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
110 #define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
111 #define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
112 #define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
113 #define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
114 #define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
115 #define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
116 #define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
117 #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
118 #define R200_EMIT_VTE_CNTL 48 /* vte/1 */
119 #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
120 #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
121 #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
122 #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
123 #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
124 #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
125 #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
126 #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
127 #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
128 #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
129 #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
130 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
131 #define R200_EMIT_PP_CUBIC_FACES_0 61
132 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62
133 #define R200_EMIT_PP_CUBIC_FACES_1 63
134 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64
135 #define R200_EMIT_PP_CUBIC_FACES_2 65
136 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66
137 #define R200_EMIT_PP_CUBIC_FACES_3 67
138 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68
139 #define R200_EMIT_PP_CUBIC_FACES_4 69
140 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70
141 #define R200_EMIT_PP_CUBIC_FACES_5 71
142 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72
143 #define RADEON_EMIT_PP_TEX_SIZE_0 73
144 #define RADEON_EMIT_PP_TEX_SIZE_1 74
145 #define RADEON_EMIT_PP_TEX_SIZE_2 75
146 #define R200_EMIT_RB3D_BLENDCOLOR 76
147 #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
148 #define RADEON_EMIT_PP_CUBIC_FACES_0 78
149 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
150 #define RADEON_EMIT_PP_CUBIC_FACES_1 80
151 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
152 #define RADEON_EMIT_PP_CUBIC_FACES_2 82
153 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
154 #define R200_EMIT_PP_TRI_PERF_CNTL 84
155 #define R200_EMIT_PP_AFS_0 85
156 #define R200_EMIT_PP_AFS_1 86
157 #define R200_EMIT_ATF_TFACTOR 87
158 #define R200_EMIT_PP_TXCTLALL_0 88
159 #define R200_EMIT_PP_TXCTLALL_1 89
160 #define R200_EMIT_PP_TXCTLALL_2 90
161 #define R200_EMIT_PP_TXCTLALL_3 91
162 #define R200_EMIT_PP_TXCTLALL_4 92
163 #define R200_EMIT_PP_TXCTLALL_5 93
164 #define R200_EMIT_VAP_PVS_CNTL 94
165 #define RADEON_MAX_STATE_PACKETS 95
167 /* Commands understood by cmd_buffer ioctl. More can be added but
168 * obviously these can't be removed or changed:
170 #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
171 #define RADEON_CMD_SCALARS 2 /* emit scalar data */
172 #define RADEON_CMD_VECTORS 3 /* emit vector data */
173 #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
174 #define RADEON_CMD_PACKET3 5 /* emit hw packet */
175 #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
176 #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
177 #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
178 * doesn't make the cpu wait, just
179 * the graphics hardware */
180 #define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
185 unsigned char cmd_type, pad0, pad1, pad2;
188 unsigned char cmd_type, packet_id, pad0, pad1;
191 unsigned char cmd_type, offset, stride, count;
194 unsigned char cmd_type, offset, stride, count;
197 unsigned char cmd_type, addr_lo, addr_hi, count;
200 unsigned char cmd_type, buf_idx, pad0, pad1;
203 unsigned char cmd_type, flags, pad0, pad1;
205 } drm_radeon_cmd_header_t;
207 #define RADEON_WAIT_2D 0x1
208 #define RADEON_WAIT_3D 0x2
210 /* Allowed parameters for R300_CMD_PACKET3
212 #define R300_CMD_PACKET3_CLEAR 0
213 #define R300_CMD_PACKET3_RAW 1
215 /* Commands understood by cmd_buffer ioctl for R300.
216 * The interface has not been stabilized, so some of these may be removed
217 * and eventually reordered before stabilization.
219 #define R300_CMD_PACKET0 1
220 #define R300_CMD_VPU 2 /* emit vertex program upload */
221 #define R300_CMD_PACKET3 3 /* emit a packet3 */
222 #define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
223 #define R300_CMD_CP_DELAY 5
224 #define R300_CMD_DMA_DISCARD 6
225 #define R300_CMD_WAIT 7
226 # define R300_WAIT_2D 0x1
227 # define R300_WAIT_3D 0x2
228 # define R300_WAIT_2D_CLEAN 0x3
229 # define R300_WAIT_3D_CLEAN 0x4
230 #define R300_CMD_SCRATCH 8
235 unsigned char cmd_type, pad0, pad1, pad2;
238 unsigned char cmd_type, count, reglo, reghi;
241 unsigned char cmd_type, count, adrlo, adrhi;
244 unsigned char cmd_type, packet, pad0, pad1;
247 unsigned char cmd_type, packet;
248 unsigned short count; /* amount of packet2 to emit */
251 unsigned char cmd_type, buf_idx, pad0, pad1;
254 unsigned char cmd_type, flags, pad0, pad1;
257 unsigned char cmd_type, reg, n_bufs, flags;
259 } drm_r300_cmd_header_t;
261 #define RADEON_FRONT 0x1
262 #define RADEON_BACK 0x2
263 #define RADEON_DEPTH 0x4
264 #define RADEON_STENCIL 0x8
265 #define RADEON_CLEAR_FASTZ 0x80000000
266 #define RADEON_USE_HIERZ 0x40000000
267 #define RADEON_USE_COMP_ZBUF 0x20000000
271 #define RADEON_POINTS 0x1
272 #define RADEON_LINES 0x2
273 #define RADEON_LINE_STRIP 0x3
274 #define RADEON_TRIANGLES 0x4
275 #define RADEON_TRIANGLE_FAN 0x5
276 #define RADEON_TRIANGLE_STRIP 0x6
278 /* Vertex/indirect buffer size
280 #define RADEON_BUFFER_SIZE 65536
282 /* Byte offsets for indirect buffer data
284 #define RADEON_INDEX_PRIM_OFFSET 20
286 #define RADEON_SCRATCH_REG_OFFSET 32
288 #define RADEON_NR_SAREA_CLIPRECTS 12
290 /* There are 2 heaps (local/GART). Each region within a heap is a
291 * minimum of 64k, and there are at most 64 of them per heap.
293 #define RADEON_LOCAL_TEX_HEAP 0
294 #define RADEON_GART_TEX_HEAP 1
295 #define RADEON_NR_TEX_HEAPS 2
296 #define RADEON_NR_TEX_REGIONS 64
297 #define RADEON_LOG_TEX_GRANULARITY 16
299 #define RADEON_MAX_TEXTURE_LEVELS 12
300 #define RADEON_MAX_TEXTURE_UNITS 3
302 #define RADEON_MAX_SURFACES 8
304 /* Blits have strict offset rules. All blit offset must be aligned on
305 * a 1K-byte boundary.
307 #define RADEON_OFFSET_SHIFT 10
308 #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
309 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
311 #endif /* __RADEON_SAREA_DEFINES__ */
318 } radeon_color_regs_t;
322 unsigned int pp_misc; /* 0x1c14 */
323 unsigned int pp_fog_color;
324 unsigned int re_solid_color;
325 unsigned int rb3d_blendcntl;
326 unsigned int rb3d_depthoffset;
327 unsigned int rb3d_depthpitch;
328 unsigned int rb3d_zstencilcntl;
330 unsigned int pp_cntl; /* 0x1c38 */
331 unsigned int rb3d_cntl;
332 unsigned int rb3d_coloroffset;
333 unsigned int re_width_height;
334 unsigned int rb3d_colorpitch;
335 unsigned int se_cntl;
337 /* Vertex format state */
338 unsigned int se_coord_fmt; /* 0x1c50 */
341 unsigned int re_line_pattern; /* 0x1cd0 */
342 unsigned int re_line_state;
344 unsigned int se_line_width; /* 0x1db8 */
347 unsigned int pp_lum_matrix; /* 0x1d00 */
349 unsigned int pp_rot_matrix_0; /* 0x1d58 */
350 unsigned int pp_rot_matrix_1;
353 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
354 unsigned int rb3d_ropcntl;
355 unsigned int rb3d_planemask;
358 unsigned int se_vport_xscale; /* 0x1d98 */
359 unsigned int se_vport_xoffset;
360 unsigned int se_vport_yscale;
361 unsigned int se_vport_yoffset;
362 unsigned int se_vport_zscale;
363 unsigned int se_vport_zoffset;
366 unsigned int se_cntl_status; /* 0x2140 */
369 unsigned int re_top_left; /* 0x26c0 */
370 unsigned int re_misc;
371 } drm_radeon_context_regs_t;
375 unsigned int se_zbias_factor; /* 0x1dac */
376 unsigned int se_zbias_constant;
377 } drm_radeon_context2_regs_t;
379 /* Setup registers for each texture unit
382 unsigned int pp_txfilter;
383 unsigned int pp_txformat;
384 unsigned int pp_txoffset;
385 unsigned int pp_txcblend;
386 unsigned int pp_txablend;
387 unsigned int pp_tfactor;
388 unsigned int pp_border_color;
389 } drm_radeon_texture_regs_t;
395 unsigned int stateidx:8;
396 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
397 unsigned int vc_format; /* vertex format */
401 drm_radeon_context_regs_t context;
402 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
403 drm_radeon_context2_regs_t context2;
405 } drm_radeon_state_t;
408 /* The channel for communication of state information to the
409 * kernel on firing a vertex buffer with either of the
410 * obsoleted vertex/index ioctls.
412 drm_radeon_context_regs_t context_state;
413 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
415 unsigned int vertsize;
416 unsigned int vc_format;
418 /* The current cliprects, or a subset thereof.
420 drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
423 /* Counters for client-side throttling of rendering clients.
425 unsigned int last_frame;
426 unsigned int last_dispatch;
427 unsigned int last_clear;
429 drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
431 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
433 int pfState; /* number of 3d windows (0,1,2ormore) */
434 int pfCurrentPage; /* which buffer is being displayed? */
435 int crtc2_base; /* CRTC2 frame offset */
436 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
437 } drm_radeon_sarea_t;
439 /* WARNING: If you change any of these defines, make sure to change the
440 * defines in the Xserver file (xf86drmRadeon.h)
442 * KW: actually it's illegal to change any of this (backwards compatibility).
445 /* Radeon specific ioctls
446 * The device specific ioctl range is 0x40 to 0x79.
448 #define DRM_RADEON_CP_INIT 0x00
449 #define DRM_RADEON_CP_START 0x01
450 #define DRM_RADEON_CP_STOP 0x02
451 #define DRM_RADEON_CP_RESET 0x03
452 #define DRM_RADEON_CP_IDLE 0x04
453 #define DRM_RADEON_RESET 0x05
454 #define DRM_RADEON_FULLSCREEN 0x06
455 #define DRM_RADEON_SWAP 0x07
456 #define DRM_RADEON_CLEAR 0x08
457 #define DRM_RADEON_VERTEX 0x09
458 #define DRM_RADEON_INDICES 0x0A
459 #define DRM_RADEON_NOT_USED
460 #define DRM_RADEON_STIPPLE 0x0C
461 #define DRM_RADEON_INDIRECT 0x0D
462 #define DRM_RADEON_TEXTURE 0x0E
463 #define DRM_RADEON_VERTEX2 0x0F
464 #define DRM_RADEON_CMDBUF 0x10
465 #define DRM_RADEON_GETPARAM 0x11
466 #define DRM_RADEON_FLIP 0x12
467 #define DRM_RADEON_ALLOC 0x13
468 #define DRM_RADEON_FREE 0x14
469 #define DRM_RADEON_INIT_HEAP 0x15
470 #define DRM_RADEON_IRQ_EMIT 0x16
471 #define DRM_RADEON_IRQ_WAIT 0x17
472 #define DRM_RADEON_CP_RESUME 0x18
473 #define DRM_RADEON_SETPARAM 0x19
474 #define DRM_RADEON_SURF_ALLOC 0x1a
475 #define DRM_RADEON_SURF_FREE 0x1b
477 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
478 #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
479 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
480 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
481 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
482 #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
483 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
484 #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
485 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
486 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
487 #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
488 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
489 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
490 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
491 #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
492 #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
493 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
494 #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
495 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
496 #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
497 #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
498 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
499 #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
500 #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
501 #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
502 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
503 #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
505 typedef struct drm_radeon_init {
507 RADEON_INIT_CP = 0x01,
508 RADEON_CLEANUP_CP = 0x02,
509 RADEON_INIT_R200_CP = 0x03,
510 RADEON_INIT_R300_CP = 0x04
512 unsigned long sarea_priv_offset;
513 int is_pci; /* for overriding only */
520 unsigned int front_offset, front_pitch;
521 unsigned int back_offset, back_pitch;
522 unsigned int depth_bpp;
523 unsigned int depth_offset, depth_pitch;
525 unsigned long fb_offset DEPRECATED; /* deprecated, driver asks hardware */
526 unsigned long mmio_offset DEPRECATED; /* deprecated, driver asks hardware */
527 unsigned long ring_offset;
528 unsigned long ring_rptr_offset;
529 unsigned long buffers_offset;
530 unsigned long gart_textures_offset;
533 typedef struct drm_radeon_cp_stop {
536 } drm_radeon_cp_stop_t;
538 typedef struct drm_radeon_fullscreen {
540 RADEON_INIT_FULLSCREEN = 0x01,
541 RADEON_CLEANUP_FULLSCREEN = 0x02
543 } drm_radeon_fullscreen_t;
549 #define CLEAR_DEPTH 4
551 typedef union drm_radeon_clear_rect {
554 } drm_radeon_clear_rect_t;
556 typedef struct drm_radeon_clear {
558 unsigned int clear_color;
559 unsigned int clear_depth;
560 unsigned int color_mask;
561 unsigned int depth_mask; /* misnamed field: should be stencil */
562 drm_radeon_clear_rect_t __user *depth_boxes;
563 } drm_radeon_clear_t;
565 typedef struct drm_radeon_vertex {
567 int idx; /* Index of vertex buffer */
568 int count; /* Number of vertices in buffer */
569 int discard; /* Client finished with buffer? */
570 } drm_radeon_vertex_t;
572 typedef struct drm_radeon_indices {
577 int discard; /* Client finished with buffer? */
578 } drm_radeon_indices_t;
580 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
581 * - allows multiple primitives and state changes in a single ioctl
582 * - supports driver change to emit native primitives
584 typedef struct drm_radeon_vertex2 {
585 int idx; /* Index of vertex buffer */
586 int discard; /* Client finished with buffer? */
588 drm_radeon_state_t __user *state;
590 drm_radeon_prim_t __user *prim;
591 } drm_radeon_vertex2_t;
593 /* v1.3 - obsoletes drm_radeon_vertex2
594 * - allows arbitarily large cliprect list
595 * - allows updating of tcl packet, vector and scalar state
596 * - allows memory-efficient description of state updates
597 * - allows state to be emitted without a primitive
598 * (for clears, ctx switches)
599 * - allows more than one dma buffer to be referenced per ioctl
600 * - supports tcl driver
601 * - may be extended in future versions with new cmd types, packets
603 typedef struct drm_radeon_cmd_buffer {
607 drm_clip_rect_t __user *boxes;
608 } drm_radeon_cmd_buffer_t;
610 typedef struct drm_radeon_tex_image {
611 unsigned int x, y; /* Blit coordinates */
612 unsigned int width, height;
613 const void __user *data;
614 } drm_radeon_tex_image_t;
616 typedef struct drm_radeon_texture {
620 int width; /* Texture image coordinates */
622 drm_radeon_tex_image_t __user *image;
623 } drm_radeon_texture_t;
625 typedef struct drm_radeon_stipple {
626 unsigned int __user *mask;
627 } drm_radeon_stipple_t;
629 typedef struct drm_radeon_indirect {
634 } drm_radeon_indirect_t;
636 /* enum for card type parameters */
637 #define RADEON_CARD_PCI 0
638 #define RADEON_CARD_AGP 1
639 #define RADEON_CARD_PCIE 2
641 /* 1.3: An ioctl to get parameters that aren't available to the 3d
642 * client any other way.
644 #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
645 #define RADEON_PARAM_LAST_FRAME 2
646 #define RADEON_PARAM_LAST_DISPATCH 3
647 #define RADEON_PARAM_LAST_CLEAR 4
648 /* Added with DRM version 1.6. */
649 #define RADEON_PARAM_IRQ_NR 5
650 #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
651 /* Added with DRM version 1.8. */
652 #define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
653 #define RADEON_PARAM_STATUS_HANDLE 8
654 #define RADEON_PARAM_SAREA_HANDLE 9
655 #define RADEON_PARAM_GART_TEX_HANDLE 10
656 #define RADEON_PARAM_SCRATCH_OFFSET 11
657 #define RADEON_PARAM_CARD_TYPE 12
658 #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
660 typedef struct drm_radeon_getparam {
663 } drm_radeon_getparam_t;
665 /* 1.6: Set up a memory manager for regions of shared memory:
667 #define RADEON_MEM_REGION_GART 1
668 #define RADEON_MEM_REGION_FB 2
670 typedef struct drm_radeon_mem_alloc {
674 int __user *region_offset; /* offset from start of fb or GART */
675 } drm_radeon_mem_alloc_t;
677 typedef struct drm_radeon_mem_free {
680 } drm_radeon_mem_free_t;
682 typedef struct drm_radeon_mem_init_heap {
686 } drm_radeon_mem_init_heap_t;
688 /* 1.6: Userspace can request & wait on irq's:
690 typedef struct drm_radeon_irq_emit {
692 } drm_radeon_irq_emit_t;
694 typedef struct drm_radeon_irq_wait {
696 } drm_radeon_irq_wait_t;
698 /* 1.10: Clients tell the DRM where they think the framebuffer is located in
699 * the card's address space, via a new generic ioctl to set parameters
702 typedef struct drm_radeon_setparam {
705 } drm_radeon_setparam_t;
707 #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
708 #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
709 #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
711 #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
712 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
713 #define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
714 /* 1.14: Clients can allocate/free a surface
716 typedef struct drm_radeon_surface_alloc {
717 unsigned int address;
720 } drm_radeon_surface_alloc_t;
722 typedef struct drm_radeon_surface_free {
723 unsigned int address;
724 } drm_radeon_surface_free_t;
726 #define DRM_RADEON_VBLANK_CRTC1 1
727 #define DRM_RADEON_VBLANK_CRTC2 2