1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
35 /* General customization:
38 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
40 #define DRIVER_NAME "radeon"
41 #define DRIVER_DESC "ATI Radeon"
42 #define DRIVER_DATE "20080528"
47 * 1.2 - Add vertex2 ioctl (keith)
48 * - Add stencil capability to clear ioctl (gareth, keith)
49 * - Increase MAX_TEXTURE_LEVELS (brian)
50 * 1.3 - Add cmdbuf ioctl (keith)
51 * - Add support for new radeon packets (keith)
52 * - Add getparam ioctl (keith)
53 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
54 * 1.4 - Add scratch registers to get_param ioctl.
55 * 1.5 - Add r200 packets to cmdbuf ioctl
56 * - Add r200 function to init ioctl
57 * - Add 'scalar2' instruction to cmdbuf
58 * 1.6 - Add static GART memory manager
59 * Add irq handler (won't be turned on unless X server knows to)
60 * Add irq ioctls and irq_active getparam.
61 * Add wait command for cmdbuf ioctl
62 * Add GART offset query for getparam
63 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
64 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
65 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
66 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
67 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
68 * Add 'GET' queries for starting additional clients on different VT's.
69 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
70 * Add texture rectangle support for r100.
71 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
72 * clients use to tell the DRM where they think the framebuffer is
73 * located in the card's address space
74 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
75 * and GL_EXT_blend_[func|equation]_separate on r200
76 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
77 * (No 3D support yet - just microcode loading).
78 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
79 * - Add hyperz support, add hyperz flags to clear ioctl.
80 * 1.14- Add support for color tiling
81 * - Add R100/R200 surface allocation/free support
82 * 1.15- Add support for texture micro tiling
83 * - Add support for r100 cube maps
84 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
85 * texture filtering on r200
86 * 1.17- Add initial support for R300 (3D).
87 * 1.18- Add support for GL_ATI_fragment_shader, new packets
88 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
89 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
90 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
91 * 1.19- Add support for gart table in FB memory and PCIE r300
92 * 1.20- Add support for r300 texrect
93 * 1.21- Add support for card type getparam
94 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
95 * 1.23- Add new radeon memory map work from benh
96 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
97 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
99 * 1.26- Add support for variable size PCI(E) gart aperture
100 * 1.27- Add support for IGPGART
101 * 1.28- Add support for VBL on CRTC2
102 * 1.29- R500 3D cmd buffer support
105 #define DRIVER_MAJOR 1
106 #define DRIVER_MINOR 30
107 #define DRIVER_PATCHLEVEL 0
110 * Radeon chip families
154 enum radeon_chip_flags {
155 RADEON_FAMILY_MASK = 0x0000ffffUL,
156 RADEON_FLAGS_MASK = 0xffff0000UL,
157 RADEON_IS_MOBILITY = 0x00010000UL,
158 RADEON_IS_IGP = 0x00020000UL,
159 RADEON_SINGLE_CRTC = 0x00040000UL,
160 RADEON_IS_AGP = 0x00080000UL,
161 RADEON_HAS_HIERZ = 0x00100000UL,
162 RADEON_IS_PCIE = 0x00200000UL,
163 RADEON_NEW_MEMMAP = 0x00400000UL,
164 RADEON_IS_PCI = 0x00800000UL,
165 RADEON_IS_IGPGART = 0x01000000UL,
171 enum radeon_pll_errata {
172 CHIP_ERRATA_R300_CG = 0x00000001,
173 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
174 CHIP_ERRATA_PLL_DELAY = 0x00000004
177 enum radeon_ext_tmds_chip {
183 #if defined(__powerpc__)
184 enum radeon_mac_model {
187 RADEON_MAC_POWERBOOK_EXTERNAL,
188 RADEON_MAC_POWERBOOK_INTERNAL,
189 RADEON_MAC_POWERBOOK_VGA,
190 RADEON_MAC_MINI_EXTERNAL,
191 RADEON_MAC_MINI_INTERNAL,
192 RADEON_MAC_IMAC_G5_ISIGHT
197 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
198 (dev_priv->mm.ring_read.bo ? readl(dev_priv->mm.ring_read.kmap.virtual + 0) : DRM_READ32((dev_priv)->ring_rptr, 0 )) : \
199 RADEON_READ(RADEON_CP_RB_RPTR))
201 #define SET_RING_HEAD(dev_priv,val) (dev_priv->mm.ring_read.bo ? \
202 writel((val), dev_priv->mm.ring_read.kmap.virtual) : \
203 DRM_WRITE32((dev_priv)->ring_rptr, 0, (val)))
205 typedef struct drm_radeon_freelist {
208 struct drm_radeon_freelist *next;
209 struct drm_radeon_freelist *prev;
210 } drm_radeon_freelist_t;
212 typedef struct drm_radeon_ring_buffer {
215 int size; /* Double Words */
216 int size_l2qw; /* log2 Quad Words */
218 int rptr_update; /* Double Words */
219 int rptr_update_l2qw; /* log2 Quad Words */
221 int fetch_size; /* Double Words */
222 int fetch_size_l2ow; /* log2 Oct Words */
229 } drm_radeon_ring_buffer_t;
231 typedef struct drm_radeon_depth_clear_t {
233 u32 rb3d_zstencilcntl;
235 } drm_radeon_depth_clear_t;
237 struct drm_radeon_driver_file_fields {
238 int64_t radeon_fb_delta;
242 struct mem_block *next;
243 struct mem_block *prev;
246 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
249 struct radeon_surface {
256 struct radeon_virt_surface {
261 struct drm_file *file_priv;
264 struct radeon_mm_obj {
265 struct drm_buffer_object *bo;
266 struct drm_bo_kmap_obj kmap;
269 struct radeon_mm_info {
270 uint64_t vram_offset; // Offset into GPU space
272 uint64_t vram_visible;
277 struct radeon_mm_obj pcie_table;
278 struct radeon_mm_obj ring;
279 struct radeon_mm_obj ring_read;
281 struct radeon_mm_obj dma_bufs;
282 struct drm_map fake_agp_map;
285 #include "radeon_mode.h"
287 struct drm_radeon_master_private {
288 drm_local_map_t *sarea;
289 drm_radeon_sarea_t *sarea_priv;
292 /* command submission struct */
293 struct drm_radeon_cs_priv {
296 uint32_t id_last_wcnt;
297 uint32_t id_last_scnt;
299 int (*parse)(struct drm_device *dev, struct drm_file *file_priv,
300 void *ib, uint32_t *packets, uint32_t dwords);
301 void (*id_emit)(struct drm_device *dev, uint32_t *id);
302 uint32_t (*id_last_get)(struct drm_device *dev);
303 /* this ib handling callback are for hidding memory manager drm
304 * from memory manager less drm, free have to emit ib discard
305 * sequence into the ring */
306 int (*ib_get)(struct drm_device *dev, void **ib, uint32_t dwords, uint32_t *card_offset);
307 uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib);
308 void (*ib_free)(struct drm_device *dev, void *ib, uint32_t dwords);
309 /* do a relocation either MM or non-MM */
310 int (*relocate)(struct drm_device *dev, struct drm_file *file_priv,
311 uint32_t *reloc, uint32_t *offset);
314 typedef struct drm_radeon_private {
316 drm_radeon_ring_buffer_t ring;
324 unsigned long gart_buffers_offset;
329 drm_radeon_freelist_t *head;
330 drm_radeon_freelist_t *tail;
332 volatile u32 *scratch;
339 int freelist_timeouts;
342 int last_frame_reads;
343 int last_clear_reads;
352 unsigned int front_offset;
353 unsigned int front_pitch;
354 unsigned int back_offset;
355 unsigned int back_pitch;
358 unsigned int depth_offset;
359 unsigned int depth_pitch;
361 u32 front_pitch_offset;
362 u32 back_pitch_offset;
363 u32 depth_pitch_offset;
365 drm_radeon_depth_clear_t depth_clear;
367 unsigned long ring_offset;
368 unsigned long ring_rptr_offset;
369 unsigned long buffers_offset;
370 unsigned long gart_textures_offset;
372 drm_local_map_t *cp_ring;
373 drm_local_map_t *ring_rptr;
374 drm_local_map_t *gart_textures;
376 struct mem_block *gart_heap;
377 struct mem_block *fb_heap;
381 wait_queue_head_t swi_queue;
383 uint32_t irq_enable_reg;
385 uint32_t r500_disp_irq_reg;
387 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
388 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
393 unsigned int crtc_last_cnt;
394 unsigned int crtc2_last_cnt;
396 /* starting from here on, data is preserved accross an open */
397 uint32_t flags; /* see radeon_chip_flags */
398 unsigned long fb_aper_offset;
402 int mm_disabled; /* on OSes with no MM this will be 1*/
403 struct radeon_mm_info mm;
404 drm_local_map_t *mmio;
406 uint32_t chip_family;
408 unsigned long pcigart_offset;
409 unsigned int pcigart_offset_set;
410 struct drm_ati_pcigart_info gart_info;
412 struct radeon_mode_info mode_info;
414 uint8_t *bios; /* copy of the BIOS image */
416 uint16_t bios_header_start;
422 enum radeon_pll_errata pll_errata;
424 struct radeon_mm_obj **ib_objs;
426 uint64_t ib_alloc_bitmap; // TO DO replace with a real bitmap
427 struct drm_radeon_cs_priv cs;
428 } drm_radeon_private_t;
430 typedef struct drm_radeon_buf_priv {
432 } drm_radeon_buf_priv_t;
434 typedef struct drm_radeon_kcmd_buffer {
438 struct drm_clip_rect __user *boxes;
439 } drm_radeon_kcmd_buffer_t;
441 extern int radeon_no_wb;
442 extern int radeon_dynclks;
443 extern struct drm_ioctl_desc radeon_ioctls[];
444 extern int radeon_max_ioctl;
446 /* Check whether the given hardware address is inside the framebuffer or the
449 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
452 u32 fb_start = dev_priv->fb_location;
453 u32 fb_end = fb_start + dev_priv->fb_size - 1;
454 u32 gart_start = dev_priv->gart_vm_start;
455 u32 gart_end = gart_start + dev_priv->gart_size - 1;
457 return ((off >= fb_start && off <= fb_end) ||
458 (off >= gart_start && off <= gart_end));
462 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
463 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
464 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
465 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
466 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
467 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
468 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
469 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
470 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
471 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
473 extern void radeon_freelist_reset(struct drm_device * dev);
474 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
476 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
478 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
480 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
481 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
482 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
483 extern void radeon_mem_takedown(struct mem_block **heap);
484 extern void radeon_mem_release(struct drm_file *file_priv,
485 struct mem_block *heap);
488 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
489 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
491 extern void radeon_do_release(struct drm_device * dev);
492 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
493 extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
494 extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
495 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
496 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
497 extern int radeon_driver_irq_postinstall(struct drm_device * dev);
498 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
499 extern int radeon_vblank_crtc_get(struct drm_device *dev);
500 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
502 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
503 extern int radeon_driver_unload(struct drm_device *dev);
504 extern int radeon_driver_firstopen(struct drm_device *dev);
505 extern void radeon_driver_preclose(struct drm_device * dev,
506 struct drm_file *file_priv);
507 extern void radeon_driver_postclose(struct drm_device * dev,
508 struct drm_file *file_priv);
509 extern void radeon_driver_lastclose(struct drm_device * dev);
510 extern int radeon_driver_open(struct drm_device * dev,
511 struct drm_file * file_priv);
512 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
516 extern void r300_init_reg_flags(struct drm_device *dev);
518 extern int r300_do_cp_cmdbuf(struct drm_device *dev,
519 struct drm_file *file_priv,
520 drm_radeon_kcmd_buffer_t *cmdbuf);
522 /* Flags for stats.boxes
524 #define RADEON_BOX_DMA_IDLE 0x1
525 #define RADEON_BOX_RING_FULL 0x2
526 #define RADEON_BOX_FLIP 0x4
527 #define RADEON_BOX_WAIT_IDLE 0x8
528 #define RADEON_BOX_TEXTURE_LOAD 0x10
530 #define R600_CONFIG_MEMSIZE 0x5428
531 #define R600_CONFIG_APER_SIZE 0x5430
532 /* Register definitions, register access macros and drmAddMap constants
533 * for Radeon kernel driver.
536 #include "radeon_reg.h"
538 #define RADEON_AGP_COMMAND 0x0f60
539 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
540 # define RADEON_AGP_ENABLE (1<<8)
541 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
542 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
543 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
544 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
545 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
546 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
547 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
549 #define RADEON_BUS_CNTL 0x0030
550 # define RADEON_BUS_MASTER_DIS (1 << 6)
552 #define RADEON_CLOCK_CNTL_DATA 0x000c
553 # define RADEON_PLL_WR_EN (1 << 7)
554 #define RADEON_CLOCK_CNTL_INDEX 0x0008
555 #define RADEON_CONFIG_APER_SIZE 0x0108
556 #define RADEON_CONFIG_MEMSIZE 0x00f8
557 #define RADEON_CRTC_OFFSET 0x0224
558 #define RADEON_CRTC_OFFSET_CNTL 0x0228
559 # define RADEON_CRTC_TILE_EN (1 << 15)
560 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
561 #define RADEON_CRTC2_OFFSET 0x0324
562 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
564 #define RADEON_PCIE_INDEX 0x0030
565 #define RADEON_PCIE_DATA 0x0034
566 #define RADEON_PCIE_TX_GART_CNTL 0x10
567 # define RADEON_PCIE_TX_GART_EN (1 << 0)
568 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
569 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
570 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
571 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
572 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
573 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
574 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
575 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
576 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
577 #define RADEON_PCIE_TX_GART_BASE 0x13
578 #define RADEON_PCIE_TX_GART_START_LO 0x14
579 #define RADEON_PCIE_TX_GART_START_HI 0x15
580 #define RADEON_PCIE_TX_GART_END_LO 0x16
581 #define RADEON_PCIE_TX_GART_END_HI 0x17
583 #define RS480_NB_MC_INDEX 0x168
584 # define RS480_NB_MC_IND_WR_EN (1 << 8)
585 #define RS480_NB_MC_DATA 0x16c
587 #define RS690_MC_INDEX 0x78
588 # define RS690_MC_INDEX_MASK 0x1ff
589 # define RS690_MC_INDEX_WR_EN (1 << 9)
590 # define RS690_MC_INDEX_WR_ACK 0x7f
591 #define RS690_MC_DATA 0x7c
593 /* MC indirect registers */
594 #define RS480_MC_MISC_CNTL 0x18
595 # define RS480_DISABLE_GTW (1 << 1)
596 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
597 # define RS480_GART_INDEX_REG_EN (1 << 12)
598 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
599 #define RS480_K8_FB_LOCATION 0x1e
600 #define RS480_GART_FEATURE_ID 0x2b
601 # define RS480_HANG_EN (1 << 11)
602 # define RS480_TLB_ENABLE (1 << 18)
603 # define RS480_P2P_ENABLE (1 << 19)
604 # define RS480_GTW_LAC_EN (1 << 25)
605 # define RS480_2LEVEL_GART (0 << 30)
606 # define RS480_1LEVEL_GART (1 << 30)
607 # define RS480_PDC_EN (1 << 31)
608 #define RS480_GART_BASE 0x2c
609 #define RS480_GART_CACHE_CNTRL 0x2e
610 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
611 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
612 # define RS480_GART_EN (1 << 0)
613 # define RS480_VA_SIZE_32MB (0 << 1)
614 # define RS480_VA_SIZE_64MB (1 << 1)
615 # define RS480_VA_SIZE_128MB (2 << 1)
616 # define RS480_VA_SIZE_256MB (3 << 1)
617 # define RS480_VA_SIZE_512MB (4 << 1)
618 # define RS480_VA_SIZE_1GB (5 << 1)
619 # define RS480_VA_SIZE_2GB (6 << 1)
620 #define RS480_AGP_MODE_CNTL 0x39
621 # define RS480_POST_GART_Q_SIZE (1 << 18)
622 # define RS480_NONGART_SNOOP (1 << 19)
623 # define RS480_AGP_RD_BUF_SIZE (1 << 20)
624 # define RS480_REQ_TYPE_SNOOP_SHIFT 22
625 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
626 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
627 #define RS480_MC_MISC_UMA_CNTL 0x5f
628 #define RS480_MC_MCLK_CNTL 0x7a
629 #define RS480_MC_UMA_DUALCH_CNTL 0x86
631 #define RS690_MC_FB_LOCATION 0x100
632 #define RS690_MC_AGP_LOCATION 0x101
633 #define RS690_MC_AGP_BASE 0x102
634 #define RS690_MC_AGP_BASE_2 0x103
636 #define R520_MC_IND_INDEX 0x70
637 #define R520_MC_IND_WR_EN (1 << 24)
638 #define R520_MC_IND_DATA 0x74
640 #define RADEON_MPP_TB_CONFIG 0x01c0
641 #define RADEON_MEM_CNTL 0x0140
642 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
643 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
644 #define RS480_AGP_BASE_2 0x0164
645 #define RADEON_AGP_BASE 0x0170
647 /* pipe config regs */
648 #define R400_GB_PIPE_SELECT 0x402c
649 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
650 #define R500_SU_REG_DEST 0x42c8
651 #define R300_GB_TILE_CONFIG 0x4018
652 # define R300_ENABLE_TILING (1 << 0)
653 # define R300_PIPE_COUNT_RV350 (0 << 1)
654 # define R300_PIPE_COUNT_R300 (3 << 1)
655 # define R300_PIPE_COUNT_R420_3P (6 << 1)
656 # define R300_PIPE_COUNT_R420 (7 << 1)
657 # define R300_TILE_SIZE_8 (0 << 4)
658 # define R300_TILE_SIZE_16 (1 << 4)
659 # define R300_TILE_SIZE_32 (2 << 4)
660 # define R300_SUBPIXEL_1_12 (0 << 16)
661 # define R300_SUBPIXEL_1_16 (1 << 16)
662 #define R300_DST_PIPE_CONFIG 0x170c
663 # define R300_PIPE_AUTO_CONFIG (1 << 31)
664 #define R300_RB2D_DSTCACHE_MODE 0x3428
665 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
666 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
668 #define RADEON_RB3D_COLOROFFSET 0x1c40
669 #define RADEON_RB3D_COLORPITCH 0x1c48
671 #define RADEON_SRC_X_Y 0x1590
673 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
674 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
675 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
676 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
677 # define RADEON_GMC_BRUSH_NONE (15 << 4)
678 # define RADEON_GMC_DST_16BPP (4 << 8)
679 # define RADEON_GMC_DST_24BPP (5 << 8)
680 # define RADEON_GMC_DST_32BPP (6 << 8)
681 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
682 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
683 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
684 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
685 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
686 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
687 # define RADEON_ROP3_S 0x00cc0000
688 # define RADEON_ROP3_P 0x00f00000
689 #define RADEON_DP_WRITE_MASK 0x16cc
690 #define RADEON_SRC_PITCH_OFFSET 0x1428
691 #define RADEON_DST_PITCH_OFFSET 0x142c
692 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
693 # define RADEON_DST_TILE_LINEAR (0 << 30)
694 # define RADEON_DST_TILE_MACRO (1 << 30)
695 # define RADEON_DST_TILE_MICRO (2 << 30)
696 # define RADEON_DST_TILE_BOTH (3 << 30)
698 #define RADEON_SCRATCH_REG0 0x15e0
699 #define RADEON_SCRATCH_REG1 0x15e4
700 #define RADEON_SCRATCH_REG2 0x15e8
701 #define RADEON_SCRATCH_REG3 0x15ec
702 #define RADEON_SCRATCH_REG4 0x15f0
703 #define RADEON_SCRATCH_REG5 0x15f4
704 #define RADEON_SCRATCH_REG6 0x15f8
705 #define RADEON_SCRATCH_UMSK 0x0770
706 #define RADEON_SCRATCH_ADDR 0x0774
708 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
710 #define GET_SCRATCH( x ) (dev_priv->writeback_works ? \
711 (dev_priv->mm.ring_read.bo ? \
712 readl(dev_priv->mm.ring_read.kmap.virtual + RADEON_SCRATCHOFF(0)) : \
713 DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x))) : \
714 RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x)))
716 #define RADEON_CRTC_CRNT_FRAME 0x0214
717 #define RADEON_CRTC2_CRNT_FRAME 0x0314
719 #define RADEON_CRTC_STATUS 0x005c
720 #define RADEON_CRTC2_STATUS 0x03fc
722 #define RADEON_GEN_INT_CNTL 0x0040
723 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
724 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
725 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
726 # define RADEON_SW_INT_ENABLE (1 << 25)
728 #define RADEON_GEN_INT_STATUS 0x0044
729 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
730 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
731 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
732 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
733 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
734 # define RADEON_SW_INT_TEST (1 << 25)
735 # define RADEON_SW_INT_TEST_ACK (1 << 25)
736 # define RADEON_SW_INT_FIRE (1 << 26)
737 # define R500_DISPLAY_INT_STATUS (1 << 0)
739 #define RADEON_HOST_PATH_CNTL 0x0130
740 # define RADEON_HDP_SOFT_RESET (1 << 26)
741 # define RADEON_HDP_APER_CNTL (1 << 23)
743 #define RADEON_NB_TOM 0x15c
745 #define RADEON_ISYNC_CNTL 0x1724
746 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
747 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
748 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
749 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
750 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
751 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
753 #define RADEON_RBBM_GUICNTL 0x172c
754 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
755 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
756 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
757 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
759 #define RADEON_MC_AGP_LOCATION 0x014c
760 #define RADEON_MC_FB_LOCATION 0x0148
761 #define RADEON_MCLK_CNTL 0x0012
762 # define RADEON_FORCEON_MCLKA (1 << 16)
763 # define RADEON_FORCEON_MCLKB (1 << 17)
764 # define RADEON_FORCEON_YCLKA (1 << 18)
765 # define RADEON_FORCEON_YCLKB (1 << 19)
766 # define RADEON_FORCEON_MC (1 << 20)
767 # define RADEON_FORCEON_AIC (1 << 21)
769 #define RADEON_PP_BORDER_COLOR_0 0x1d40
770 #define RADEON_PP_BORDER_COLOR_1 0x1d44
771 #define RADEON_PP_BORDER_COLOR_2 0x1d48
772 #define RADEON_PP_CNTL 0x1c38
773 # define RADEON_SCISSOR_ENABLE (1 << 1)
774 #define RADEON_PP_LUM_MATRIX 0x1d00
775 #define RADEON_PP_MISC 0x1c14
776 #define RADEON_PP_ROT_MATRIX_0 0x1d58
777 #define RADEON_PP_TXFILTER_0 0x1c54
778 #define RADEON_PP_TXOFFSET_0 0x1c5c
779 #define RADEON_PP_TXFILTER_1 0x1c6c
780 #define RADEON_PP_TXFILTER_2 0x1c84
782 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
783 # define RADEON_RB2D_DC_FLUSH (3 << 0)
784 # define RADEON_RB2D_DC_FREE (3 << 2)
785 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
786 # define RADEON_RB2D_DC_BUSY (1 << 31)
787 #define RADEON_RB3D_CNTL 0x1c3c
788 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
789 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
790 # define RADEON_DITHER_ENABLE (1 << 2)
791 # define RADEON_ROUND_ENABLE (1 << 3)
792 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
793 # define RADEON_DITHER_INIT (1 << 5)
794 # define RADEON_ROP_ENABLE (1 << 6)
795 # define RADEON_STENCIL_ENABLE (1 << 7)
796 # define RADEON_Z_ENABLE (1 << 8)
797 # define RADEON_ZBLOCK16 (1 << 15)
798 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
799 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
800 #define RADEON_RB3D_DEPTHPITCH 0x1c28
801 #define RADEON_RB3D_PLANEMASK 0x1d84
802 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
803 #define RADEON_RB3D_ZCACHE_MODE 0x3250
804 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
805 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
806 # define RADEON_RB3D_ZC_FREE (1 << 2)
807 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
808 # define RADEON_RB3D_ZC_BUSY (1 << 31)
809 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
810 # define R300_ZC_FLUSH (1 << 0)
811 # define R300_ZC_FREE (1 << 1)
812 # define R300_ZC_FLUSH_ALL 0x3
813 # define R300_ZC_BUSY (1 << 31)
814 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
815 # define R300_RB3D_DC_FINISH (1 << 4)
816 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
817 # define RADEON_Z_TEST_MASK (7 << 4)
818 # define RADEON_Z_TEST_ALWAYS (7 << 4)
819 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
820 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
821 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
822 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
823 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
824 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
825 # define RADEON_FORCE_Z_DIRTY (1 << 29)
826 # define RADEON_Z_WRITE_ENABLE (1 << 30)
827 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
828 #define RADEON_RBBM_SOFT_RESET 0x00f0
829 # define RADEON_SOFT_RESET_CP (1 << 0)
830 # define RADEON_SOFT_RESET_HI (1 << 1)
831 # define RADEON_SOFT_RESET_SE (1 << 2)
832 # define RADEON_SOFT_RESET_RE (1 << 3)
833 # define RADEON_SOFT_RESET_PP (1 << 4)
834 # define RADEON_SOFT_RESET_E2 (1 << 5)
835 # define RADEON_SOFT_RESET_RB (1 << 6)
836 # define RADEON_SOFT_RESET_HDP (1 << 7)
838 * 6:0 Available slots in the FIFO
839 * 8 Host Interface active
840 * 9 CP request active
841 * 10 FIFO request active
842 * 11 Host Interface retry active
844 * 13 FIFO retry active
845 * 14 FIFO pipeline busy
846 * 15 Event engine busy
847 * 16 CP command stream busy
849 * 18 2D portion of render backend busy
850 * 20 3D setup engine busy
852 * 27 CBA 2D engine busy
853 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
854 * command stream queue not empty or Ring Buffer not empty
856 #define RADEON_RBBM_STATUS 0x0e40
857 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
858 /* #define RADEON_RBBM_STATUS 0x1740 */
859 /* bits 6:0 are dword slots available in the cmd fifo */
860 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
861 # define RADEON_HIRQ_ON_RBB (1 << 8)
862 # define RADEON_CPRQ_ON_RBB (1 << 9)
863 # define RADEON_CFRQ_ON_RBB (1 << 10)
864 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
865 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
866 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
867 # define RADEON_PIPE_BUSY (1 << 14)
868 # define RADEON_ENG_EV_BUSY (1 << 15)
869 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
870 # define RADEON_E2_BUSY (1 << 17)
871 # define RADEON_RB2D_BUSY (1 << 18)
872 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
873 # define RADEON_VAP_BUSY (1 << 20)
874 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
875 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
876 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
877 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
878 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
879 # define RADEON_GA_BUSY (1 << 26)
880 # define RADEON_CBA2D_BUSY (1 << 27)
881 # define RADEON_RBBM_ACTIVE (1 << 31)
882 #define RADEON_RE_LINE_PATTERN 0x1cd0
883 #define RADEON_RE_MISC 0x26c4
884 #define RADEON_RE_TOP_LEFT 0x26c0
885 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
886 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
887 #define RADEON_RE_STIPPLE_DATA 0x1ccc
889 #define RADEON_SCISSOR_TL_0 0x1cd8
890 #define RADEON_SCISSOR_BR_0 0x1cdc
891 #define RADEON_SCISSOR_TL_1 0x1ce0
892 #define RADEON_SCISSOR_BR_1 0x1ce4
893 #define RADEON_SCISSOR_TL_2 0x1ce8
894 #define RADEON_SCISSOR_BR_2 0x1cec
895 #define RADEON_SE_COORD_FMT 0x1c50
896 #define RADEON_SE_CNTL 0x1c4c
897 # define RADEON_FFACE_CULL_CW (0 << 0)
898 # define RADEON_BFACE_SOLID (3 << 1)
899 # define RADEON_FFACE_SOLID (3 << 3)
900 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
901 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
902 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
903 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
904 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
905 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
906 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
907 # define RADEON_FOG_SHADE_FLAT (1 << 14)
908 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
909 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
910 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
911 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
912 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
913 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
914 #define RADEON_SE_CNTL_STATUS 0x2140
915 #define RADEON_SE_LINE_WIDTH 0x1db8
916 #define RADEON_SE_VPORT_XSCALE 0x1d98
917 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
918 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
919 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
920 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
921 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
922 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
923 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
924 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
925 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
926 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
927 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
928 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
929 #define RADEON_SURFACE_CNTL 0x0b00
930 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
931 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
932 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
933 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
934 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
935 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
936 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
937 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
938 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
939 #define RADEON_SURFACE0_INFO 0x0b0c
940 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
941 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
942 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
943 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
944 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
945 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
946 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
947 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
948 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
949 #define RADEON_SURFACE1_INFO 0x0b1c
950 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
951 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
952 #define RADEON_SURFACE2_INFO 0x0b2c
953 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
954 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
955 #define RADEON_SURFACE3_INFO 0x0b3c
956 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
957 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
958 #define RADEON_SURFACE4_INFO 0x0b4c
959 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
960 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
961 #define RADEON_SURFACE5_INFO 0x0b5c
962 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
963 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
964 #define RADEON_SURFACE6_INFO 0x0b6c
965 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
966 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
967 #define RADEON_SURFACE7_INFO 0x0b7c
968 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
969 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
970 #define RADEON_SW_SEMAPHORE 0x013c
972 #define RADEON_WAIT_UNTIL 0x1720
973 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
974 # define RADEON_WAIT_2D_IDLE (1 << 14)
975 # define RADEON_WAIT_3D_IDLE (1 << 15)
976 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
977 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
978 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
980 #define RADEON_RB3D_ZMASKOFFSET 0x3234
981 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
982 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
983 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
986 #define RADEON_CP_ME_RAM_ADDR 0x07d4
987 #define RADEON_CP_ME_RAM_RADDR 0x07d8
988 #define RADEON_CP_ME_RAM_DATAH 0x07dc
989 #define RADEON_CP_ME_RAM_DATAL 0x07e0
991 #define RADEON_CP_RB_BASE 0x0700
992 #define RADEON_CP_RB_CNTL 0x0704
993 # define RADEON_BUF_SWAP_32BIT (2 << 16)
994 # define RADEON_RB_NO_UPDATE (1 << 27)
995 #define RADEON_CP_RB_RPTR_ADDR 0x070c
996 #define RADEON_CP_RB_RPTR 0x0710
997 #define RADEON_CP_RB_WPTR 0x0714
999 #define RADEON_CP_RB_WPTR_DELAY 0x0718
1000 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
1001 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
1003 #define RADEON_CP_IB_BASE 0x0738
1005 #define RADEON_CP_CSQ_CNTL 0x0740
1006 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
1007 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
1008 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
1009 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
1010 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
1011 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
1012 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
1014 #define RADEON_AIC_CNTL 0x01d0
1015 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
1016 #define RADEON_AIC_STAT 0x01d4
1017 #define RADEON_AIC_PT_BASE 0x01d8
1018 #define RADEON_AIC_LO_ADDR 0x01dc
1019 #define RADEON_AIC_HI_ADDR 0x01e0
1020 #define RADEON_AIC_TLB_ADDR 0x01e4
1021 #define RADEON_AIC_TLB_DATA 0x01e8
1023 /* CP command packets */
1024 #define RADEON_CP_PACKET0 0x00000000
1025 # define RADEON_ONE_REG_WR (1 << 15)
1026 #define RADEON_CP_PACKET1 0x40000000
1027 #define RADEON_CP_PACKET2 0x80000000
1028 #define RADEON_CP_PACKET3 0xC0000000
1029 # define RADEON_CP_NOP 0x00001000
1030 # define RADEON_CP_NEXT_CHAR 0x00001900
1031 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
1032 # define RADEON_CP_SET_SCISSORS 0x00001E00
1033 /* GEN_INDX_PRIM is unsupported starting with R300 */
1034 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1035 # define RADEON_WAIT_FOR_IDLE 0x00002600
1036 # define RADEON_3D_DRAW_VBUF 0x00002800
1037 # define RADEON_3D_DRAW_IMMD 0x00002900
1038 # define RADEON_3D_DRAW_INDX 0x00002A00
1039 # define RADEON_CP_LOAD_PALETTE 0x00002C00
1040 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
1041 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1042 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1043 # define RADEON_3D_CLEAR_ZMASK 0x00003200
1044 # define RADEON_CP_INDX_BUFFER 0x00003300
1045 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1046 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1047 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1048 # define RADEON_3D_CLEAR_HIZ 0x00003700
1049 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1050 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1051 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
1052 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1053 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1055 #define RADEON_CP_PACKET_MASK 0xC0000000
1056 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1057 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1058 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1059 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1061 #define RADEON_VTX_Z_PRESENT (1 << 31)
1062 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1064 #define RADEON_PRIM_TYPE_NONE (0 << 0)
1065 #define RADEON_PRIM_TYPE_POINT (1 << 0)
1066 #define RADEON_PRIM_TYPE_LINE (2 << 0)
1067 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1068 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1069 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1070 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1071 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1072 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1073 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1074 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1075 #define RADEON_PRIM_TYPE_MASK 0xf
1076 #define RADEON_PRIM_WALK_IND (1 << 4)
1077 #define RADEON_PRIM_WALK_LIST (2 << 4)
1078 #define RADEON_PRIM_WALK_RING (3 << 4)
1079 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
1080 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
1081 #define RADEON_MAOS_ENABLE (1 << 7)
1082 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
1083 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1084 #define RADEON_NUM_VERTICES_SHIFT 16
1086 #define RADEON_COLOR_FORMAT_CI8 2
1088 #define R200_PP_TXCBLEND_0 0x2f00
1089 #define R200_PP_TXCBLEND_1 0x2f10
1090 #define R200_PP_TXCBLEND_2 0x2f20
1091 #define R200_PP_TXCBLEND_3 0x2f30
1092 #define R200_PP_TXCBLEND_4 0x2f40
1093 #define R200_PP_TXCBLEND_5 0x2f50
1094 #define R200_PP_TXCBLEND_6 0x2f60
1095 #define R200_PP_TXCBLEND_7 0x2f70
1096 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1097 #define R200_PP_TFACTOR_0 0x2ee0
1098 #define R200_SE_VTX_FMT_0 0x2088
1099 #define R200_SE_VAP_CNTL 0x2080
1100 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
1101 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1102 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1103 #define R200_PP_TXFILTER_5 0x2ca0
1104 #define R200_PP_TXFILTER_4 0x2c80
1105 #define R200_PP_TXFILTER_3 0x2c60
1106 #define R200_PP_TXFILTER_2 0x2c40
1107 #define R200_PP_TXFILTER_1 0x2c20
1108 #define R200_PP_TXFILTER_0 0x2c00
1109 #define R200_PP_TXOFFSET_5 0x2d78
1110 #define R200_PP_TXOFFSET_4 0x2d60
1111 #define R200_PP_TXOFFSET_3 0x2d48
1112 #define R200_PP_TXOFFSET_2 0x2d30
1113 #define R200_PP_TXOFFSET_1 0x2d18
1114 #define R200_PP_TXOFFSET_0 0x2d00
1116 #define R200_PP_CUBIC_FACES_0 0x2c18
1117 #define R200_PP_CUBIC_FACES_1 0x2c38
1118 #define R200_PP_CUBIC_FACES_2 0x2c58
1119 #define R200_PP_CUBIC_FACES_3 0x2c78
1120 #define R200_PP_CUBIC_FACES_4 0x2c98
1121 #define R200_PP_CUBIC_FACES_5 0x2cb8
1122 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1123 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1124 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1125 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1126 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1127 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1128 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1129 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1130 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1131 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1132 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1133 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1134 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1135 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1136 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1137 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1138 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1139 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1140 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1141 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1142 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1143 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1144 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1145 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1146 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1147 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1148 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1149 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1150 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1151 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1153 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1154 #define R200_SE_VTE_CNTL 0x20b0
1155 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1156 #define R200_PP_TAM_DEBUG3 0x2d9c
1157 #define R200_PP_CNTL_X 0x2cc4
1158 #define R200_SE_VAP_CNTL_STATUS 0x2140
1159 #define R200_RE_SCISSOR_TL_0 0x1cd8
1160 #define R200_RE_SCISSOR_TL_1 0x1ce0
1161 #define R200_RE_SCISSOR_TL_2 0x1ce8
1162 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1163 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1164 #define R200_SE_VTX_STATE_CNTL 0x2180
1165 #define R200_RE_POINTSIZE 0x2648
1166 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1168 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1169 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1170 #define RADEON_PP_TEX_SIZE_2 0x1d14
1172 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1173 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1174 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1175 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1176 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1177 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1179 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1181 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1182 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1183 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1184 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1185 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1186 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1187 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1188 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1189 #define R200_3D_DRAW_IMMD_2 0xC0003500
1190 #define R200_SE_VTX_FMT_1 0x208c
1191 #define R200_RE_CNTL 0x1c50
1193 #define R200_RB3D_BLENDCOLOR 0x3218
1195 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1197 #define R200_PP_TRI_PERF 0x2cf8
1199 #define R200_PP_AFS_0 0x2f80
1200 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1202 #define R200_VAP_PVS_CNTL_1 0x22D0
1204 /* MPEG settings from VHA code */
1205 #define RADEON_VHA_SETTO16_1 0x2694
1206 #define RADEON_VHA_SETTO16_2 0x2680
1207 #define RADEON_VHA_SETTO0_1 0x1840
1208 #define RADEON_VHA_FB_OFFSET 0x19e4
1209 #define RADEON_VHA_SETTO1AND70S 0x19d8
1210 #define RADEON_VHA_DST_PITCH 0x1408
1212 // set as reference header
1213 #define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840
1214 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844
1215 #define RADEON_VHA_BACKFRAME0_OFF_U 0x1848
1216 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c
1217 #define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850
1218 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854
1219 #define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858
1220 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c
1221 #define RADEON_VHA_FORWFRAME0_OFF_U 0x1860
1222 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864
1223 #define RADEON_VHA_FORWFRAME0_OFF_V 0x1868
1224 #define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880
1225 #define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884
1226 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888
1227 #define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c
1228 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890
1229 #define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894
1230 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898
1232 #define R500_D1CRTC_STATUS 0x609c
1233 #define R500_D2CRTC_STATUS 0x689c
1234 #define R500_CRTC_V_BLANK (1<<0)
1236 #define R500_D1CRTC_FRAME_COUNT 0x60a4
1237 #define R500_D2CRTC_FRAME_COUNT 0x68a4
1239 #define R500_D1MODE_V_COUNTER 0x6530
1240 #define R500_D2MODE_V_COUNTER 0x6d30
1242 #define R500_D1MODE_VBLANK_STATUS 0x6534
1243 #define R500_D2MODE_VBLANK_STATUS 0x6d34
1244 #define R500_VBLANK_OCCURED (1<<0)
1245 #define R500_VBLANK_ACK (1<<4)
1246 #define R500_VBLANK_STAT (1<<12)
1247 #define R500_VBLANK_INT (1<<16)
1249 #define R500_DxMODE_INT_MASK 0x6540
1250 #define R500_D1MODE_INT_MASK (1<<0)
1251 #define R500_D2MODE_INT_MASK (1<<8)
1253 #define R500_DISP_INTERRUPT_STATUS 0x7edc
1254 #define R500_D1_VBLANK_INTERRUPT (1 << 4)
1255 #define R500_D2_VBLANK_INTERRUPT (1 << 5)
1258 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1260 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1261 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1262 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1263 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1264 #define RADEON_LAST_DISPATCH 1
1266 #define RADEON_MAX_VB_AGE 0x7fffffff
1267 #define RADEON_MAX_VB_VERTS (0xffff)
1269 #define RADEON_RING_HIGH_MARK 128
1271 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1272 #define RADEON_DEFAULT_RING_SIZE (1024*1024)
1273 #define RADEON_DEFAULT_CP_TIMEOUT 100000 /* usecs */
1275 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1276 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1277 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1278 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1280 extern int RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr);
1281 extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data);
1283 #define RADEON_WRITE_P(reg, val, mask) \
1285 uint32_t tmp = RADEON_READ(reg); \
1287 tmp |= ((val) & ~(mask)); \
1288 RADEON_WRITE(reg, tmp); \
1291 #define RADEON_WRITE_PLL_P(dev_priv, addr, val, mask) \
1293 uint32_t tmp_ = RADEON_READ_PLL(dev_priv, addr); \
1295 tmp_ |= ((val) & ~(mask)); \
1296 RADEON_WRITE_PLL(dev_priv, addr, tmp_); \
1301 #define RADEON_WRITE_PCIE(addr, val) \
1303 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1305 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1308 #define R500_WRITE_MCIND(addr, val) \
1310 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1311 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1312 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1315 #define RS480_WRITE_MCIND(addr, val) \
1317 RADEON_WRITE(RS480_NB_MC_INDEX, \
1318 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1319 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1320 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1323 #define RS690_WRITE_MCIND(addr, val) \
1325 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1326 RADEON_WRITE(RS690_MC_DATA, val); \
1327 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1330 #define IGP_WRITE_MCIND(addr, val) \
1332 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
1333 RS690_WRITE_MCIND(addr, val); \
1335 RS480_WRITE_MCIND(addr, val); \
1338 #define CP_PACKET0( reg, n ) \
1339 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1340 #define CP_PACKET0_TABLE( reg, n ) \
1341 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1342 #define CP_PACKET1( reg0, reg1 ) \
1343 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1344 #define CP_PACKET2() \
1346 #define CP_PACKET3( pkt, n ) \
1347 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1349 /* ================================================================
1350 * Engine control helper macros
1353 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1354 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1355 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1356 RADEON_WAIT_HOST_IDLECLEAN) ); \
1359 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1360 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1361 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1362 RADEON_WAIT_HOST_IDLECLEAN) ); \
1365 #define RADEON_WAIT_UNTIL_IDLE() do { \
1366 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1367 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1368 RADEON_WAIT_3D_IDLECLEAN | \
1369 RADEON_WAIT_HOST_IDLECLEAN) ); \
1372 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1373 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1374 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1377 #define RADEON_FLUSH_CACHE() do { \
1378 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1379 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1380 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1382 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1383 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1387 #define RADEON_PURGE_CACHE() do { \
1388 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1389 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1390 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1392 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1393 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1397 #define RADEON_FLUSH_ZCACHE() do { \
1398 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1399 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1400 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1402 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1403 OUT_RING(R300_ZC_FLUSH); \
1407 #define RADEON_PURGE_ZCACHE() do { \
1408 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1409 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1410 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
1412 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); \
1413 OUT_RING(R300_ZC_FLUSH_ALL); \
1417 /* ================================================================
1418 * Misc helper macros
1421 /* Perfbox functionality only.
1423 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1425 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1426 u32 head = GET_RING_HEAD( dev_priv ); \
1427 if (head == dev_priv->ring.tail) \
1428 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1432 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1434 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
1435 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
1436 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1437 int __ret = radeon_do_cp_idle( dev_priv ); \
1438 if ( __ret ) return __ret; \
1439 sarea_priv->last_dispatch = 0; \
1440 radeon_freelist_reset( dev ); \
1444 #define RADEON_DISPATCH_AGE( age ) do { \
1445 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1449 #define RADEON_FRAME_AGE( age ) do { \
1450 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1454 #define RADEON_CLEAR_AGE( age ) do { \
1455 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1459 /* ================================================================
1463 #define RADEON_VERBOSE 0
1465 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1467 #define BEGIN_RING( n ) do { \
1468 if ( RADEON_VERBOSE ) { \
1469 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1471 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1473 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1475 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1476 ring = dev_priv->ring.start; \
1477 write = dev_priv->ring.tail; \
1478 mask = dev_priv->ring.tail_mask; \
1481 #define ADVANCE_RING() do { \
1482 if ( RADEON_VERBOSE ) { \
1483 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1484 write, dev_priv->ring.tail ); \
1486 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1488 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1489 ((dev_priv->ring.tail + _nr) & mask), \
1492 dev_priv->ring.tail = write; \
1495 #define COMMIT_RING() do { \
1496 /* Flush writes to ring */ \
1497 DRM_MEMORYBARRIER(); \
1498 GET_RING_HEAD( dev_priv ); \
1499 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1500 /* read from PCI bus to ensure correct posting */ \
1501 RADEON_READ( RADEON_CP_RB_RPTR ); \
1504 #define OUT_RING( x ) do { \
1505 if ( RADEON_VERBOSE ) { \
1506 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1507 (unsigned int)(x), write ); \
1509 ring[write++] = (x); \
1513 #define OUT_RING_REG( reg, val ) do { \
1514 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1518 #define OUT_RING_TABLE( tab, sz ) do { \
1520 int *_tab = (int *)(tab); \
1522 if (write + _size > mask) { \
1523 int _i = (mask+1) - write; \
1526 *(int *)(ring + write) = *_tab++; \
1533 while (_size > 0) { \
1534 *(ring + write) = *_tab++; \
1541 /* radeon GEM->TTM munger */
1542 struct drm_radeon_gem_object {
1544 struct drm_buffer_object *bo;
1545 struct drm_fence_object *fence;
1546 struct drm_gem_object *obj;
1550 extern int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1551 struct drm_file *file_priv);
1553 extern int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1554 struct drm_file *file_priv);
1556 extern int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1557 struct drm_file *file_priv);
1559 extern int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1560 struct drm_file *file_priv);
1561 extern int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1562 struct drm_file *file_priv);
1564 extern void radeon_fence_handler(struct drm_device *dev);
1565 extern int radeon_fence_emit_sequence(struct drm_device *dev, uint32_t class,
1566 uint32_t flags, uint32_t *sequence,
1567 uint32_t *native_type);
1568 extern void radeon_poke_flush(struct drm_device *dev, uint32_t class);
1569 extern int radeon_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
1571 /* radeon_buffer.c */
1572 extern struct drm_ttm_backend *radeon_create_ttm_backend_entry(struct drm_device *dev);
1573 extern int radeon_fence_types(struct drm_buffer_object *bo, uint32_t *class, uint32_t *type);
1574 extern int radeon_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
1575 extern int radeon_init_mem_type(struct drm_device * dev, uint32_t type,
1576 struct drm_mem_type_manager * man);
1577 extern int radeon_move(struct drm_buffer_object * bo,
1578 int evict, int no_wait, struct drm_bo_mem_reg * new_mem);
1580 extern void radeon_gart_flush(struct drm_device *dev);
1581 extern uint64_t radeon_evict_flags(struct drm_buffer_object *bo);
1583 #define BREADCRUMB_BITS 31
1584 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
1586 /* Breadcrumb - swi irq */
1587 #define READ_BREADCRUMB(dev_priv) RADEON_READ(RADEON_LAST_SWI_REG)
1589 static inline int radeon_update_breadcrumb(struct drm_device *dev)
1591 struct drm_radeon_private *dev_priv = dev->dev_private;
1592 struct drm_radeon_master_private *master_priv;
1594 ++dev_priv->counter;
1595 if (dev_priv->counter > BREADCRUMB_MASK)
1596 dev_priv->counter = 1;
1598 if (dev->primary->master) {
1599 master_priv = dev->primary->master->driver_priv;
1601 if (master_priv->sarea_priv)
1602 master_priv->sarea_priv->last_fence = dev_priv->counter;
1604 return dev_priv->counter;
1607 #define radeon_is_avivo(dev_priv) ((dev_priv->chip_family >= CHIP_RS600))
1609 #define radeon_is_dce3(dev_priv) ((dev_priv->chip_family >= CHIP_RV620))
1611 #define radeon_is_rv100(dev_priv) ((dev_priv->chip_family == CHIP_RV100) || \
1612 (dev_priv->chip_family == CHIP_RV200) || \
1613 (dev_priv->chip_family == CHIP_RS100) || \
1614 (dev_priv->chip_family == CHIP_RS200) || \
1615 (dev_priv->chip_family == CHIP_RV250) || \
1616 (dev_priv->chip_family == CHIP_RV280) || \
1617 (dev_priv->chip_family == CHIP_RS300))
1619 #define radeon_is_r300(dev_priv) ((dev_priv->chip_family == CHIP_R300) || \
1620 (dev_priv->chip_family == CHIP_RV350) || \
1621 (dev_priv->chip_family == CHIP_R350) || \
1622 (dev_priv->chip_family == CHIP_RV380) || \
1623 (dev_priv->chip_family == CHIP_R420) || \
1624 (dev_priv->chip_family == CHIP_RV410) || \
1625 (dev_priv->chip_family == CHIP_RS400) || \
1626 (dev_priv->chip_family == CHIP_RS480))
1628 #define radeon_bios8(dev_priv, v) (dev_priv->bios[v])
1629 #define radeon_bios16(dev_priv, v) (dev_priv->bios[v] | (dev_priv->bios[(v) + 1] << 8))
1630 #define radeon_bios32(dev_priv, v) ((dev_priv->bios[v]) | \
1631 (dev_priv->bios[(v) + 1] << 8) | \
1632 (dev_priv->bios[(v) + 2] << 16) | \
1633 (dev_priv->bios[(v) + 3] << 24))
1635 extern void radeon_pll_errata_after_index(struct drm_radeon_private *dev_priv);
1636 extern int radeon_emit_irq(struct drm_device * dev);
1638 extern void radeon_gem_free_object(struct drm_gem_object *obj);
1639 extern int radeon_gem_init_object(struct drm_gem_object *obj);
1640 extern int radeon_gem_mm_init(struct drm_device *dev);
1641 extern void radeon_gem_mm_fini(struct drm_device *dev);
1642 extern int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1643 struct drm_file *file_priv);
1644 extern int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1645 struct drm_file *file_priv);
1646 int radeon_gem_object_pin(struct drm_gem_object *obj,
1647 uint32_t alignment);
1648 int radeon_gem_indirect_ioctl(struct drm_device *dev, void *data,
1649 struct drm_file *file_priv);
1650 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1651 struct drm_file *file_priv);
1652 struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment,
1653 int initial_domain);
1654 int radeon_modeset_init(struct drm_device *dev);
1655 void radeon_modeset_cleanup(struct drm_device *dev);
1656 extern u32 radeon_read_mc_reg(drm_radeon_private_t *dev_priv, int addr);
1657 extern void radeon_write_mc_reg(drm_radeon_private_t *dev_priv, u32 addr, u32 val);
1659 extern void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on);
1660 #define RADEONFB_CONN_LIMIT 4
1662 extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
1663 extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
1664 extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *master);
1665 extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
1666 extern int radeon_cs_init(struct drm_device *dev);
1667 void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master);
1670 #define MARK_CHECK_OFFSET 2
1671 #define MARK_CHECK_SCISSOR 3
1673 extern int r300_check_range(unsigned reg, int count);
1674 extern int r300_get_reg_flags(unsigned reg);
1675 #endif /* __RADEON_DRV_H__ */