2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
3 * Copyright 2007 Jérôme Glisse
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
25 * Jérôme Glisse <glisse@freedesktop.org>
27 #ifndef __RADEON_MS_COMBIOS_H__
28 #define __RADEON_MS_COMBIOS_H__
32 #define ROM_HEADER 0x48
36 uint8_t ucTypeDefinition;
37 uint8_t ucExtFunctionCode;
40 uint8_t ucBiosMajorRev;
41 uint8_t ucBiosMinorRev;
42 uint16_t usStructureSize;
43 uint16_t usPointerToSmi;
44 uint16_t usPointerToPmid;
45 uint16_t usPointerToInitTable;
46 uint16_t usPointerToCrcChecksumBlock;
47 uint16_t usPointerToConfigFilename;
48 uint16_t usPointerToLogonMessage;
49 uint16_t usPointerToMiscInfo;
50 uint16_t usPciBusDevInitCode;
51 uint16_t usBiosRuntimeSegmentAddress;
52 uint16_t usIoBaseAddress;
53 uint16_t usSubsystemVendorID;
54 uint16_t usSubsystemID;
55 uint16_t usPostVendorID;
56 uint16_t usInt10Offset;
57 uint16_t usInt10Segment;
58 uint16_t usMonitorInfo;
59 uint16_t usPointerToConfigBlock;
60 uint16_t usPointerToDacDelayInfo;
61 uint16_t usPointerToCapDataStruct;
62 uint16_t usPointerToInternalCrtTables;
63 uint16_t usPointerToPllInfoBlock;
64 uint16_t usPointerToTVInfoTable;
65 uint16_t usPointerToDFPInfoTable;
66 uint16_t usPointerToHWConfigTable;
67 uint16_t usPointerToMMConfigTable;
68 uint32_t ulTVStdPatchTableSignature;
69 uint16_t usPointerToTVStdPatchTable;
70 uint16_t usPointerToPanelInfoTable;
71 uint16_t usPointerToAsicInfoTable;
72 uint16_t usPointerToAuroraInfoTable;
73 uint16_t usPointerToPllInitTable;
74 uint16_t usPointerToMemoryConfigTable;
75 uint16_t usPointerToSaveMaskTable;
76 uint16_t usPointerHardCodedEdid;
77 uint16_t usPointerToExtendedInitTable1;
78 uint16_t usPointerToExtendedInitTable2;
79 uint16_t usPointerToDynamicClkTable;
80 uint16_t usPointerToReservedMemoryTable;
81 uint16_t usPointerToBridgetInitTable;
82 uint16_t usPointerToExtTMDSInitTable;
83 uint16_t usPointerToMemClkInfoTable;
84 uint16_t usPointerToExtDACTable;
85 uint16_t usPointerToMiscInfoTable;
88 struct combios_pll_block
91 uint8_t ucPLLBiosVersion;
93 uint8_t ucStructureSize;
94 /* Dot clock entry used for accelerated modes */
95 uint8_t ucDotClockEntry;
96 /* Dot clock entry used for extended VGA modes */
97 uint8_t ucDotClockEntryVga;
98 /* Offset into internal clock table used for by VGA parameter table */
99 uint16_t usPointerToInternalClock;
100 /* Offset into actual programmed frequency table at POST */
101 uint16_t usPointerToFreqTable;
102 /* XCLK setting, (memory clock in 10 KHz units) */
103 uint16_t usXclkSetting;
104 /* MCLK setting, (engine clock in 10 KHz units) */
105 uint16_t usMclkSetting;
106 /* Number of PLL information block to follow, currently value is 3 */
107 uint8_t ucPllInfoBlockNumber;
108 /* Size of each PLL information block */
109 uint8_t ucPllInfoBlockSize;
110 /* Reference frequency of the dot clock */
111 uint16_t usDotClockRefFreq;
112 /* Reference Divider of the dot clock */
113 uint16_t usDotClockRefDiv;
114 /* Min Frequency supported before post divider for the dot clock */
115 uint32_t ulDotClockMinFreq;
116 /* Max Frequency can be supported for the dot clock */
117 uint32_t ulDotClockMaxFreq;
118 /* Reference frequency of the MCLK, engine clock */
119 uint16_t usMclkRefFreq;
120 /* Reference Divider of the MCLK, engine clock */
121 uint16_t usMclkRefDiv;
122 /* Min Frequency supported before post divider for MCLK, engine clock */
123 uint32_t ulMclkMinFreq;
124 /* Max Frequency can be supported for the MCLK, engine clock */
125 uint32_t ulMclkMaxFreq;
126 /* Reference frequency of the XCLK, memory clock */
127 uint16_t usXclkRefFreq;
128 /* Reference Divider of the XCLK, memory clock */
129 uint16_t usXclkRefDiv;
130 /* Min Frequency supported before post divider for XCLK, memory clock */
131 uint32_t ulXclkMinFreq;
132 /* Max Frequency can be supported for the XCLK, memory clock */
133 uint32_t ulXclkMaxFreq;
135 /*this is the PLL Information Table Extended structure version 10 */
136 uint8_t ucNumberOfExtendedPllBlocks;
137 uint8_t ucSizePLLDefinition;
138 uint16_t ulCrystalFrequencyPixelClock_pll;
139 uint32_t ulMinInputPixelClockPLLFrequency;
140 uint32_t ulMaxInputPixelClockPLLFrequency;
141 uint32_t ulMinOutputPixelClockPLLFrequency;
142 uint32_t ulMaxOutputPixelClockPLLFrequency;
145 uint16_t ulCrystalFrequencyEngineClock_pll;
146 uint32_t ulMinInputFrequencyEngineClock_pll;
147 uint32_t ulMaxInputFrequencyEngineClock_pll;
148 uint32_t ulMinOutputFrequencyEngineClock_pll;
149 uint32_t ulMaxOutputFrequencyEngineClock_pll;
150 uint16_t ulCrystalFrequencyMemoryClock_pll;
151 uint32_t ulMinInputFrequencyMemoryClock_pll;
152 uint32_t ulMaxInputFrequencyMemoryClock_pll;
153 uint32_t ulMinOutputFrequencyMemoryClock_pll;
154 uint32_t ulMaxOutputFrequencyMemoryClock_pll;
155 uint32_t ulMaximumDACOutputFrequency;
158 #define MAX_NO_OF_LCD_RES_TIMING 25
160 struct panel_information_table
162 uint8_t ucPanelIdentification;
163 uint8_t ucPanelIDString[24];
164 uint16_t usHorizontalSize;
165 uint16_t usVerticalSize;
166 uint16_t usFlatPanelType;
167 uint8_t ucRedBitsPerPrimary;
168 uint8_t ucGreenBitsPerPrimary;
169 uint8_t ucBlueBitsPerPrimary;
170 uint8_t ucReservedBitsPerPrimary;
172 uint8_t ucPowerSequenceDelayStepsInMS;
173 uint8_t ucSupportedRefreshRateExtended;
174 uint16_t usExtendedPanelInfoTable;
175 uint16_t usPtrToHalfFrameBufferInformationTable;
176 uint16_t usVccOntoBlOn;
180 uint16_t usFeedBackDiv;
181 uint8_t ucSpreadSpectrumType;
182 uint16_t usSpreadSpectrumPercentage;
183 uint8_t ucBackLightLevel;
185 uint8_t ucPowerSequenceDelay;
186 uint32_t ulPanelData;
187 uint8_t ucPanelRefreshRateData;
188 uint16_t usSupportedRefreshRate;
189 uint16_t usModeTableOffset[MAX_NO_OF_LCD_RES_TIMING];
192 struct extended_panel_info_table
194 uint8_t ucExtendedPanelInfoTableVer;
196 uint8_t ucSSStepSizeIndex;
199 struct lcd_mode_table_center
201 uint16_t usHorizontalRes;
202 uint16_t usVerticalRes;
204 uint16_t usOffset2ExpParamTable;
205 uint16_t usOffset2TvParamTable;
206 uint16_t usPixelClock;
207 uint16_t usPixelClockAdjustment;
211 uint16_t usCrtcHTotal;
212 uint16_t usCrtcHDisp;
213 uint16_t usCrtcHSyncStrt;
214 uint8_t ucCrtcHSyncWid;
215 uint16_t usCrtcVTotal;
216 uint16_t usCrtcVDisp;
217 uint16_t usCrtcVSyncStrt;
221 struct lcd_mode_table_exp
223 uint16_t usPixelClock;
224 uint16_t usPixelClockAdjustment;
228 uint16_t usCrtcHTotal;
229 uint16_t usCrtcHDisp;
230 uint16_t usCrtcHSyncStrt;
231 uint8_t ucCrtcHSyncWid;
232 uint16_t usCrtcVTotal;
233 uint16_t usCrtcVDisp;
234 uint16_t usCrtcVSyncStrt;
236 uint16_t usHorizontalBlendRatio;
237 uint32_t ulVgaVertStretching;
238 uint16_t usCopVertStretching;
239 uint16_t usVgaExtVertStretching;
242 struct tmds_pll_cntl_block
244 uint16_t usClockUpperRange;
245 uint32_t ulPllSetting;
248 #define MAX_PLL_CNTL_ENTRIES 8
250 struct combios_dfp_info_table
252 uint8_t ucDFPInfoTableRev;
253 uint8_t ucDFPInfoTableSize;
254 uint16_t usOffsetDetailedTimingTable;
256 uint8_t ucNumberOfClockRanges;
257 uint16_t usMaxPixelClock;
258 uint32_t ulInitValueTmdsPllCntl;
259 uint32_t ulFinalValueTmdsPllCntl;
260 struct tmds_pll_cntl_block sTmdsPllCntlBlock[MAX_PLL_CNTL_ENTRIES];
263 struct combios_exttmds_table_header
266 uint16_t usTableSize;
270 struct combios_exttmds_block_header
273 uint8_t ucI2CSlaveAddr;
275 uint8_t ucConnectorId;
279 /* Connector table - applicable from Piglet and later ASICs
280 byte 0 (embedded revision)
281 [7:4] = number of chips (valid number 1 - 15)
282 [3:0] = revision number of table (valid number 1 - 15)
285 [7:4] = chip number, max. 15 (valid number 1 - 15)
286 [3:0] = number of connectors for that chip, (valid number 1 - 15)
287 (number of connectors = number of 'Connector info' entries
290 byte 2,3 (Connector info)
291 [15:12] - connector type
297 = 5-15 - reserved for future expansion
298 [11:8] - DDC line pair used for that connector
304 = 5-15 - reserved for future expansion
305 [5] - bit indicating presence of multiplexer for TV,CRT2
306 [7:6] - reserved for future expansion
310 [3:1] - reserved for future expansion
311 [0] - DAC associated with that connector
313 = 1 - non-CRT DAC (e.g. TV DAC, external DAC ..)
315 byte 4,5,6... - byte 4,5 can be another "Connector info" word
316 describing another connector
317 - or byte 5 is a "Chip info" byte for anther chip,
318 then start with byte 5,6 to describe connectors
320 - or byte 5 = 0 if all connectors for all chips on
321 board have been described, no more connector left
324 #define BIOS_CONNECTOR_INFO__TYPE__MASK 0xF000
325 #define BIOS_CONNECTOR_INFO__TYPE__SHIFT 0x0000000C
326 #define BIOS_CONNECTOR_TYPE__NONE 0x00000000
327 #define BIOS_CONNECTOR_TYPE__PROPRIETARY 0x00000001
328 #define BIOS_CONNECTOR_TYPE__CRT 0x00000002
329 #define BIOS_CONNECTOR_TYPE__DVI_I 0x00000003
330 #define BIOS_CONNECTOR_TYPE__DVI_D 0x00000004
332 #define BIOS_CONNECTOR_INFO__DDC_LINE__MASK 0x0F00
333 #define BIOS_CONNECTOR_INFO__DDC_LINE__SHIFT 0x00000008
334 #define BIOS_DDC_LINE__NONE 0x00000000
335 #define BIOS_DDC_LINE__MONID01 0x00000001
336 #define BIOS_DDC_LINE__DVI 0x00000002
337 #define BIOS_DDC_LINE__VGA 0x00000003
338 #define BIOS_DDC_LINE__CRT2 0x00000004
339 #define BIOS_DDC_LINE__GPIOPAD 0x00000005
340 #define BIOS_DDC_LINE__ZV_LCDPAD 0x00000006
342 #define BIOS_CONNECTOR_INFO__TMDS_TYPE__MASK 0x0010
343 #define BIOS_CONNECTOR_INFO__TMDS_TYPE__SHIFT 0x00000004
344 #define BIOS_TMDS_TYPE__INTERNAL 0x00000000
345 #define BIOS_TMDS_TYPE__EXTERNAL 0x00000001
347 #define BIOS_CONNECTOR_INFO__DAC_TYPE__MASK 0x0001
348 #define BIOS_CONNECTOR_INFO__DAC_TYPE__SHIFT 0x00000000
349 #define BIOS_DAC_TYPE__CRT 0x00000000
350 #define BIOS_DAC_TYPE__NON_CRT 0x00000001
352 #define BIOS_CONNECTOR_INFO__MUX_MASK 0x00000020
353 #define BIOS_CONNECTOR_INFO__MUX_SHIFT 0x00000005
355 #define BIOS_CHIPINFO_HEADER__CHIP_NUMBER__MASK 0xF0
356 #define BIOS_CHIPINFO_HEADER__CHIP_NUMBER__SHIFT 0x00000004
358 #define BIOS_CHIPINFO_HEADER__NUMBER_OF_CONNECTORS__MASK 0x0F
359 #define BIOS_CHIPINFO_HEADER__NUMBER_OF_CONNECTORS__SHIFT 0x00000000
361 #define BIOS_CHIPINFO__MAX_NUMBER_OF_CONNECTORS 0x00000010
363 struct combios_connector_chip_info
365 uint8_t ucChipHeader;
366 uint16_t sConnectorInfo[BIOS_CHIPINFO__MAX_NUMBER_OF_CONNECTORS];
369 #define BIOS_CONNECTOR_HEADER__NUMBER_OF_CHIPS__MASK 0xF0
370 #define BIOS_CONNECTOR_HEADER__NUMBER_OF_CHIPS__SHIFT 0x00000004
372 #define BIOS_CONNECTOR_HEADER__TABLE_REVISION__MASK 0x0F
373 #define BIOS_CONNECTOR_HEADER__TABLE_REVISION__SHIFT 0x00000000
375 struct combios_connector_table
377 uint8_t ucConnectorHeader;
378 struct combios_connector_chip_info sChipConnectorInfo[0x10];
383 int combios_parse(unsigned char *rom, struct combios_header *header);