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1 /*

6 *

7 * Permission is hereby granted, free of charge, to any person obtaining

8 * a copy of this software and associated documentation files (the

9 * "Software"), to deal in the Software without restriction, including

10 * without limitation on the rights to use, copy, modify, merge,

11 * publish, distribute, sublicense, and/or sell copies of the Software,

12 * and to permit persons to whom the Software is furnished to do so,

13 * subject to the following conditions:

14 *

15 * The above copyright notice and this permission notice (including the

16 * next paragraph) shall be included in all copies or substantial

17 * portions of the Software.

18 *

19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR

23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

26 * DEALINGS IN THE SOFTWARE.

27 */

28 #include "radeon_ms.h"

29

30 int radeon_ms_dac1_initialize(struct radeon_ms_output *output)

31 {

32 struct drm_radeon_private *dev_priv = output->dev->dev_private;

33 struct radeon_state *state = &dev_priv->driver_state;

34

35 state->dac_cntl =

36 REG_S(DAC_CNTL, DAC_RANGE_CNTL, DAC_RANGE_CNTL__PS2) |

37 DAC_CNTL__DAC_8BIT_EN |

38 DAC_CNTL__DAC_VGA_ADR_EN |

39 DAC_CNTL__DAC_PDWN |

40 REG_S(DAC_CNTL, DAC, 0xff);

41 state->dac_ext_cntl = 0;

42 state->dac_macro_cntl =

43 DAC_MACRO_CNTL__DAC_PDWN_R |

44 DAC_MACRO_CNTL__DAC_PDWN_G |

45 DAC_MACRO_CNTL__DAC_PDWN_B |

46 REG_S(DAC_MACRO_CNTL, DAC_WHITE_CNTL, 7) |

47 REG_S(DAC_MACRO_CNTL, DAC_BG_ADJ, 7);

48 state->dac_embedded_sync_cntl =

49 DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_VSYNC_EN_Y_G;

50 state->dac_broad_pulse = 0;

51 state->dac_skew_clks = 0;

52 state->dac_incr = 0;

53 state->dac_neg_sync_level = 0;

54 state->dac_pos_sync_level = 0;

55 state->dac_blank_level = 0;

56 state->dac_sync_equalization = 0;

57 state->disp_output_cntl = 0;

58 radeon_ms_dac1_restore(output, state);

59 return 0;

60 }

61

62 enum drm_output_status radeon_ms_dac1_detect(struct radeon_ms_output *output)

63 {

64 return output_status_unknown;

65 }

66

67 void radeon_ms_dac1_dpms(struct radeon_ms_output *output, int mode)

68 {

69 struct drm_radeon_private *dev_priv = output->dev->dev_private;

70 struct radeon_state *state = &dev_priv->driver_state;

71 uint32_t dac_cntl;

72 uint32_t dac_macro_cntl;

73

74 dac_cntl = DAC_CNTL__DAC_PDWN;

75 dac_macro_cntl = DAC_MACRO_CNTL__DAC_PDWN_R |

76 DAC_MACRO_CNTL__DAC_PDWN_G |

77 DAC_MACRO_CNTL__DAC_PDWN_B;

78 switch(mode) {

79 case DPMSModeOn:

80 state->dac_cntl &= ~dac_cntl;

81 state->dac_macro_cntl &= ~dac_macro_cntl;

82 break;

83 case DPMSModeStandby:

84 case DPMSModeSuspend:

85 case DPMSModeOff:

86 state->dac_cntl |= dac_cntl;

87 state->dac_macro_cntl |= dac_macro_cntl;

88 break;

89 default:

90 /* error */

91 break;

92 }

93 MMIO_W(DAC_CNTL, state->dac_cntl);

94 MMIO_W(DAC_MACRO_CNTL, state->dac_macro_cntl);

95 }

96

97 int radeon_ms_dac1_get_modes(struct radeon_ms_output *output)

98 {

99 return 0;

100 }

101

102 bool radeon_ms_dac1_mode_fixup(struct radeon_ms_output *output,

103 struct drm_display_mode *mode,

104 struct drm_display_mode *adjusted_mode)

105 {

106 return true;

107 }

108

109 int radeon_ms_dac1_mode_set(struct radeon_ms_output *output,

110 struct drm_display_mode *mode,

111 struct drm_display_mode *adjusted_mode)

112 {

113 struct drm_radeon_private *dev_priv = output->dev->dev_private;

114 struct radeon_ms_connector *connector = output->connector;

115 struct radeon_state *state = &dev_priv->driver_state;

116 uint32_t v = 0;

117

118 if (connector == NULL) {

119 /* output not associated with a connector */

120 return -EINVAL;

121 }

122 state->disp_output_cntl &= ~DISP_OUTPUT_CNTL__DISP_DAC_SOURCE__MASK;

123 state->dac_cntl2 &= ~DAC_CNTL2__DAC_CLK_SEL;

124 switch (connector->crtc) {

125 case 1:

126 v = DISP_DAC_SOURCE__PRIMARYCRTC;

127 break;

128 case 2:

129 v = DISP_DAC_SOURCE__SECONDARYCRTC;

130 state->dac_cntl2 |= DAC_CNTL2__DAC_CLK_SEL;

131 break;

132 }

133 state->disp_output_cntl |= REG_S(DISP_OUTPUT_CNTL, DISP_DAC_SOURCE, v);

134 MMIO_W(DISP_OUTPUT_CNTL, state->disp_output_cntl);

135 MMIO_W(DAC_CNTL2, state->dac_cntl2);

136 return 0;

137 }

138

139 void radeon_ms_dac1_restore(struct radeon_ms_output *output,

140 struct radeon_state *state)

141 {

142 struct drm_radeon_private *dev_priv = output->dev->dev_private;

143

144 MMIO_W(DAC_CNTL, state->dac_cntl);

145 MMIO_W(DAC_EXT_CNTL, state->dac_ext_cntl);

146 MMIO_W(DAC_MACRO_CNTL, state->dac_macro_cntl);

147 MMIO_W(DAC_EMBEDDED_SYNC_CNTL, state->dac_embedded_sync_cntl);

148 MMIO_W(DAC_BROAD_PULSE, state->dac_broad_pulse);

149 MMIO_W(DAC_SKEW_CLKS, state->dac_skew_clks);

150 MMIO_W(DAC_INCR, state->dac_incr);

151 MMIO_W(DAC_NEG_SYNC_LEVEL, state->dac_neg_sync_level);

152 MMIO_W(DAC_POS_SYNC_LEVEL, state->dac_pos_sync_level);

153 MMIO_W(DAC_BLANK_LEVEL, state->dac_blank_level);

154 MMIO_W(DAC_SYNC_EQUALIZATION, state->dac_sync_equalization);

155 }

156

157 void radeon_ms_dac1_save(struct radeon_ms_output *output,

158 struct radeon_state *state)

159 {

160 struct drm_radeon_private *dev_priv = output->dev->dev_private;

161

162 state->dac_cntl = MMIO_R(DAC_CNTL);

163 state->dac_ext_cntl = MMIO_R(DAC_EXT_CNTL);

164 state->dac_macro_cntl = MMIO_R(DAC_MACRO_CNTL);

165 state->dac_embedded_sync_cntl = MMIO_R(DAC_EMBEDDED_SYNC_CNTL);

166 state->dac_broad_pulse = MMIO_R(DAC_BROAD_PULSE);

167 state->dac_skew_clks = MMIO_R(DAC_SKEW_CLKS);

168 state->dac_incr = MMIO_R(DAC_INCR);

169 state->dac_neg_sync_level = MMIO_R(DAC_NEG_SYNC_LEVEL);

170 state->dac_pos_sync_level = MMIO_R(DAC_POS_SYNC_LEVEL);

171 state->dac_blank_level = MMIO_R(DAC_BLANK_LEVEL);

172 state->dac_sync_equalization = MMIO_R(DAC_SYNC_EQUALIZATION);

173 }

174

175 int radeon_ms_dac2_initialize(struct radeon_ms_output *output)

176 {

177 struct drm_radeon_private *dev_priv = output->dev->dev_private;

178 struct radeon_state *state = &dev_priv->driver_state;

179

180 state->tv_dac_cntl = TV_DAC_CNTL__BGSLEEP |

181 REG_S(TV_DAC_CNTL, STD, STD__PS2) |

182 REG_S(TV_DAC_CNTL, BGADJ, 0);

183 switch (dev_priv->family) {

184 case CHIP_R100:

185 case CHIP_R200:

186 case CHIP_RV200:

187 case CHIP_RV250:

188 case CHIP_RV280:

189 case CHIP_RS300:

190 case CHIP_R300:

191 case CHIP_R350:

192 case CHIP_R360:

193 case CHIP_RV350:

194 case CHIP_RV370:

195 case CHIP_RV380:

196 case CHIP_RS400:

197 state->tv_dac_cntl |= TV_DAC_CNTL__RDACPD |

198 TV_DAC_CNTL__GDACPD |

199 TV_DAC_CNTL__BDACPD |

200 REG_S(TV_DAC_CNTL, DACADJ, 0);

201 break;

202 case CHIP_RV410:

203 case CHIP_R420:

204 case CHIP_R430:

205 case CHIP_R480:

206 state->tv_dac_cntl |= TV_DAC_CNTL__RDACPD_R4 |

207 TV_DAC_CNTL__GDACPD_R4 |

208 TV_DAC_CNTL__BDACPD_R4 |

209 REG_S(TV_DAC_CNTL, DACADJ_R4, 0);

210 break;

211 }

212 state->tv_master_cntl = TV_MASTER_CNTL__TV_ASYNC_RST |

213 TV_MASTER_CNTL__CRT_ASYNC_RST |

214 TV_MASTER_CNTL__RESTART_PHASE_FIX |

215 TV_MASTER_CNTL__CRT_FIFO_CE_EN |

216 TV_MASTER_CNTL__TV_FIFO_CE_EN;

217 state->dac_cntl2 = 0;

218 state->disp_output_cntl = 0;

219 radeon_ms_dac2_restore(output, state);

220 return 0;

221 }

222

223 enum drm_output_status radeon_ms_dac2_detect(struct radeon_ms_output *output)

224 {

225 return output_status_unknown;

226 }

227

228 void radeon_ms_dac2_dpms(struct radeon_ms_output *output, int mode)

229 {

230 struct drm_radeon_private *dev_priv = output->dev->dev_private;

231 struct radeon_state *state = &dev_priv->driver_state;

232 uint32_t tv_dac_cntl_on, tv_dac_cntl_off;

233

234 tv_dac_cntl_off = TV_DAC_CNTL__BGSLEEP;

235 tv_dac_cntl_on = TV_DAC_CNTL__NBLANK |

236 TV_DAC_CNTL__NHOLD;

237 switch (dev_priv->family) {

238 case CHIP_R100:

239 case CHIP_R200:

240 case CHIP_RV200:

241 case CHIP_RV250:

242 case CHIP_RV280:

243 case CHIP_RS300:

244 case CHIP_R300:

245 case CHIP_R350:

246 case CHIP_R360:

247 case CHIP_RV350:

248 case CHIP_RV370:

249 case CHIP_RV380:

250 case CHIP_RS400:

251 tv_dac_cntl_off |= TV_DAC_CNTL__RDACPD |

252 TV_DAC_CNTL__GDACPD |

253 TV_DAC_CNTL__BDACPD;

254 break;

255 case CHIP_RV410:

256 case CHIP_R420:

257 case CHIP_R430:

258 case CHIP_R480:

259 tv_dac_cntl_off |= TV_DAC_CNTL__RDACPD_R4 |

260 TV_DAC_CNTL__GDACPD_R4 |

261 TV_DAC_CNTL__BDACPD_R4;

262 break;

263 }

264 switch(mode) {

265 case DPMSModeOn:

266 state->tv_dac_cntl &= ~tv_dac_cntl_off;

267 state->tv_dac_cntl |= tv_dac_cntl_on;

268 break;

269 case DPMSModeStandby:

270 case DPMSModeSuspend:

271 case DPMSModeOff:

272 state->tv_dac_cntl &= ~tv_dac_cntl_on;

273 state->tv_dac_cntl |= tv_dac_cntl_off;

274 break;

275 default:

276 /* error */

277 break;

278 }

279 MMIO_W(TV_DAC_CNTL, state->tv_dac_cntl);

280 }

281

282 int radeon_ms_dac2_get_modes(struct radeon_ms_output *output)

283 {

284 return 0;

285 }

286

287 bool radeon_ms_dac2_mode_fixup(struct radeon_ms_output *output,

288 struct drm_display_mode *mode,

289 struct drm_display_mode *adjusted_mode)

290 {

291 return true;

292 }

293

294 int radeon_ms_dac2_mode_set(struct radeon_ms_output *output,

295 struct drm_display_mode *mode,

296 struct drm_display_mode *adjusted_mode)

297 {

298 struct drm_radeon_private *dev_priv = output->dev->dev_private;

299 struct radeon_ms_connector *connector = output->connector;

300 struct radeon_state *state = &dev_priv->driver_state;

301

302 if (connector == NULL) {

303 /* output not associated with a connector */

304 return -EINVAL;

305 }

306 switch (dev_priv->family) {

307 case CHIP_R100:

308 case CHIP_R200:

309 state->disp_output_cntl &= ~DISP_OUTPUT_CNTL__DISP_TV_SOURCE;

310 switch (connector->crtc) {

311 case 1:

312 break;

313 case 2:

314 state->disp_output_cntl |=

315 DISP_OUTPUT_CNTL__DISP_TV_SOURCE;

316 break;

317 }

318 break;

319 case CHIP_RV200:

320 case CHIP_RV250:

321 case CHIP_RV280:

322 case CHIP_RS300:

323 break;

324 case CHIP_R300:

325 case CHIP_R350:

326 case CHIP_R360:

327 case CHIP_RV350:

328 case CHIP_RV370:

329 case CHIP_RV380:

330 case CHIP_RS400:

331 case CHIP_RV410:

332 case CHIP_R420:

333 case CHIP_R430:

334 case CHIP_R480:

335 state->disp_output_cntl &=

336 ~DISP_OUTPUT_CNTL__DISP_TVDAC_SOURCE__MASK;

337 switch (connector->crtc) {

338 case 1:

339 state->disp_output_cntl |=

340 REG_S(DISP_OUTPUT_CNTL,

341 DISP_TVDAC_SOURCE,

342 DISP_TVDAC_SOURCE__PRIMARYCRTC);

343 break;

344 case 2:

345 state->disp_output_cntl |=

346 REG_S(DISP_OUTPUT_CNTL,

347 DISP_TVDAC_SOURCE,

348 DISP_TVDAC_SOURCE__SECONDARYCRTC);

349 break;

350 }

351 break;

352 }

353 switch (dev_priv->family) {

354 case CHIP_R200:

355 break;

356 case CHIP_R100:

357 case CHIP_RV200:

358 case CHIP_RV250:

359 case CHIP_RV280:

360 case CHIP_RS300:

361 case CHIP_R300:

362 case CHIP_R350:

363 case CHIP_R360:

364 case CHIP_RV350:

365 case CHIP_RV370:

366 case CHIP_RV380:

367 case CHIP_RS400:

368 case CHIP_RV410:

369 case CHIP_R420:

370 case CHIP_R430:

371 case CHIP_R480:

372 if (connector->type != CONNECTOR_CTV &&

373 connector->type != CONNECTOR_STV) {

374 state->dac_cntl2 |= DAC_CNTL2__DAC2_CLK_SEL;

375 }

376 }

377 MMIO_W(DAC_CNTL2, state->dac_cntl2);

378 MMIO_W(DISP_OUTPUT_CNTL, state->disp_output_cntl);

379 return 0;

380 }

381

382 void radeon_ms_dac2_restore(struct radeon_ms_output *output,

383 struct radeon_state *state)

384 {

385 struct drm_radeon_private *dev_priv = output->dev->dev_private;

386

387 MMIO_W(DAC_CNTL2, state->dac_cntl2);

388 MMIO_W(TV_DAC_CNTL, state->tv_dac_cntl);

389 MMIO_W(TV_MASTER_CNTL, state->tv_master_cntl);

390 }

391

392 void radeon_ms_dac2_save(struct radeon_ms_output *output,

393 struct radeon_state *state)

394 {

395 struct drm_radeon_private *dev_priv = output->dev->dev_private;

396

397 state->dac_cntl2 = MMIO_R(DAC_CNTL2);

398 state->tv_dac_cntl = MMIO_R(TV_DAC_CNTL);

399 state->tv_master_cntl = MMIO_R(TV_MASTER_CNTL);

400 }