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1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro

2 *

5 *

8 *

11 *

12 * Permission is hereby granted, free of charge, to any person obtaining a

13 * copy of this software and associated documentation files (the "Software"),

14 * to deal in the Software without restriction, including without limitation

15 * the rights to use, copy, modify, merge, publish, distribute, sub license,

16 * and/or sell copies of the Software, and to permit persons to whom the

17 * Software is furnished to do so, subject to the following conditions:

18 *

19 * The above copyright notice and this permission notice (including the

20 * next paragraph) shall be included in all copies or substantial portions

21 * of the Software.

22 *

23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL

26 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,

27 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR

28 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE

29 * USE OR OTHER DEALINGS IN THE SOFTWARE.

30 *

31 * Authors:

32 * Tungsten Graphics,

33 * Erdi Chen,

34 * Thomas Hellstrom.

35 */

37 #include "drmP.h"

38 #include "drm.h"

39 #include "via_drm.h"

40 #include "via_drv.h"

41 #include "via_3d_reg.h"

43 #define SetReg2DAGP(nReg, nData) { \

44 *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \

45 *((uint32_t *)(vb) + 1) = (nData); \

46 vb = ((uint32_t *)vb) + 2; \

47 dev_priv->dma_low +=8; \

48 }

50 #define via_flush_write_combine() DRM_MEMORYBARRIER()

52 #define VIA_OUT_RING_QW(w1,w2) \

53 *vb++ = (w1); \

54 *vb++ = (w2); \

55 dev_priv->dma_low += 8;

57 static void via_cmdbuf_start(drm_via_private_t *dev_priv);

58 static void via_cmdbuf_pause(drm_via_private_t *dev_priv);

59 static void via_cmdbuf_reset(drm_via_private_t *dev_priv);

60 static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);

61 static int via_wait_idle(drm_via_private_t *dev_priv);

62 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);

65 /*

66 * Free space in command buffer.

67 */

69 static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv)

70 {

71 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

72 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;

74 return ((hw_addr <= dev_priv->dma_low) ?

75 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :

76 (hw_addr - dev_priv->dma_low));

77 }

79 /*

80 * How much does the command regulator lag behind?

81 */

83 static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv)

84 {

85 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

86 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;

88 return ((hw_addr <= dev_priv->dma_low) ?

89 (dev_priv->dma_low - hw_addr) :

90 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));

91 }

93 /*

94 * Check that the given size fits in the buffer, otherwise wait.

95 */

97 static inline int

98 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)

99 {

100 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

101 uint32_t cur_addr, hw_addr, next_addr;

102 volatile uint32_t *hw_addr_ptr;

103 uint32_t count;

104 hw_addr_ptr = dev_priv->hw_addr_ptr;

105 cur_addr = dev_priv->dma_low;

106 next_addr = cur_addr + size + 512 * 1024;

107 count = 1000000;

108 do {

109 hw_addr = *hw_addr_ptr - agp_base;

110 if (count-- == 0) {

111 DRM_ERROR

112 ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",

113 hw_addr, cur_addr, next_addr);

114 return -1;

115 }

116 if ((cur_addr < hw_addr) && (next_addr >= hw_addr))

117 msleep(1);

118 } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));

119 return 0;

120 }

121

122

123 /*

124 * Checks whether buffer head has reach the end. Rewind the ring buffer

125 * when necessary.

126 *

127 * Returns virtual pointer to ring buffer.

128 */

129

130 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,

131 unsigned int size)

132 {

133 if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >

134 dev_priv->dma_high) {

135 via_cmdbuf_rewind(dev_priv);

136 }

137 if (via_cmdbuf_wait(dev_priv, size) != 0) {

138 return NULL;

139 }

140

141 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);

142 }

143

144 int via_dma_cleanup(struct drm_device * dev)

145 {

146 if (dev->dev_private) {

147 drm_via_private_t *dev_priv =

148 (drm_via_private_t *) dev->dev_private;

149

150 if (dev_priv->ring.virtual_start) {

151 via_cmdbuf_reset(dev_priv);

152

153 drm_core_ioremapfree(&dev_priv->ring.map, dev);

154 dev_priv->ring.virtual_start = NULL;

155 }

156

157 }

158

159 return 0;

160 }

161

162 static int via_initialize(struct drm_device * dev,

163 drm_via_private_t * dev_priv,

164 drm_via_dma_init_t * init)

165 {

166 if (!dev_priv || !dev_priv->mmio) {

167 DRM_ERROR("via_dma_init called before via_map_init\n");

168 return -EFAULT;

169 }

170

171 if (dev_priv->ring.virtual_start != NULL) {

172 DRM_ERROR("called again without calling cleanup\n");

173 return -EFAULT;

174 }

175

176 if (!dev->agp || !dev->agp->base) {

177 DRM_ERROR("called with no agp memory available\n");

178 return -EFAULT;

179 }

180

181 if (dev_priv->chipset == VIA_DX9_0) {

182 DRM_ERROR("AGP DMA is not supported on this chip\n");

183 return -EINVAL;

184 }

185

186 dev_priv->ring.map.offset = dev->agp->base + init->offset;

187 dev_priv->ring.map.size = init->size;

188 dev_priv->ring.map.type = 0;

189 dev_priv->ring.map.flags = 0;

190 dev_priv->ring.map.mtrr = 0;

191

192 drm_core_ioremap(&dev_priv->ring.map, dev);

193

194 if (dev_priv->ring.map.handle == NULL) {

195 via_dma_cleanup(dev);

196 DRM_ERROR("can not ioremap virtual address for"

197 " ring buffer\n");

198 return -ENOMEM;

199 }

200

201 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;

202

203 dev_priv->dma_ptr = dev_priv->ring.virtual_start;

204 dev_priv->dma_low = 0;

205 dev_priv->dma_high = init->size;

206 dev_priv->dma_wrap = init->size;

207 dev_priv->dma_offset = init->offset;

208 dev_priv->last_pause_ptr = NULL;

209 dev_priv->hw_addr_ptr =

210 (volatile uint32_t *)((char *)dev_priv->mmio->handle +

211 init->reg_pause_addr);

212

213 via_cmdbuf_start(dev_priv);

214

215 return 0;

216 }

217

218 static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv)

219 {

220 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;

221 drm_via_dma_init_t *init = data;

222 int retcode = 0;

223

224 switch (init->func) {

225 case VIA_INIT_DMA:

226 if (!DRM_SUSER(DRM_CURPROC))

227 retcode = -EPERM;

228 else

229 retcode = via_initialize(dev, dev_priv, init);

230 break;

231 case VIA_CLEANUP_DMA:

232 if (!DRM_SUSER(DRM_CURPROC))

233 retcode = -EPERM;

234 else

235 retcode = via_dma_cleanup(dev);

236 break;

237 case VIA_DMA_INITIALIZED:

238 retcode = (dev_priv->ring.virtual_start != NULL) ?

239 0 : -EFAULT;

240 break;

241 default:

242 retcode = -EINVAL;

243 break;

244 }

245

246 return retcode;

247 }

248

249

250

251 static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd)

252 {

253 drm_via_private_t *dev_priv;

254 uint32_t *vb;

255 int ret;

256

257 dev_priv = (drm_via_private_t *) dev->dev_private;

258

259 if (dev_priv->ring.virtual_start == NULL) {

260 DRM_ERROR("called without initializing AGP ring buffer.\n");

261 return -EFAULT;

262 }

263

264 if (cmd->size > VIA_PCI_BUF_SIZE) {

265 return -ENOMEM;

266 }

267

268 if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))

269 return -EFAULT;

270

271 /*

272 * Running this function on AGP memory is dead slow. Therefore

273 * we run it on a temporary cacheable system memory buffer and

274 * copy it to AGP memory when ready.

275 */

276

277 if ((ret =

278 via_verify_command_stream((uint32_t *)dev_priv->pci_buf,

279 cmd->size, dev, 1))) {

280 return ret;

281 }

282

283 vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);

284 if (vb == NULL) {

285 return -EAGAIN;

286 }

287

288 memcpy(vb, dev_priv->pci_buf, cmd->size);

289

290 dev_priv->dma_low += cmd->size;

291

292 /*

293 * Small submissions somehow stalls the CPU. (AGP cache effects?)

294 * pad to greater size.

295 */

296

297 if (cmd->size < 0x100)

298 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);

299 via_cmdbuf_pause(dev_priv);

300

301 return 0;

302 }

303

304 int via_driver_dma_quiescent(struct drm_device * dev)

305 {

306 drm_via_private_t *dev_priv = dev->dev_private;

307

308 if (!via_wait_idle(dev_priv)) {

309 return -EBUSY;

310 }

311 return 0;

312 }

313

314 static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)

315 {

316

317 LOCK_TEST_WITH_RETURN(dev, file_priv);

318

319 return via_driver_dma_quiescent(dev);

320 }

321

322 static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)

323 {

324 drm_via_cmdbuffer_t *cmdbuf = data;

325 int ret;

326

327 LOCK_TEST_WITH_RETURN(dev, file_priv);

328

329 DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size);

330

331 ret = via_dispatch_cmdbuffer(dev, cmdbuf);

332 if (ret) {

333 return ret;

334 }

335

336 return 0;

337 }

338

339 static int via_dispatch_pci_cmdbuffer(struct drm_device * dev,

340 drm_via_cmdbuffer_t * cmd)

341 {

342 drm_via_private_t *dev_priv = dev->dev_private;

343 int ret;

344

345 if (cmd->size > VIA_PCI_BUF_SIZE) {

346 return -ENOMEM;

347 }

348 if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))

349 return -EFAULT;

350

351 if ((ret =

352 via_verify_command_stream((uint32_t *) dev_priv->pci_buf,

353 cmd->size, dev, 0))) {

354 return ret;

355 }

356

357 ret =

358 via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,

359 cmd->size);

360 return ret;

361 }

362

363 static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)

364 {

365 drm_via_cmdbuffer_t *cmdbuf = data;

366 int ret;

367

368 LOCK_TEST_WITH_RETURN(dev, file_priv);

369

370 DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size);

371

372 ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf);

373 if (ret) {

374 return ret;

375 }

376

377 return 0;

378 }

379

380 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,

381 uint32_t * vb, int qw_count)

382 {

383 for (; qw_count > 0; --qw_count) {

384 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);

385 }

386 return vb;

387 }

388

389 /*

390 * This function is used internally by ring buffer mangement code.

391 *

392 * Returns virtual pointer to ring buffer.

393 */

394 static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)

395 {

396 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);

397 }

398

399 /*

400 * Hooks a segment of data into the tail of the ring-buffer by

401 * modifying the pause address stored in the buffer itself. If

402 * the regulator has already paused, restart it.

403 */

404 static int via_hook_segment(drm_via_private_t * dev_priv,

405 uint32_t pause_addr_hi, uint32_t pause_addr_lo,

406 int no_pci_fire)

407 {

408 int paused, count;

409 volatile uint32_t *paused_at = dev_priv->last_pause_ptr;

410 uint32_t reader,ptr;

411 uint32_t diff;

412

413 paused = 0;

414 via_flush_write_combine();

415 (void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1);

416

417 *paused_at = pause_addr_lo;

418 via_flush_write_combine();

419 (void) *paused_at;

420

421 reader = *(dev_priv->hw_addr_ptr);

422 ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +

423 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;

424

425 dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;

426

427 /*

428 * If there is a possibility that the command reader will

429 * miss the new pause address and pause on the old one,

430 * In that case we need to program the new start address

431 * using PCI.

432 */

433

434 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;

435 count = 10000000;

436 while(diff == 0 && count--) {

437 paused = (VIA_READ(0x41c) & 0x80000000);

438 if (paused)

439 break;

440 reader = *(dev_priv->hw_addr_ptr);

441 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;

442 }

443

444 paused = VIA_READ(0x41c) & 0x80000000;

445

446 if (paused && !no_pci_fire) {

447 reader = *(dev_priv->hw_addr_ptr);

448 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;

449 diff &= (dev_priv->dma_high - 1);

450 if (diff != 0 && diff < (dev_priv->dma_high >> 1)) {

451 DRM_ERROR("Paused at incorrect address. "

452 "0x%08x, 0x%08x 0x%08x\n",

453 ptr, reader, dev_priv->dma_diff);

454 } else if (diff == 0) {

455 /*

456 * There is a concern that these writes may stall the PCI bus

457 * if the GPU is not idle. However, idling the GPU first

458 * doesn't make a difference.

459 */

460

461 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));

462 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);

463 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);

464 VIA_READ(VIA_REG_TRANSPACE);

465 }

466 }

467

468 return paused;

469 }

470

471

472

473 static int via_wait_idle(drm_via_private_t *dev_priv)

474 {

475 int count = 10000000;

476

477 while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--);

478

479 while (count-- && (VIA_READ(VIA_REG_STATUS) &

480 (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |

481 VIA_3D_ENG_BUSY))) ;

482 return count;

483 }

484

485 static uint32_t *via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type,

486 uint32_t addr, uint32_t *cmd_addr_hi,

487 uint32_t *cmd_addr_lo, int skip_wait)

488 {

489 uint32_t agp_base;

490 uint32_t cmd_addr, addr_lo, addr_hi;

491 uint32_t *vb;

492 uint32_t qw_pad_count;

493

494 if (!skip_wait)

495 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);

496

497 vb = via_get_dma(dev_priv);

498 VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |

499 (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);

500

501 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

502 qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -

503 ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);

504

505 cmd_addr = (addr) ? addr :

506 agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);

507 addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |

508 (cmd_addr & HC_HAGPBpL_MASK));

509 addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));

510

511 vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);

512 VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);

513 return vb;

514 }

515

516 static void via_cmdbuf_start(drm_via_private_t * dev_priv)

517 {

518 uint32_t pause_addr_lo, pause_addr_hi;

519 uint32_t start_addr, start_addr_lo;

520 uint32_t end_addr, end_addr_lo;

521 uint32_t command;

522 uint32_t agp_base;

523 uint32_t ptr;

524 uint32_t reader;

525 int count;

526

527 dev_priv->dma_low = 0;

528

529 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

530 start_addr = agp_base;

531 end_addr = agp_base + dev_priv->dma_high;

532

533 start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));

534 end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));

535 command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |

536 ((end_addr & 0xff000000) >> 16));

537

538 dev_priv->last_pause_ptr =

539 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,

540 &pause_addr_hi, & pause_addr_lo, 1) - 1;

541

542 via_flush_write_combine();

543 (void) *(volatile uint32_t *)dev_priv->last_pause_ptr;

544

545 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));

546 VIA_WRITE(VIA_REG_TRANSPACE, command);

547 VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);

548 VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);

549

550 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);

551 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);

552 DRM_WRITEMEMORYBARRIER();

553 VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);

554 VIA_READ(VIA_REG_TRANSPACE);

555

556 dev_priv->dma_diff = 0;

557

558 count = 10000000;

559 while (!(VIA_READ(0x41c) & 0x80000000) && count--);

560

561 reader = *(dev_priv->hw_addr_ptr);

562 ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +

563 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;

564

565 /*

566 * This is the difference between where we tell the

567 * command reader to pause and where it actually pauses.

568 * This differs between hw implementation so we need to

569 * detect it.

570 */

571

572 dev_priv->dma_diff = ptr - reader;

573 }

574

575 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords)

576 {

577 uint32_t *vb;

578

579 via_cmdbuf_wait(dev_priv, qwords + 2);

580 vb = via_get_dma(dev_priv);

581 VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);

582 via_align_buffer(dev_priv, vb, qwords);

583 }

584

585 static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)

586 {

587 uint32_t *vb = via_get_dma(dev_priv);

588 SetReg2DAGP(0x0C, (0 | (0 << 16)));

589 SetReg2DAGP(0x10, 0 | (0 << 16));

590 SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);

591 }

592

593 static void via_cmdbuf_jump(drm_via_private_t * dev_priv)

594 {

595 uint32_t agp_base;

596 uint32_t pause_addr_lo, pause_addr_hi;

597 uint32_t jump_addr_lo, jump_addr_hi;

598 volatile uint32_t *last_pause_ptr;

599 uint32_t dma_low_save1, dma_low_save2;

600

601 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

602 via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,

603 &jump_addr_lo, 0);

604

605 dev_priv->dma_wrap = dev_priv->dma_low;

606

607 /*

608 * Wrap command buffer to the beginning.

609 */

610

611 dev_priv->dma_low = 0;

612 if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {

613 DRM_ERROR("via_cmdbuf_jump failed\n");

614 }

615

616 via_dummy_bitblt(dev_priv);

617 via_dummy_bitblt(dev_priv);

618

619 last_pause_ptr =

620 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,

621 &pause_addr_lo, 0) - 1;

622 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,

623 &pause_addr_lo, 0);

624

625 *last_pause_ptr = pause_addr_lo;

626 dma_low_save1 = dev_priv->dma_low;

627

628 /*

629 * Now, set a trap that will pause the regulator if it tries to rerun the old

630 * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause

631 * and reissues the jump command over PCI, while the regulator has already taken the jump

632 * and actually paused at the current buffer end).

633 * There appears to be no other way to detect this condition, since the hw_addr_pointer

634 * does not seem to get updated immediately when a jump occurs.

635 */

636

637 last_pause_ptr =

638 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,

639 &pause_addr_lo, 0) - 1;

640 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,

641 &pause_addr_lo, 0);

642 *last_pause_ptr = pause_addr_lo;

643

644 dma_low_save2 = dev_priv->dma_low;

645 dev_priv->dma_low = dma_low_save1;

646 via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);

647 dev_priv->dma_low = dma_low_save2;

648 via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);

649 }

650

651

652 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)

653 {

654 via_cmdbuf_jump(dev_priv);

655 }

656

657 static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)

658 {

659 uint32_t pause_addr_lo, pause_addr_hi;

660

661 via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);

662 via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);

663 }

664

665

666 static void via_cmdbuf_pause(drm_via_private_t * dev_priv)

667 {

668 via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);

669 }

670

671 static void via_cmdbuf_reset(drm_via_private_t * dev_priv)

672 {

673 via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);

674 via_wait_idle(dev_priv);

675 }

676

677 /*

678 * User interface to the space and lag functions.

679 */

680

681 static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv)

682 {

683 drm_via_cmdbuf_size_t *d_siz = data;

684 int ret = 0;

685 uint32_t tmp_size, count;

686 drm_via_private_t *dev_priv;

687

688 DRM_DEBUG("\n");

689 LOCK_TEST_WITH_RETURN(dev, file_priv);

690

691 dev_priv = (drm_via_private_t *) dev->dev_private;

692

693 if (dev_priv->ring.virtual_start == NULL) {

694 DRM_ERROR("called without initializing AGP ring buffer.\n");

695 return -EFAULT;

696 }

697

698 count = 1000000;

699 tmp_size = d_siz->size;

700 switch (d_siz->func) {

701 case VIA_CMDBUF_SPACE:

702 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size)

703 && count--) {

704 if (!d_siz->wait) {

705 break;

706 }

707 }

708 if (!count) {

709 DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");

710 ret = -EAGAIN;

711 }

712 break;

713 case VIA_CMDBUF_LAG:

714 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size)

715 && count--) {

716 if (!d_siz->wait) {

717 break;

718 }

719 }

720 if (!count) {

721 DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");

722 ret = -EAGAIN;

723 }

724 break;

725 default:

726 ret = -EFAULT;

727 }

728 d_siz->size = tmp_size;

729

730 return ret;

731 }

732

733 #ifndef VIA_HAVE_DMABLIT

734 int

735 via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv ) {

736 DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");

737 return -EINVAL;

738 }

739 int

740 via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv ) {

741 DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");

742 return -EINVAL;

743 }

744 #endif

745

746 struct drm_ioctl_desc via_ioctls[] = {

747 DRM_IOCTL_DEF(DRM_VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH),

748 DRM_IOCTL_DEF(DRM_VIA_FREEMEM, via_mem_free, DRM_AUTH),

749 DRM_IOCTL_DEF(DRM_VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER),

750 DRM_IOCTL_DEF(DRM_VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER),

751 DRM_IOCTL_DEF(DRM_VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER),

752 DRM_IOCTL_DEF(DRM_VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH),

753 DRM_IOCTL_DEF(DRM_VIA_DMA_INIT, via_dma_init, DRM_AUTH),

754 DRM_IOCTL_DEF(DRM_VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH),

755 DRM_IOCTL_DEF(DRM_VIA_FLUSH, via_flush_ioctl, DRM_AUTH),

756 DRM_IOCTL_DEF(DRM_VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH),

757 DRM_IOCTL_DEF(DRM_VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH),

758 DRM_IOCTL_DEF(DRM_VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH),

759 DRM_IOCTL_DEF(DRM_VIA_DMA_BLIT, via_dma_blit, DRM_AUTH),

760 DRM_IOCTL_DEF(DRM_VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH)

761 };

762

763 int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);