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1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro

2 *

5 *

8 *

11 *

12 * Permission is hereby granted, free of charge, to any person obtaining a

13 * copy of this software and associated documentation files (the "Software"),

14 * to deal in the Software without restriction, including without limitation

15 * the rights to use, copy, modify, merge, publish, distribute, sub license,

16 * and/or sell copies of the Software, and to permit persons to whom the

17 * Software is furnished to do so, subject to the following conditions:

18 *

19 * The above copyright notice and this permission notice (including the

20 * next paragraph) shall be included in all copies or substantial portions

21 * of the Software.

22 *

23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL

26 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,

27 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR

28 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE

29 * USE OR OTHER DEALINGS IN THE SOFTWARE.

30 *

31 * Authors:

32 * Tungsten Graphics,

33 * Erdi Chen,

34 * Thomas Hellstrom.

35 */

37 #include "drmP.h"

38 #include "drm.h"

39 #include "via_drm.h"

40 #include "via_drv.h"

41 #include "via_3d_reg.h"

43 #define SetReg2DAGP(nReg, nData) { \

44 *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \

45 *((uint32_t *)(vb) + 1) = (nData); \

46 vb = ((uint32_t *)vb) + 2; \

47 dev_priv->dma_low +=8; \

48 }

50 #define via_flush_write_combine() DRM_MEMORYBARRIER()

52 #define VIA_OUT_RING_QW(w1,w2) \

53 *vb++ = (w1); \

54 *vb++ = (w2); \

55 dev_priv->dma_low += 8;

57 static void via_cmdbuf_start(drm_via_private_t *dev_priv);

58 static void via_cmdbuf_pause(drm_via_private_t *dev_priv);

59 static void via_cmdbuf_reset(drm_via_private_t *dev_priv);

60 static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);

61 static int via_wait_idle(drm_via_private_t *dev_priv);

62 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);

65 /*

66 * Free space in command buffer.

67 */

69 static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv)

70 {

71 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

72 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;

74 return ((hw_addr <= dev_priv->dma_low) ?

75 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :

76 (hw_addr - dev_priv->dma_low));

77 }

79 /*

80 * How much does the command regulator lag behind?

81 */

83 static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv)

84 {

85 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

86 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;

88 return ((hw_addr <= dev_priv->dma_low) ?

89 (dev_priv->dma_low - hw_addr) :

90 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));

91 }

93 /*

94 * Check that the given size fits in the buffer, otherwise wait.

95 */

97 static inline int

98 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)

99 {

100 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

101 uint32_t cur_addr, hw_addr, next_addr;

102 volatile uint32_t *hw_addr_ptr;

103 uint32_t count;

104 hw_addr_ptr = dev_priv->hw_addr_ptr;

105 cur_addr = dev_priv->dma_low;

106 next_addr = cur_addr + size + 512 * 1024;

107 count = 1000000;

108 do {

109 hw_addr = *hw_addr_ptr - agp_base;

110 if (count-- == 0) {

111 DRM_ERROR

112 ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",

113 hw_addr, cur_addr, next_addr);

114 return -1;

115 }

116 } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));

117 return 0;

118 }

119

120

121 /*

122 * Checks whether buffer head has reach the end. Rewind the ring buffer

123 * when necessary.

124 *

125 * Returns virtual pointer to ring buffer.

126 */

127

128 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,

129 unsigned int size)

130 {

131 if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >

132 dev_priv->dma_high) {

133 via_cmdbuf_rewind(dev_priv);

134 }

135 if (via_cmdbuf_wait(dev_priv, size) != 0) {

136 return NULL;

137 }

138

139 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);

140 }

141

142 int via_dma_cleanup(struct drm_device * dev)

143 {

144 if (dev->dev_private) {

145 drm_via_private_t *dev_priv =

146 (drm_via_private_t *) dev->dev_private;

147

148 if (dev_priv->ring.virtual_start) {

149 via_cmdbuf_reset(dev_priv);

150

151 drm_core_ioremapfree(&dev_priv->ring.map, dev);

152 dev_priv->ring.virtual_start = NULL;

153 }

154

155 }

156

157 return 0;

158 }

159

160 static int via_initialize(struct drm_device * dev,

161 drm_via_private_t * dev_priv,

162 drm_via_dma_init_t * init)

163 {

164 if (!dev_priv || !dev_priv->mmio) {

165 DRM_ERROR("via_dma_init called before via_map_init\n");

166 return -EFAULT;

167 }

168

169 if (dev_priv->ring.virtual_start != NULL) {

170 DRM_ERROR("%s called again without calling cleanup\n",

171 __FUNCTION__);

172 return -EFAULT;

173 }

174

175 if (!dev->agp || !dev->agp->base) {

176 DRM_ERROR("%s called with no agp memory available\n",

177 __FUNCTION__);

178 return -EFAULT;

179 }

180

181 if (dev_priv->chipset == VIA_DX9_0) {

182 DRM_ERROR("AGP DMA is not supported on this chip\n");

183 return -EINVAL;

184 }

185

186 dev_priv->ring.map.offset = dev->agp->base + init->offset;

187 dev_priv->ring.map.size = init->size;

188 dev_priv->ring.map.type = 0;

189 dev_priv->ring.map.flags = 0;

190 dev_priv->ring.map.mtrr = 0;

191

192 drm_core_ioremap(&dev_priv->ring.map, dev);

193

194 if (dev_priv->ring.map.handle == NULL) {

195 via_dma_cleanup(dev);

196 DRM_ERROR("can not ioremap virtual address for"

197 " ring buffer\n");

198 return -ENOMEM;

199 }

200

201 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;

202

203 dev_priv->dma_ptr = dev_priv->ring.virtual_start;

204 dev_priv->dma_low = 0;

205 dev_priv->dma_high = init->size;

206 dev_priv->dma_wrap = init->size;

207 dev_priv->dma_offset = init->offset;

208 dev_priv->last_pause_ptr = NULL;

209 dev_priv->hw_addr_ptr =

210 (volatile uint32_t *)((char *)dev_priv->mmio->handle +

211 init->reg_pause_addr);

212

213 via_cmdbuf_start(dev_priv);

214

215 return 0;

216 }

217

218 static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv)

219 {

220 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;

221 drm_via_dma_init_t *init = data;

222 int retcode = 0;

223

224 switch (init->func) {

225 case VIA_INIT_DMA:

226 if (!DRM_SUSER(DRM_CURPROC))

227 retcode = -EPERM;

228 else

229 retcode = via_initialize(dev, dev_priv, init);

230 break;

231 case VIA_CLEANUP_DMA:

232 if (!DRM_SUSER(DRM_CURPROC))

233 retcode = -EPERM;

234 else

235 retcode = via_dma_cleanup(dev);

236 break;

237 case VIA_DMA_INITIALIZED:

238 retcode = (dev_priv->ring.virtual_start != NULL) ?

239 0 : -EFAULT;

240 break;

241 default:

242 retcode = -EINVAL;

243 break;

244 }

245

246 return retcode;

247 }

248

249

250

251 static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd)

252 {

253 drm_via_private_t *dev_priv;

254 uint32_t *vb;

255 int ret;

256

257 dev_priv = (drm_via_private_t *) dev->dev_private;

258

259 if (dev_priv->ring.virtual_start == NULL) {

260 DRM_ERROR("%s called without initializing AGP ring buffer.\n",

261 __FUNCTION__);

262 return -EFAULT;

263 }

264

265 if (cmd->size > VIA_PCI_BUF_SIZE) {

266 return -ENOMEM;

267 }

268

269 if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))

270 return -EFAULT;

271

272 /*

273 * Running this function on AGP memory is dead slow. Therefore

274 * we run it on a temporary cacheable system memory buffer and

275 * copy it to AGP memory when ready.

276 */

277

278 if ((ret =

279 via_verify_command_stream((uint32_t *)dev_priv->pci_buf,

280 cmd->size, dev, 1))) {

281 return ret;

282 }

283

284 vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);

285 if (vb == NULL) {

286 return -EAGAIN;

287 }

288

289 memcpy(vb, dev_priv->pci_buf, cmd->size);

290

291 dev_priv->dma_low += cmd->size;

292

293 /*

294 * Small submissions somehow stalls the CPU. (AGP cache effects?)

295 * pad to greater size.

296 */

297

298 if (cmd->size < 0x100)

299 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);

300 via_cmdbuf_pause(dev_priv);

301

302 return 0;

303 }

304

305 int via_driver_dma_quiescent(struct drm_device * dev)

306 {

307 drm_via_private_t *dev_priv = dev->dev_private;

308

309 if (!via_wait_idle(dev_priv)) {

310 return -EBUSY;

311 }

312 return 0;

313 }

314

315 static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)

316 {

317

318 LOCK_TEST_WITH_RETURN(dev, file_priv);

319

320 return via_driver_dma_quiescent(dev);

321 }

322

323 static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)

324 {

325 drm_via_cmdbuffer_t *cmdbuf = data;

326 int ret;

327

328 LOCK_TEST_WITH_RETURN(dev, file_priv);

329

330 DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf->buf,

331 cmdbuf->size);

332

333 ret = via_dispatch_cmdbuffer(dev, cmdbuf);

334 if (ret) {

335 return ret;

336 }

337

338 return 0;

339 }

340

341 static int via_dispatch_pci_cmdbuffer(struct drm_device * dev,

342 drm_via_cmdbuffer_t * cmd)

343 {

344 drm_via_private_t *dev_priv = dev->dev_private;

345 int ret;

346

347 if (cmd->size > VIA_PCI_BUF_SIZE) {

348 return -ENOMEM;

349 }

350 if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))

351 return -EFAULT;

352

353 if ((ret =

354 via_verify_command_stream((uint32_t *) dev_priv->pci_buf,

355 cmd->size, dev, 0))) {

356 return ret;

357 }

358

359 ret =

360 via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,

361 cmd->size);

362 return ret;

363 }

364

365 static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)

366 {

367 drm_via_cmdbuffer_t *cmdbuf = data;

368 int ret;

369

370 LOCK_TEST_WITH_RETURN(dev, file_priv);

371

372 DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf->buf,

373 cmdbuf->size);

374

375 ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf);

376 if (ret) {

377 return ret;

378 }

379

380 return 0;

381 }

382

383 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,

384 uint32_t * vb, int qw_count)

385 {

386 for (; qw_count > 0; --qw_count) {

387 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);

388 }

389 return vb;

390 }

391

392 /*

393 * This function is used internally by ring buffer mangement code.

394 *

395 * Returns virtual pointer to ring buffer.

396 */

397 static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)

398 {

399 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);

400 }

401

402 /*

403 * Hooks a segment of data into the tail of the ring-buffer by

404 * modifying the pause address stored in the buffer itself. If

405 * the regulator has already paused, restart it.

406 */

407 static int via_hook_segment(drm_via_private_t * dev_priv,

408 uint32_t pause_addr_hi, uint32_t pause_addr_lo,

409 int no_pci_fire)

410 {

411 int paused, count;

412 volatile uint32_t *paused_at = dev_priv->last_pause_ptr;

413 uint32_t reader,ptr;

414

415 paused = 0;

416 via_flush_write_combine();

417 (void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1);

418 *paused_at = pause_addr_lo;

419 via_flush_write_combine();

420 (void) *paused_at;

421 reader = *(dev_priv->hw_addr_ptr);

422 ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +

423 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;

424 dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;

425

426 if ((ptr - reader) <= dev_priv->dma_diff ) {

427 count = 10000000;

428 while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);

429 }

430

431 if (paused && !no_pci_fire) {

432 reader = *(dev_priv->hw_addr_ptr);

433 if ((ptr - reader) == dev_priv->dma_diff) {

434

435 /*

436 * There is a concern that these writes may stall the PCI bus

437 * if the GPU is not idle. However, idling the GPU first

438 * doesn't make a difference.

439 */

440

441 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));

442 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);

443 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);

444 VIA_READ(VIA_REG_TRANSPACE);

445 }

446 }

447

448 return paused;

449 }

450

451

452

453 static int via_wait_idle(drm_via_private_t *dev_priv)

454 {

455 int count = 10000000;

456

457 while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--);

458

459 while (count-- && (VIA_READ(VIA_REG_STATUS) &

460 (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |

461 VIA_3D_ENG_BUSY))) ;

462 return count;

463 }

464

465 static uint32_t *via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type,

466 uint32_t addr, uint32_t *cmd_addr_hi,

467 uint32_t *cmd_addr_lo, int skip_wait)

468 {

469 uint32_t agp_base;

470 uint32_t cmd_addr, addr_lo, addr_hi;

471 uint32_t *vb;

472 uint32_t qw_pad_count;

473

474 if (!skip_wait)

475 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);

476

477 vb = via_get_dma(dev_priv);

478 VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |

479 (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);

480

481 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

482 qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -

483 ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);

484

485 cmd_addr = (addr) ? addr :

486 agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);

487 addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |

488 (cmd_addr & HC_HAGPBpL_MASK));

489 addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));

490

491 vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);

492 VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);

493 return vb;

494 }

495

496 static void via_cmdbuf_start(drm_via_private_t * dev_priv)

497 {

498 uint32_t pause_addr_lo, pause_addr_hi;

499 uint32_t start_addr, start_addr_lo;

500 uint32_t end_addr, end_addr_lo;

501 uint32_t command;

502 uint32_t agp_base;

503 uint32_t ptr;

504 uint32_t reader;

505 int count;

506

507 dev_priv->dma_low = 0;

508

509 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

510 start_addr = agp_base;

511 end_addr = agp_base + dev_priv->dma_high;

512

513 start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));

514 end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));

515 command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |

516 ((end_addr & 0xff000000) >> 16));

517

518 dev_priv->last_pause_ptr =

519 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,

520 &pause_addr_hi, & pause_addr_lo, 1) - 1;

521

522 via_flush_write_combine();

523 (void) *(volatile uint32_t *)dev_priv->last_pause_ptr;

524

525 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));

526 VIA_WRITE(VIA_REG_TRANSPACE, command);

527 VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);

528 VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);

529

530 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);

531 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);

532 DRM_WRITEMEMORYBARRIER();

533 VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);

534 VIA_READ(VIA_REG_TRANSPACE);

535

536 dev_priv->dma_diff = 0;

537

538 count = 10000000;

539 while (!(VIA_READ(0x41c) & 0x80000000) && count--);

540

541 reader = *(dev_priv->hw_addr_ptr);

542 ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +

543 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;

544

545 /*

546 * This is the difference between where we tell the

547 * command reader to pause and where it actually pauses.

548 * This differs between hw implementation so we need to

549 * detect it.

550 */

551

552 dev_priv->dma_diff = ptr - reader;

553 }

554

555 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords)

556 {

557 uint32_t *vb;

558

559 via_cmdbuf_wait(dev_priv, qwords + 2);

560 vb = via_get_dma(dev_priv);

561 VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);

562 via_align_buffer(dev_priv, vb, qwords);

563 }

564

565 static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)

566 {

567 uint32_t *vb = via_get_dma(dev_priv);

568 SetReg2DAGP(0x0C, (0 | (0 << 16)));

569 SetReg2DAGP(0x10, 0 | (0 << 16));

570 SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);

571 }

572

573 static void via_cmdbuf_jump(drm_via_private_t * dev_priv)

574 {

575 uint32_t agp_base;

576 uint32_t pause_addr_lo, pause_addr_hi;

577 uint32_t jump_addr_lo, jump_addr_hi;

578 volatile uint32_t *last_pause_ptr;

579

580 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;

581 via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,

582 &jump_addr_lo, 0);

583

584 dev_priv->dma_wrap = dev_priv->dma_low;

585

586

587 /*

588 * Wrap command buffer to the beginning.

589 */

590

591 dev_priv->dma_low = 0;

592 if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {

593 DRM_ERROR("via_cmdbuf_jump failed\n");

594 }

595

596 via_dummy_bitblt(dev_priv);

597 via_dummy_bitblt(dev_priv);

598 last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,

599 &pause_addr_lo, 0) -1;

600 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,

601 &pause_addr_lo, 0);

602 *last_pause_ptr = pause_addr_lo;

603

604 via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);

605 }

606

607 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)

608 {

609 via_cmdbuf_jump(dev_priv);

610 }

611

612 static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)

613 {

614 uint32_t pause_addr_lo, pause_addr_hi;

615

616 via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);

617 via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);

618 }

619

620

621 static void via_cmdbuf_pause(drm_via_private_t * dev_priv)

622 {

623 via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);

624 }

625

626 static void via_cmdbuf_reset(drm_via_private_t * dev_priv)

627 {

628 via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);

629 via_wait_idle(dev_priv);

630 }

631

632 /*

633 * User interface to the space and lag functions.

634 */

635

636 static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv)

637 {

638 drm_via_cmdbuf_size_t *d_siz = data;

639 int ret = 0;

640 uint32_t tmp_size, count;

641 drm_via_private_t *dev_priv;

642

643 DRM_DEBUG("via cmdbuf_size\n");

644 LOCK_TEST_WITH_RETURN(dev, file_priv);

645

646 dev_priv = (drm_via_private_t *) dev->dev_private;

647

648 if (dev_priv->ring.virtual_start == NULL) {

649 DRM_ERROR("%s called without initializing AGP ring buffer.\n",

650 __FUNCTION__);

651 return -EFAULT;

652 }

653

654 count = 1000000;

655 tmp_size = d_siz->size;

656 switch (d_siz->func) {

657 case VIA_CMDBUF_SPACE:

658 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size)

659 && count--) {

660 if (!d_siz->wait) {

661 break;

662 }

663 }

664 if (!count) {

665 DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");

666 ret = -EAGAIN;

667 }

668 break;

669 case VIA_CMDBUF_LAG:

670 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size)

671 && count--) {

672 if (!d_siz->wait) {

673 break;

674 }

675 }

676 if (!count) {

677 DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");

678 ret = -EAGAIN;

679 }

680 break;

681 default:

682 ret = -EFAULT;

683 }

684 d_siz->size = tmp_size;

685

686 return ret;

687 }

688

689 #ifndef VIA_HAVE_DMABLIT

690 int

691 via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv ) {

692 DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");

693 return -EINVAL;

694 }

695 int

696 via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv ) {

697 DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");

698 return -EINVAL;

699 }

700 #endif

701

702 struct drm_ioctl_desc via_ioctls[] = {

703 DRM_IOCTL_DEF(DRM_VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH),

704 DRM_IOCTL_DEF(DRM_VIA_FREEMEM, via_mem_free, DRM_AUTH),

705 DRM_IOCTL_DEF(DRM_VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER),

706 DRM_IOCTL_DEF(DRM_VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER),

707 DRM_IOCTL_DEF(DRM_VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER),

708 DRM_IOCTL_DEF(DRM_VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH),

709 DRM_IOCTL_DEF(DRM_VIA_DMA_INIT, via_dma_init, DRM_AUTH),

710 DRM_IOCTL_DEF(DRM_VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH),

711 DRM_IOCTL_DEF(DRM_VIA_FLUSH, via_flush_ioctl, DRM_AUTH),

712 DRM_IOCTL_DEF(DRM_VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH),

713 DRM_IOCTL_DEF(DRM_VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH),

714 DRM_IOCTL_DEF(DRM_VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH),

715 DRM_IOCTL_DEF(DRM_VIA_DMA_BLIT, via_dma_blit, DRM_AUTH),

716 DRM_IOCTL_DEF(DRM_VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH)

717 };

718

719 int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);