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1 /* via_irq.c

2 *

7 *

8 * Permission is hereby granted, free of charge, to any person obtaining a

9 * copy of this software and associated documentation files (the "Software"),

10 * to deal in the Software without restriction, including without limitation

11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

12 * and/or sell copies of the Software, and to permit persons to whom the

13 * Software is furnished to do so, subject to the following conditions:

14 *

15 * The above copyright notice and this permission notice (including the next

16 * paragraph) shall be included in all copies or substantial portions of the

17 * Software.

18 *

19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

22 * BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,

23 * DAMAGES OR

24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

26 * DEALINGS IN THE SOFTWARE.

27 *

28 * Authors:

29 * Terry Barnaby <terry1@beam.ltd.uk>

30 * Keith Whitwell <keith@tungstengraphics.com>

31 * Thomas Hellstrom <unichrome@shipmail.org>

32 *

33 * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank

34 * interrupt, as well as an infrastructure to handle other interrupts of the chip.

35 * The refresh rate is also calculated for video playback sync purposes.

36 */

38 #include "drmP.h"

39 #include "drm.h"

40 #include "via_drm.h"

41 #include "via_drv.h"

43 #define VIA_REG_INTERRUPT 0x200

45 /* VIA_REG_INTERRUPT */

46 #define VIA_IRQ_GLOBAL (1 << 31)

47 #define VIA_IRQ_VBLANK_ENABLE (1 << 19)

48 #define VIA_IRQ_VBLANK_PENDING (1 << 3)

49 #define VIA_IRQ_HQV0_ENABLE (1 << 11)

50 #define VIA_IRQ_HQV1_ENABLE (1 << 25)

51 #define VIA_IRQ_HQV0_PENDING (1 << 9)

52 #define VIA_IRQ_HQV1_PENDING (1 << 10)

53 #define VIA_IRQ_DMA0_DD_ENABLE (1 << 20)

54 #define VIA_IRQ_DMA0_TD_ENABLE (1 << 21)

55 #define VIA_IRQ_DMA1_DD_ENABLE (1 << 22)

56 #define VIA_IRQ_DMA1_TD_ENABLE (1 << 23)

57 #define VIA_IRQ_DMA0_DD_PENDING (1 << 4)

58 #define VIA_IRQ_DMA0_TD_PENDING (1 << 5)

59 #define VIA_IRQ_DMA1_DD_PENDING (1 << 6)

60 #define VIA_IRQ_DMA1_TD_PENDING (1 << 7)

63 /*

64 * Device-specific IRQs go here. This type might need to be extended with

65 * the register if there are multiple IRQ control registers.

66 * Currently we activate the HQV interrupts of Unichrome Pro group A.

67 */

69 static maskarray_t via_pro_group_a_irqs[] = {

70 {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,

71 0x00000000 },

72 {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,

73 0x00000000 },

74 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,

75 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},

76 {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,

77 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},

78 };

79 static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);

80 static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};

82 static maskarray_t via_unichrome_irqs[] = {

83 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,

84 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},

85 {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,

86 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}

87 };

88 static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);

89 static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};

92 static unsigned time_diff(struct timeval *now,struct timeval *then)

93 {

94 return (now->tv_usec >= then->tv_usec) ?

95 now->tv_usec - then->tv_usec :

96 1000000 - (then->tv_usec - now->tv_usec);

97 }

99 u32 via_get_vblank_counter(struct drm_device *dev, int crtc)

100 {

101 drm_via_private_t *dev_priv = dev->dev_private;

102 if (crtc != 0)

103 return 0;

104

105 return atomic_read(&dev_priv->vbl_received);

106 }

107

108 irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)

109 {

110 struct drm_device *dev = (struct drm_device *) arg;

111 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;

112 u32 status;

113 int handled = 0;

114 struct timeval cur_vblank;

115 drm_via_irq_t *cur_irq = dev_priv->via_irqs;

116 int i;

117

118 status = VIA_READ(VIA_REG_INTERRUPT);

119 if (status & VIA_IRQ_VBLANK_PENDING) {

120 atomic_inc(&dev_priv->vbl_received);

121 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {

122 #ifdef __linux__

123 do_gettimeofday(&cur_vblank);

124 #else

125 microtime(&cur_vblank);

126 #endif

127 if (dev_priv->last_vblank_valid) {

128 dev_priv->usec_per_vblank =

129 time_diff(&cur_vblank,

130 &dev_priv->last_vblank) >> 4;

131 }

132 dev_priv->last_vblank = cur_vblank;

133 dev_priv->last_vblank_valid = 1;

134 }

135 if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) {

136 DRM_DEBUG("US per vblank is: %u\n",

137 dev_priv->usec_per_vblank);

138 }

139 drm_handle_vblank(dev, 0);

140 handled = 1;

141 }

142

143 for (i = 0; i < dev_priv->num_irqs; ++i) {

144 if (status & cur_irq->pending_mask) {

145 atomic_inc(&cur_irq->irq_received);

146 DRM_WAKEUP(&cur_irq->irq_queue);

147 handled = 1;

148 #ifdef VIA_HAVE_DMABLIT

149 if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) {

150 via_dmablit_handler(dev, 0, 1);

151 } else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) {

152 via_dmablit_handler(dev, 1, 1);

153 }

154 #endif

155 }

156 cur_irq++;

157 }

158

159 /* Acknowlege interrupts */

160 VIA_WRITE(VIA_REG_INTERRUPT, status);

161

162

163 if (handled)

164 return IRQ_HANDLED;

165 else

166 return IRQ_NONE;

167 }

168

169 static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)

170 {

171 u32 status;

172

173 if (dev_priv) {

174 /* Acknowlege interrupts */

175 status = VIA_READ(VIA_REG_INTERRUPT);

176 VIA_WRITE(VIA_REG_INTERRUPT, status |

177 dev_priv->irq_pending_mask);

178 }

179 }

180

181 int via_enable_vblank(struct drm_device *dev, int crtc)

182 {

183 drm_via_private_t *dev_priv = dev->dev_private;

184 u32 status;

185

186 if (crtc != 0) {

187 DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc);

188 return -EINVAL;

189 }

190

191 status = VIA_READ(VIA_REG_INTERRUPT);

192 VIA_WRITE(VIA_REG_INTERRUPT, status & VIA_IRQ_VBLANK_ENABLE);

193 return 0;

194 }

195

196 void via_disable_vblank(struct drm_device *dev, int crtc)

197 {

198 if (crtc != 0)

199 DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc);

200 }

201

202 static int

203 via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequence,

204 unsigned int *sequence)

205 {

206 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;

207 unsigned int cur_irq_sequence;

208 drm_via_irq_t *cur_irq;

209 int ret = 0;

210 maskarray_t *masks;

211 int real_irq;

212

213 DRM_DEBUG("\n");

214

215 if (!dev_priv) {

216 DRM_ERROR("called with no initialization\n");

217 return -EINVAL;

218 }

219

220 if (irq >= drm_via_irq_num) {

221 DRM_ERROR("Trying to wait on unknown irq %d\n", irq);

222 return -EINVAL;

223 }

224

225 real_irq = dev_priv->irq_map[irq];

226

227 if (real_irq < 0) {

228 DRM_ERROR("Video IRQ %d not available on this hardware.\n",

229 irq);

230 return -EINVAL;

231 }

232

233 masks = dev_priv->irq_masks;

234 cur_irq = dev_priv->via_irqs + real_irq;

235

236 if (masks[real_irq][2] && !force_sequence) {

237 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,

238 ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==

239 masks[irq][4]));

240 cur_irq_sequence = atomic_read(&cur_irq->irq_received);

241 } else {

242 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,

243 (((cur_irq_sequence =

244 atomic_read(&cur_irq->irq_received)) -

245 *sequence) <= (1 << 23)));

246 }

247 *sequence = cur_irq_sequence;

248 return ret;

249 }

250

251

252 /*

253 * drm_dma.h hooks

254 */

255

256 void via_driver_irq_preinstall(struct drm_device * dev)

257 {

258 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;

259 u32 status;

260 drm_via_irq_t *cur_irq;

261 int i;

262

263 DRM_DEBUG("dev_priv: %p\n", dev_priv);

264 if (dev_priv) {

265 cur_irq = dev_priv->via_irqs;

266

267 dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;

268 dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;

269

270 if (dev_priv->chipset == VIA_PRO_GROUP_A ||

271 dev_priv->chipset == VIA_DX9_0) {

272 dev_priv->irq_masks = via_pro_group_a_irqs;

273 dev_priv->num_irqs = via_num_pro_group_a;

274 dev_priv->irq_map = via_irqmap_pro_group_a;

275 } else {

276 dev_priv->irq_masks = via_unichrome_irqs;

277 dev_priv->num_irqs = via_num_unichrome;

278 dev_priv->irq_map = via_irqmap_unichrome;

279 }

280

281 for (i = 0; i < dev_priv->num_irqs; ++i) {

282 atomic_set(&cur_irq->irq_received, 0);

283 cur_irq->enable_mask = dev_priv->irq_masks[i][0];

284 cur_irq->pending_mask = dev_priv->irq_masks[i][1];

285 DRM_INIT_WAITQUEUE(&cur_irq->irq_queue);

286 dev_priv->irq_enable_mask |= cur_irq->enable_mask;

287 dev_priv->irq_pending_mask |= cur_irq->pending_mask;

288 cur_irq++;

289

290 DRM_DEBUG("Initializing IRQ %d\n", i);

291 }

292

293 dev_priv->last_vblank_valid = 0;

294

295 /* Clear VSync interrupt regs */

296 status = VIA_READ(VIA_REG_INTERRUPT);

297 VIA_WRITE(VIA_REG_INTERRUPT, status &

298 ~(dev_priv->irq_enable_mask));

299

300 /* Clear bits if they're already high */

301 viadrv_acknowledge_irqs(dev_priv);

302 }

303 }

304

305 int via_driver_irq_postinstall(struct drm_device * dev)

306 {

307 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;

308 u32 status;

309

310 DRM_DEBUG("via_driver_irq_postinstall\n");

311 if (!dev_priv)

312 return -EINVAL;

313

314 status = VIA_READ(VIA_REG_INTERRUPT);

315 VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL

316 | dev_priv->irq_enable_mask);

317

318 /* Some magic, oh for some data sheets ! */

319 VIA_WRITE8(0x83d4, 0x11);

320 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);

321

322 return 0;

323 }

324

325 void via_driver_irq_uninstall(struct drm_device * dev)

326 {

327 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;

328 u32 status;

329

330 DRM_DEBUG("\n");

331 if (dev_priv) {

332

333 /* Some more magic, oh for some data sheets ! */

334

335 VIA_WRITE8(0x83d4, 0x11);

336 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);

337

338 status = VIA_READ(VIA_REG_INTERRUPT);

339 VIA_WRITE(VIA_REG_INTERRUPT, status &

340 ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));

341 }

342 }

343

344 int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)

345 {

346 drm_via_irqwait_t *irqwait = data;

347 struct timeval now;

348 int ret = 0;

349 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;

350 drm_via_irq_t *cur_irq = dev_priv->via_irqs;

351 int force_sequence;

352

353 if (!dev->irq)

354 return -EINVAL;

355

356 if (irqwait->request.irq >= dev_priv->num_irqs) {

357 DRM_ERROR("Trying to wait on unknown irq %d\n",

358 irqwait->request.irq);

359 return -EINVAL;

360 }

361

362 cur_irq += irqwait->request.irq;

363

364 switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {

365 case VIA_IRQ_RELATIVE:

366 irqwait->request.sequence +=

367 atomic_read(&cur_irq->irq_received);

368 irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;

369 case VIA_IRQ_ABSOLUTE:

370 break;

371 default:

372 return -EINVAL;

373 }

374

375 if (irqwait->request.type & VIA_IRQ_SIGNAL) {

376 DRM_ERROR("Signals on Via IRQs not implemented yet.\n");

377 return -EINVAL;

378 }

379

380 force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);

381

382 ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,

383 &irqwait->request.sequence);

384 #ifdef __linux__

385 do_gettimeofday(&now);

386 #else

387 microtime(&now);

388 #endif

389 irqwait->reply.tval_sec = now.tv_sec;

390 irqwait->reply.tval_usec = now.tv_usec;

391

392 return ret;

393 }