3 * Copyright 2004 BEAM Ltd.
4 * Copyright 2002 Tungsten Graphics, Inc.
5 * Copyright 2005 Thomas Hellstrom.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Terry Barnaby <terry1@beam.ltd.uk>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 * Thomas Hellstrom <unichrome@shipmail.org>
33 * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
34 * interrupt, as well as an infrastructure to handle other interrupts of the chip.
35 * The refresh rate is also calculated for video playback sync purposes.
43 #define VIA_REG_INTERRUPT 0x200
45 /* VIA_REG_INTERRUPT */
46 #define VIA_IRQ_GLOBAL (1 << 31)
47 #define VIA_IRQ_VBLANK_ENABLE (1 << 19)
48 #define VIA_IRQ_VBLANK_PENDING (1 << 3)
49 #define VIA_IRQ_HQV0_ENABLE (1 << 11)
50 #define VIA_IRQ_HQV1_ENABLE (1 << 25)
51 #define VIA_IRQ_HQV0_PENDING (1 << 9)
52 #define VIA_IRQ_HQV1_PENDING (1 << 10)
53 #define VIA_IRQ_DMA0_DD_ENABLE (1 << 20)
54 #define VIA_IRQ_DMA0_TD_ENABLE (1 << 21)
55 #define VIA_IRQ_DMA1_DD_ENABLE (1 << 22)
56 #define VIA_IRQ_DMA1_TD_ENABLE (1 << 23)
57 #define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
58 #define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
59 #define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
60 #define VIA_IRQ_DMA1_TD_PENDING (1 << 7)
64 * Device-specific IRQs go here. This type might need to be extended with
65 * the register if there are multiple IRQ control registers.
66 * Currently we activate the HQV interrupts of Unichrome Pro group A.
69 static maskarray_t via_pro_group_a_irqs[] = {
70 {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
72 {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
74 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
75 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
76 {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
77 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
79 static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);
80 static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
82 static maskarray_t via_unichrome_irqs[] = {
83 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
84 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
85 {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
86 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
88 static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);
89 static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
92 static unsigned time_diff(struct timeval *now,struct timeval *then)
94 return (now->tv_usec >= then->tv_usec) ?
95 now->tv_usec - then->tv_usec :
96 1000000 - (then->tv_usec - now->tv_usec);
99 u32 via_get_vblank_counter(struct drm_device *dev, int crtc)
101 drm_via_private_t *dev_priv = dev->dev_private;
105 return atomic_read(&dev_priv->vbl_received);
108 irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
110 struct drm_device *dev = (struct drm_device *) arg;
111 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
114 struct timeval cur_vblank;
115 drm_via_irq_t *cur_irq = dev_priv->via_irqs;
118 status = VIA_READ(VIA_REG_INTERRUPT);
119 if (status & VIA_IRQ_VBLANK_PENDING) {
120 atomic_inc(&dev_priv->vbl_received);
121 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
123 do_gettimeofday(&cur_vblank);
125 microtime(&cur_vblank);
127 if (dev_priv->last_vblank_valid) {
128 dev_priv->usec_per_vblank =
129 time_diff(&cur_vblank,
130 &dev_priv->last_vblank) >> 4;
132 dev_priv->last_vblank = cur_vblank;
133 dev_priv->last_vblank_valid = 1;
135 if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) {
136 DRM_DEBUG("US per vblank is: %u\n",
137 dev_priv->usec_per_vblank);
139 drm_handle_vblank(dev, 0);
143 for (i = 0; i < dev_priv->num_irqs; ++i) {
144 if (status & cur_irq->pending_mask) {
145 atomic_inc(&cur_irq->irq_received);
146 DRM_WAKEUP(&cur_irq->irq_queue);
148 #ifdef VIA_HAVE_DMABLIT
149 if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) {
150 via_dmablit_handler(dev, 0, 1);
151 } else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) {
152 via_dmablit_handler(dev, 1, 1);
159 /* Acknowlege interrupts */
160 VIA_WRITE(VIA_REG_INTERRUPT, status);
169 static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
174 /* Acknowlege interrupts */
175 status = VIA_READ(VIA_REG_INTERRUPT);
176 VIA_WRITE(VIA_REG_INTERRUPT, status |
177 dev_priv->irq_pending_mask);
181 int via_enable_vblank(struct drm_device *dev, int crtc)
183 drm_via_private_t *dev_priv = dev->dev_private;
187 DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc);
191 status = VIA_READ(VIA_REG_INTERRUPT);
192 VIA_WRITE(VIA_REG_INTERRUPT, status & VIA_IRQ_VBLANK_ENABLE);
194 VIA_WRITE8(0x83d4, 0x11);
195 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
200 void via_disable_vblank(struct drm_device *dev, int crtc)
202 drm_via_private_t *dev_priv = dev->dev_private;
204 VIA_WRITE8(0x83d4, 0x11);
205 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
208 DRM_ERROR("%s: bad crtc %d\n", __FUNCTION__, crtc);
212 via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequence,
213 unsigned int *sequence)
215 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
216 unsigned int cur_irq_sequence;
217 drm_via_irq_t *cur_irq;
225 DRM_ERROR("called with no initialization\n");
229 if (irq >= drm_via_irq_num) {
230 DRM_ERROR("Trying to wait on unknown irq %d\n", irq);
234 real_irq = dev_priv->irq_map[irq];
237 DRM_ERROR("Video IRQ %d not available on this hardware.\n",
242 masks = dev_priv->irq_masks;
243 cur_irq = dev_priv->via_irqs + real_irq;
245 if (masks[real_irq][2] && !force_sequence) {
246 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
247 ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
249 cur_irq_sequence = atomic_read(&cur_irq->irq_received);
251 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
252 (((cur_irq_sequence =
253 atomic_read(&cur_irq->irq_received)) -
254 *sequence) <= (1 << 23)));
256 *sequence = cur_irq_sequence;
265 void via_driver_irq_preinstall(struct drm_device * dev)
267 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
269 drm_via_irq_t *cur_irq;
272 DRM_DEBUG("dev_priv: %p\n", dev_priv);
274 cur_irq = dev_priv->via_irqs;
276 dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
277 dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
279 if (dev_priv->chipset == VIA_PRO_GROUP_A ||
280 dev_priv->chipset == VIA_DX9_0) {
281 dev_priv->irq_masks = via_pro_group_a_irqs;
282 dev_priv->num_irqs = via_num_pro_group_a;
283 dev_priv->irq_map = via_irqmap_pro_group_a;
285 dev_priv->irq_masks = via_unichrome_irqs;
286 dev_priv->num_irqs = via_num_unichrome;
287 dev_priv->irq_map = via_irqmap_unichrome;
290 for (i = 0; i < dev_priv->num_irqs; ++i) {
291 atomic_set(&cur_irq->irq_received, 0);
292 cur_irq->enable_mask = dev_priv->irq_masks[i][0];
293 cur_irq->pending_mask = dev_priv->irq_masks[i][1];
294 DRM_INIT_WAITQUEUE(&cur_irq->irq_queue);
295 dev_priv->irq_enable_mask |= cur_irq->enable_mask;
296 dev_priv->irq_pending_mask |= cur_irq->pending_mask;
299 DRM_DEBUG("Initializing IRQ %d\n", i);
302 dev_priv->last_vblank_valid = 0;
304 /* Clear VSync interrupt regs */
305 status = VIA_READ(VIA_REG_INTERRUPT);
306 VIA_WRITE(VIA_REG_INTERRUPT, status &
307 ~(dev_priv->irq_enable_mask));
309 /* Clear bits if they're already high */
310 viadrv_acknowledge_irqs(dev_priv);
314 int via_driver_irq_postinstall(struct drm_device * dev)
316 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
319 DRM_DEBUG("via_driver_irq_postinstall\n");
323 status = VIA_READ(VIA_REG_INTERRUPT);
324 VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
325 | dev_priv->irq_enable_mask);
327 /* Some magic, oh for some data sheets ! */
328 VIA_WRITE8(0x83d4, 0x11);
329 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
334 void via_driver_irq_uninstall(struct drm_device * dev)
336 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
342 /* Some more magic, oh for some data sheets ! */
344 VIA_WRITE8(0x83d4, 0x11);
345 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
347 status = VIA_READ(VIA_REG_INTERRUPT);
348 VIA_WRITE(VIA_REG_INTERRUPT, status &
349 ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
353 int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
355 drm_via_irqwait_t *irqwait = data;
358 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
359 drm_via_irq_t *cur_irq = dev_priv->via_irqs;
365 if (irqwait->request.irq >= dev_priv->num_irqs) {
366 DRM_ERROR("Trying to wait on unknown irq %d\n",
367 irqwait->request.irq);
371 cur_irq += irqwait->request.irq;
373 switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
374 case VIA_IRQ_RELATIVE:
375 irqwait->request.sequence +=
376 atomic_read(&cur_irq->irq_received);
377 irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
378 case VIA_IRQ_ABSOLUTE:
384 if (irqwait->request.type & VIA_IRQ_SIGNAL) {
385 DRM_ERROR("Signals on Via IRQs not implemented yet.\n");
389 force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);
391 ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
392 &irqwait->request.sequence);
394 do_gettimeofday(&now);
398 irqwait->reply.tval_sec = now.tv_sec;
399 irqwait->reply.tval_usec = now.tv_usec;