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drm/i915/pmu: Fix synchronization of PMU callback with reset
authorUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Mon, 8 Nov 2021 21:10:57 +0000 (13:10 -0800)
committerJohn Harrison <John.C.Harrison@Intel.com>
Wed, 1 Dec 2021 01:08:07 +0000 (17:08 -0800)
commit2a67b18e67f30b526ce69b7796a16d847e94e2df
tree0eadf690d47ac0745d2dd3d2c99e84abbb9c7712
parent95d35838880fb040ccb9fe4a48816bd0c8b62df5
drm/i915/pmu: Fix synchronization of PMU callback with reset

Since the PMU callback runs in irq context, it synchronizes with gt
reset using the reset count. We could run into a case where the PMU
callback could read the reset count before it is updated. This has a
potential of corrupting the busyness stats.

In addition to the reset count, check if the reset bit is set before
capturing busyness.

In addition save the previous stats only if you intend to update them.

v2:
- The 2 reset counts captured in the PMU callback can end up being the
  same if they were captured right after the count is incremented in the
  reset flow. This can lead to a bad busyness state. Ensure that reset
  is not in progress when the initial reset count is captured.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211108211057.68783-1-umesh.nerlige.ramappa@intel.com
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c