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x86/amd: Fix L1i and L2 cache sharing information for AMD family 15h processors
authorAndreas Herrmann <andreas.herrmann3@amd.com>
Wed, 8 Feb 2012 19:52:29 +0000 (20:52 +0100)
committerIngo Molnar <mingo@elte.hu>
Thu, 9 Feb 2012 08:38:15 +0000 (09:38 +0100)
commit32c3233885eb10ac9cb9410f2f8cd64b8df2b2a1
treef3267d1cff7d7d42824b51920f00fd47a03e19c5
parentc1d2f1bccf4259384e581b937e694ee8a350fe55
x86/amd: Fix L1i and L2 cache sharing information for AMD family 15h processors

For L1 instruction cache and L2 cache the shared CPU information
is wrong. On current AMD family 15h CPUs those caches are shared
between both cores of a compute unit.

This fixes https://bugzilla.kernel.org/show_bug.cgi?id=42607

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Petkov Borislav <Borislav.Petkov@amd.com>
Cc: Dave Jones <davej@redhat.com>
Cc: <stable@kernel.org>
Link: http://lkml.kernel.org/r/20120208195229.GA17523@alberich.amd.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/intel_cacheinfo.c