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clk: sunxi-ng: Adjust MP clock parent rate when allowed
authorJernej Skrabec <jernej.skrabec@siol.net>
Sun, 4 Nov 2018 18:26:39 +0000 (19:26 +0100)
committerMaxime Ripard <maxime.ripard@bootlin.com>
Mon, 5 Nov 2018 09:21:01 +0000 (10:21 +0100)
commit3f790433c3cb27ecaf2ca0e07ac25964e4fd9f15
tree34c84be8f9a331bbebdfa40ac7bd46ef427d61b1
parentdb7548934603d9eda12649dff97ea5c29884405d
clk: sunxi-ng: Adjust MP clock parent rate when allowed

Currently MP clocks don't consider adjusting parent rate even if they
are allowed to do so. Such behaviour considerably lowers amount of
possible rates, which is very inconvenient when such clock is used for
pixel clock, for example.

In order to improve the situation, adjusting parent rate is considered
when allowed.

This code is inspired by clk_divider_bestdiv() function, which does
basically the same thing for different clock type.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
drivers/clk/sunxi-ng/ccu_mp.c