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arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC
authorDinh Nguyen <dinguyen@opensource.altera.com>
Thu, 4 Sep 2014 21:45:56 +0000 (16:45 -0500)
committerDinh Nguyen <dinguyen@opensource.altera.com>
Fri, 21 Nov 2014 05:08:42 +0000 (23:08 -0600)
commit475dc86d08de4af61b6e8524bbcdbf8d675cb4fa
tree499b98442fdd1c59461e1d10f057f2836fa25ba8
parentc1ad85d77224b91448761a3f0ab0d14459c7bb44
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC

The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10
SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there
are enough differences to warrant a new base dtsi.

The differences are:
* 3 EMAC controllers
* 5 I2C controllers
* 3 SPI controllers
* 1.5 GHZ dual A9s
* Support for DDR4

Besides the usual memory map and IRQ changes, the clock framework will be
different, so this patch just adds the fixed-clocks.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/socfpga_arria10.dtsi [new file with mode: 0644]
arch/arm/boot/dts/socfpga_arria10_socdk.dts [new file with mode: 0755]