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(parent: 855d4ca) | patch
dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller
authorLiu Peibao <liupeibao@loongson.cn>
Mon, 14 Nov 2022 11:38:24 +0000 (19:38 +0800)
committerMarc Zyngier <maz@kernel.org>
Sat, 26 Nov 2022 11:54:11 +0000 (11:54 +0000)
commit6b2748ada244c7597e9b677a0bdda4e8781a8d8f
tree88d42dda6f6ed3777d6e0b206dfdc1b8eec1bc38tree | snapshot
parent855d4ca4bdb366aab3d43408b74e02ab629d1d55commit | diff
dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller

Current LoongArch compatible CPUs support 14 CPU IRQs. We can describe how
the 14 IRQs are wired to the platform's internal interrupt controller by
devicetree.

Signed-off-by: Liu Peibao <liupeibao@loongson.cn>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221114113824.1880-3-liupeibao@loongson.cn
Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml [new file with mode: 0644] blob
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