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[AArch64][GlobalISel] Don't use explicit zero registers for compare results.
authorAmara Emerson <amara@apple.com>
Wed, 14 Oct 2020 19:32:33 +0000 (12:32 -0700)
committerAmara Emerson <amara@apple.com>
Wed, 14 Oct 2020 23:49:33 +0000 (16:49 -0700)
commit78ccb0359d8da3269636d85933dd8afe50a2211f
tree2af31c81ac67adc05b30c6973331bd12a6418eb5
parent8b6d1c0467b2dfa14cb2d2dec7637bf95c78364b
[AArch64][GlobalISel] Don't use explicit zero registers for compare results.

These cause problems for later optimizations, just using an unused vreg like
SelectionDAG generates better code in the end, and obviates the need for some
GISel specific flag optimizations.

Differential Revision: https://reviews.llvm.org/D89419
16 files changed:
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
llvm/test/CodeGen/AArch64/GlobalISel/opt-shifted-reg-compare.mir
llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-arith-immed-compare.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/select.mir
llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir