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clk: imx7d: Fix the powerdown bit location of PLL DDR
authorFabio Estevam <fabio.estevam@nxp.com>
Mon, 15 May 2017 11:55:05 +0000 (08:55 -0300)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 1 Jun 2017 07:25:38 +0000 (00:25 -0700)
commitad14972422899b620fb594789824f0871dfb788c
tree949897fde1a7c049d9fd9ec8d2eb4255dcd65a78
parent9593f4f56cf5d1c443f66660a0c7f01de38f979d
clk: imx7d: Fix the powerdown bit location of PLL DDR

According to the MX7D Reference Manual the powerdown bit of
CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/imx/clk-imx7d.c
drivers/clk/imx/clk-pllv3.c
drivers/clk/imx/clk.h