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1 // SPDX-License-Identifier: MIT

2 /*

4 *

5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>

6 * Manasi Navare <manasi.d.navare@intel.com>

7 */

8 #include <linux/limits.h>

9 #include "i915_drv.h"

10 #include "intel_de.h"

11 #include "intel_display_types.h"

12 #include "intel_dsi.h"

13 #include "intel_vdsc.h"

14 #include "intel_qp_tables.h"

15

16 enum ROW_INDEX_BPP {

17 ROW_INDEX_6BPP = 0,

18 ROW_INDEX_8BPP,

19 ROW_INDEX_10BPP,

20 ROW_INDEX_12BPP,

21 ROW_INDEX_15BPP,

22 MAX_ROW_INDEX

23 };

24

25 enum COLUMN_INDEX_BPC {

26 COLUMN_INDEX_8BPC = 0,

27 COLUMN_INDEX_10BPC,

28 COLUMN_INDEX_12BPC,

29 COLUMN_INDEX_14BPC,

30 COLUMN_INDEX_16BPC,

31 MAX_COLUMN_INDEX

32 };

33

34 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */

35 static const u16 rc_buf_thresh[] = {

36 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,

37 7744, 7872, 8000, 8064

38 };

39

40 struct rc_parameters {

41 u16 initial_xmit_delay;

42 u8 first_line_bpg_offset;

43 u16 initial_offset;

44 u8 flatness_min_qp;

45 u8 flatness_max_qp;

46 u8 rc_quant_incr_limit0;

47 u8 rc_quant_incr_limit1;

48 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];

49 };

50

51 /*

52 * Selected Rate Control Related Parameter Recommended Values

53 * from DSC_v1.11 spec & C Model release: DSC_model_20161212

54 */

55 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {

56 {

57 /* 6BPP/8BPC */

58 { 768, 15, 6144, 3, 13, 11, 11, {

59 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },

60 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },

61 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },

62 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }

63 }

64 },

65 /* 6BPP/10BPC */

66 { 768, 15, 6144, 7, 17, 15, 15, {

67 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },

68 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },

69 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },

70 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },

71 { 17, 18, -12 }

72 }

73 },

74 /* 6BPP/12BPC */

75 { 768, 15, 6144, 11, 21, 19, 19, {

76 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },

77 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },

78 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },

79 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },

80 { 21, 22, -12 }

81 }

82 },

83 /* 6BPP/14BPC */

84 { 768, 15, 6144, 15, 25, 23, 27, {

85 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },

86 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },

87 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },

88 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },

89 { 25, 26, -12 }

90 }

91 },

92 /* 6BPP/16BPC */

93 { 768, 15, 6144, 19, 29, 27, 27, {

94 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },

95 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },

96 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },

97 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },

98 { 29, 30, -12 }

99 }

100 },

101 },

102 {

103 /* 8BPP/8BPC */

104 { 512, 12, 6144, 3, 12, 11, 11, {

105 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },

106 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },

107 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },

108 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }

109 }

110 },

111 /* 8BPP/10BPC */

112 { 512, 12, 6144, 7, 16, 15, 15, {

113 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },

114 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },

115 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },

116 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }

117 }

118 },

119 /* 8BPP/12BPC */

120 { 512, 12, 6144, 11, 20, 19, 19, {

121 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },

122 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },

123 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },

124 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },

125 { 21, 23, -12 }

126 }

127 },

128 /* 8BPP/14BPC */

129 { 512, 12, 6144, 15, 24, 23, 23, {

130 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },

131 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },

132 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },

133 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },

134 { 24, 25, -12 }

135 }

136 },

137 /* 8BPP/16BPC */

138 { 512, 12, 6144, 19, 28, 27, 27, {

139 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },

140 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },

141 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },

142 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },

143 { 28, 29, -12 }

144 }

145 },

146 },

147 {

148 /* 10BPP/8BPC */

149 { 410, 15, 5632, 3, 12, 11, 11, {

150 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },

151 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },

152 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },

153 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }

154 }

155 },

156 /* 10BPP/10BPC */

157 { 410, 15, 5632, 7, 16, 15, 15, {

158 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },

159 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },

160 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },

161 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }

162 }

163 },

164 /* 10BPP/12BPC */

165 { 410, 15, 5632, 11, 20, 19, 19, {

166 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },

167 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },

168 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },

169 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },

170 { 19, 20, -12 }

171 }

172 },

173 /* 10BPP/14BPC */

174 { 410, 15, 5632, 15, 24, 23, 23, {

175 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },

176 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },

177 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },

178 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },

179 { 23, 24, -12 }

180 }

181 },

182 /* 10BPP/16BPC */

183 { 410, 15, 5632, 19, 28, 27, 27, {

184 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },

185 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },

186 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },

187 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },

188 { 27, 28, -12 }

189 }

190 },

191 },

192 {

193 /* 12BPP/8BPC */

194 { 341, 15, 2048, 3, 12, 11, 11, {

195 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },

196 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },

197 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },

198 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }

199 }

200 },

201 /* 12BPP/10BPC */

202 { 341, 15, 2048, 7, 16, 15, 15, {

203 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },

204 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },

205 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },

206 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }

207 }

208 },

209 /* 12BPP/12BPC */

210 { 341, 15, 2048, 11, 20, 19, 19, {

211 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },

212 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },

213 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },

214 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },

215 { 21, 23, -12 }

216 }

217 },

218 /* 12BPP/14BPC */

219 { 341, 15, 2048, 15, 24, 23, 23, {

220 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },

221 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },

222 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },

223 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },

224 { 22, 23, -12 }

225 }

226 },

227 /* 12BPP/16BPC */

228 { 341, 15, 2048, 19, 28, 27, 27, {

229 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },

230 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },

231 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },

232 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },

233 { 26, 27, -12 }

234 }

235 },

236 },

237 {

238 /* 15BPP/8BPC */

239 { 273, 15, 2048, 3, 12, 11, 11, {

240 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },

241 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },

242 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },

243 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }

244 }

245 },

246 /* 15BPP/10BPC */

247 { 273, 15, 2048, 7, 16, 15, 15, {

248 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },

249 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },

250 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },

251 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }

252 }

253 },

254 /* 15BPP/12BPC */

255 { 273, 15, 2048, 11, 20, 19, 19, {

256 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },

257 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },

258 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },

259 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },

260 { 16, 17, -12 }

261 }

262 },

263 /* 15BPP/14BPC */

264 { 273, 15, 2048, 15, 24, 23, 23, {

265 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },

266 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },

267 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },

268 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },

269 { 20, 21, -12 }

270 }

271 },

272 /* 15BPP/16BPC */

273 { 273, 15, 2048, 19, 28, 27, 27, {

274 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },

275 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },

276 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },

277 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },

278 { 24, 25, -12 }

279 }

280 }

281 }

282

283 };

284

285 static int get_row_index_for_rc_params(u16 compressed_bpp)

286 {

287 switch (compressed_bpp) {

288 case 6:

289 return ROW_INDEX_6BPP;

290 case 8:

291 return ROW_INDEX_8BPP;

292 case 10:

293 return ROW_INDEX_10BPP;

294 case 12:

295 return ROW_INDEX_12BPP;

296 case 15:

297 return ROW_INDEX_15BPP;

298 default:

299 return -EINVAL;

300 }

301 }

302

303 static int get_column_index_for_rc_params(u8 bits_per_component)

304 {

305 switch (bits_per_component) {

306 case 8:

307 return COLUMN_INDEX_8BPC;

308 case 10:

309 return COLUMN_INDEX_10BPC;

310 case 12:

311 return COLUMN_INDEX_12BPC;

312 case 14:

313 return COLUMN_INDEX_14BPC;

314 case 16:

315 return COLUMN_INDEX_16BPC;

316 default:

317 return -EINVAL;

318 }

319 }

320

321 static const struct rc_parameters *get_rc_params(u16 compressed_bpp,

322 u8 bits_per_component)

323 {

324 int row_index, column_index;

325

326 row_index = get_row_index_for_rc_params(compressed_bpp);

327 if (row_index < 0)

328 return NULL;

329

330 column_index = get_column_index_for_rc_params(bits_per_component);

331 if (column_index < 0)

332 return NULL;

333

334 return &rc_parameters[row_index][column_index];

335 }

336

337 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)

338 {

339 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

340 struct drm_i915_private *i915 = to_i915(crtc->base.dev);

341 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

342 enum pipe pipe = crtc->pipe;

343

344 if (!INTEL_INFO(i915)->display.has_dsc)

345 return false;

346

347 /* On TGL, DSC is supported on all Pipes */

348 if (DISPLAY_VER(i915) >= 12)

349 return true;

350

351 if (DISPLAY_VER(i915) >= 11 &&

352 (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP ||

353 cpu_transcoder == TRANSCODER_DSI_0 ||

354 cpu_transcoder == TRANSCODER_DSI_1))

355 return true;

356

357 return false;

358 }

359

360 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)

361 {

362 struct drm_i915_private *i915 = to_i915(crtc->base.dev);

363

364 if (DISPLAY_VER(i915) >= 12)

365 return true;

366

367 if (cpu_transcoder == TRANSCODER_EDP ||

368 cpu_transcoder == TRANSCODER_DSI_0 ||

369 cpu_transcoder == TRANSCODER_DSI_1)

370 return false;

371

372 /* There's no pipe A DSC engine on ICL */

373 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);

374

375 return true;

376 }

377

378 static void

379 calculate_rc_params(struct rc_parameters *rc,

380 struct drm_dsc_config *vdsc_cfg)

381 {

382 int bpc = vdsc_cfg->bits_per_component;

383 int bpp = vdsc_cfg->bits_per_pixel >> 4;

384 int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };

385 int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };

386 int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };

387 int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };

388 int qp_bpc_modifier = (bpc - 8) * 2;

389 u32 res, buf_i, bpp_i;

390

391 if (vdsc_cfg->slice_height >= 8)

392 rc->first_line_bpg_offset =

393 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);

394 else

395 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);

396

397 /* Our hw supports only 444 modes as of today */

398 if (bpp >= 12)

399 rc->initial_offset = 2048;

400 else if (bpp >= 10)

401 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);

402 else if (bpp >= 8)

403 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);

404 else

405 rc->initial_offset = 6144;

406

407 /* initial_xmit_delay = rc_model_size/2/compression_bpp */

408 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);

409

410 rc->flatness_min_qp = 3 + qp_bpc_modifier;

411 rc->flatness_max_qp = 12 + qp_bpc_modifier;

412

413 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;

414 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;

415

416 bpp_i = (2 * (bpp - 6));

417 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {

418 /* Read range_minqp and range_max_qp from qp tables */

419 rc->rc_range_params[buf_i].range_min_qp =

420 intel_lookup_range_min_qp(bpc, buf_i, bpp_i);

421 rc->rc_range_params[buf_i].range_max_qp =

422 intel_lookup_range_max_qp(bpc, buf_i, bpp_i);

423

424 /* Calculate range_bgp_offset */

425 if (bpp <= 6) {

426 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];

427 } else if (bpp <= 8) {

428 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);

429 rc->rc_range_params[buf_i].range_bpg_offset =

430 ofs_und6[buf_i] + res;

431 } else if (bpp <= 12) {

432 rc->rc_range_params[buf_i].range_bpg_offset =

433 ofs_und8[buf_i];

434 } else if (bpp <= 15) {

435 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);

436 rc->rc_range_params[buf_i].range_bpg_offset =

437 ofs_und12[buf_i] + res;

438 } else {

439 rc->rc_range_params[buf_i].range_bpg_offset =

440 ofs_und15[buf_i];

441 }

442 }

443 }

444

445 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)

446 {

447 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);

448 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

449 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;

450 u16 compressed_bpp = pipe_config->dsc.compressed_bpp;

451 const struct rc_parameters *rc_params;

452 struct rc_parameters *rc = NULL;

453 u8 i = 0;

454

455 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;

456 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;

457 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,

458 pipe_config->dsc.slice_count);

459

460 /* Gen 11 does not support YCbCr */

461 vdsc_cfg->simple_422 = false;

462 /* Gen 11 does not support VBR */

463 vdsc_cfg->vbr_enable = false;

464

465 /* Gen 11 only supports integral values of bpp */

466 vdsc_cfg->bits_per_pixel = compressed_bpp << 4;

467 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;

468

469 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {

470 /*

471 * six 0s are appended to the lsb of each threshold value

472 * internally in h/w.

473 * Only 8 bits are allowed for programming RcBufThreshold

474 */

475 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;

476 }

477

478 /*

479 * For 6bpp, RC Buffer threshold 12 and 13 need a different value

480 * as per C Model

481 */

482 if (compressed_bpp == 6) {

483 vdsc_cfg->rc_buf_thresh[12] = 0x7C;

484 vdsc_cfg->rc_buf_thresh[13] = 0x7D;

485 }

486

487 /*

488 * From XE_LPD onwards we supports compression bpps in steps of 1

489 * upto uncompressed bpp-1, hence add calculations for all the rc

490 * parameters

491 */

492 if (DISPLAY_VER(dev_priv) >= 13) {

493 rc = kmalloc(sizeof(*rc), GFP_KERNEL);

494 if (!rc)

495 return -ENOMEM;

496

497 calculate_rc_params(rc, vdsc_cfg);

498 rc_params = rc;

499 } else {

500 rc_params = get_rc_params(compressed_bpp,

501 vdsc_cfg->bits_per_component);

502 if (!rc_params)

503 return -EINVAL;

504 }

505

506 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;

507 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;

508 vdsc_cfg->initial_offset = rc_params->initial_offset;

509 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;

510 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;

511 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;

512 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;

513

514 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {

515 vdsc_cfg->rc_range_params[i].range_min_qp =

516 rc_params->rc_range_params[i].range_min_qp;

517 vdsc_cfg->rc_range_params[i].range_max_qp =

518 rc_params->rc_range_params[i].range_max_qp;

519 /*

520 * Range BPG Offset uses 2's complement and is only a 6 bits. So

521 * mask it to get only 6 bits.

522 */

523 vdsc_cfg->rc_range_params[i].range_bpg_offset =

524 rc_params->rc_range_params[i].range_bpg_offset &

525 DSC_RANGE_BPG_OFFSET_MASK;

526 }

527

528 /*

529 * BitsPerComponent value determines mux_word_size:

530 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to

531 * 48 bits otherwise 64

532 */

533 if (vdsc_cfg->bits_per_component <= 10)

534 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;

535 else

536 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;

537

538 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */

539 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /

540 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);

541

542 kfree(rc);

543

544 return 0;

545 }

546

547 enum intel_display_power_domain

548 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)

549 {

550 struct drm_i915_private *i915 = to_i915(crtc->base.dev);

551 enum pipe pipe = crtc->pipe;

552

553 /*

554 * VDSC/joining uses a separate power well, PW2, and requires

555 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:

556 *

557 * - ICL eDP/DSI transcoder

558 * - Display version 12 (except RKL) pipe A

559 *

560 * For any other pipe, VDSC/joining uses the power well associated with

561 * the pipe in use. Hence another reference on the pipe power domain

562 * will suffice. (Except no VDSC/joining on ICL pipe A.)

563 */

564 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)

565 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;

566 else if (is_pipe_dsc(crtc, cpu_transcoder))

567 return POWER_DOMAIN_PIPE(pipe);

568 else

569 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;

570 }

571

572 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)

573 {

574 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

575 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

576 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

577 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

578 enum pipe pipe = crtc->pipe;

579 u32 pps_val = 0;

580 u32 rc_buf_thresh_dword[4];

581 u32 rc_range_params_dword[8];

582 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;

583 int i = 0;

584

585 if (crtc_state->bigjoiner)

586 num_vdsc_instances *= 2;

587

588 /* Populate PICTURE_PARAMETER_SET_0 registers */

589 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<

590 DSC_VER_MIN_SHIFT |

591 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |

592 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;

593 if (vdsc_cfg->block_pred_enable)

594 pps_val |= DSC_BLOCK_PREDICTION;

595 if (vdsc_cfg->convert_rgb)

596 pps_val |= DSC_COLOR_SPACE_CONVERSION;

597 if (vdsc_cfg->simple_422)

598 pps_val |= DSC_422_ENABLE;

599 if (vdsc_cfg->vbr_enable)

600 pps_val |= DSC_VBR_ENABLE;

601 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);

602 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

603 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,

604 pps_val);

605 /*

606 * If 2 VDSC instances are needed, configure PPS for second

607 * VDSC

608 */

609 if (crtc_state->dsc.dsc_split)

610 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,

611 pps_val);

612 } else {

613 intel_de_write(dev_priv,

614 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),

615 pps_val);

616 if (crtc_state->dsc.dsc_split)

617 intel_de_write(dev_priv,

618 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),

619 pps_val);

620 }

621

622 /* Populate PICTURE_PARAMETER_SET_1 registers */

623 pps_val = 0;

624 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);

625 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);

626 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

627 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,

628 pps_val);

629 /*

630 * If 2 VDSC instances are needed, configure PPS for second

631 * VDSC

632 */

633 if (crtc_state->dsc.dsc_split)

634 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,

635 pps_val);

636 } else {

637 intel_de_write(dev_priv,

638 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),

639 pps_val);

640 if (crtc_state->dsc.dsc_split)

641 intel_de_write(dev_priv,

642 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),

643 pps_val);

644 }

645

646 /* Populate PICTURE_PARAMETER_SET_2 registers */

647 pps_val = 0;

648 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |

649 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);

650 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);

651 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

652 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,

653 pps_val);

654 /*

655 * If 2 VDSC instances are needed, configure PPS for second

656 * VDSC

657 */

658 if (crtc_state->dsc.dsc_split)

659 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,

660 pps_val);

661 } else {

662 intel_de_write(dev_priv,

663 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),

664 pps_val);

665 if (crtc_state->dsc.dsc_split)

666 intel_de_write(dev_priv,

667 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),

668 pps_val);

669 }

670

671 /* Populate PICTURE_PARAMETER_SET_3 registers */

672 pps_val = 0;

673 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |

674 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);

675 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);

676 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

677 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,

678 pps_val);

679 /*

680 * If 2 VDSC instances are needed, configure PPS for second

681 * VDSC

682 */

683 if (crtc_state->dsc.dsc_split)

684 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,

685 pps_val);

686 } else {

687 intel_de_write(dev_priv,

688 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),

689 pps_val);

690 if (crtc_state->dsc.dsc_split)

691 intel_de_write(dev_priv,

692 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),

693 pps_val);

694 }

695

696 /* Populate PICTURE_PARAMETER_SET_4 registers */

697 pps_val = 0;

698 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |

699 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);

700 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);

701 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

702 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,

703 pps_val);

704 /*

705 * If 2 VDSC instances are needed, configure PPS for second

706 * VDSC

707 */

708 if (crtc_state->dsc.dsc_split)

709 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,

710 pps_val);

711 } else {

712 intel_de_write(dev_priv,

713 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),

714 pps_val);

715 if (crtc_state->dsc.dsc_split)

716 intel_de_write(dev_priv,

717 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),

718 pps_val);

719 }

720

721 /* Populate PICTURE_PARAMETER_SET_5 registers */

722 pps_val = 0;

723 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |

724 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);

725 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);

726 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

727 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,

728 pps_val);

729 /*

730 * If 2 VDSC instances are needed, configure PPS for second

731 * VDSC

732 */

733 if (crtc_state->dsc.dsc_split)

734 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,

735 pps_val);

736 } else {

737 intel_de_write(dev_priv,

738 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),

739 pps_val);

740 if (crtc_state->dsc.dsc_split)

741 intel_de_write(dev_priv,

742 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),

743 pps_val);

744 }

745

746 /* Populate PICTURE_PARAMETER_SET_6 registers */

747 pps_val = 0;

748 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |

749 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |

750 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |

751 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);

752 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);

753 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

754 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,

755 pps_val);

756 /*

757 * If 2 VDSC instances are needed, configure PPS for second

758 * VDSC

759 */

760 if (crtc_state->dsc.dsc_split)

761 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,

762 pps_val);

763 } else {

764 intel_de_write(dev_priv,

765 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),

766 pps_val);

767 if (crtc_state->dsc.dsc_split)

768 intel_de_write(dev_priv,

769 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),

770 pps_val);

771 }

772

773 /* Populate PICTURE_PARAMETER_SET_7 registers */

774 pps_val = 0;

775 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |

776 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);

777 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);

778 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

779 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,

780 pps_val);

781 /*

782 * If 2 VDSC instances are needed, configure PPS for second

783 * VDSC

784 */

785 if (crtc_state->dsc.dsc_split)

786 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,

787 pps_val);

788 } else {

789 intel_de_write(dev_priv,

790 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),

791 pps_val);

792 if (crtc_state->dsc.dsc_split)

793 intel_de_write(dev_priv,

794 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),

795 pps_val);

796 }

797

798 /* Populate PICTURE_PARAMETER_SET_8 registers */

799 pps_val = 0;

800 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |

801 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);

802 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);

803 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

804 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,

805 pps_val);

806 /*

807 * If 2 VDSC instances are needed, configure PPS for second

808 * VDSC

809 */

810 if (crtc_state->dsc.dsc_split)

811 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,

812 pps_val);

813 } else {

814 intel_de_write(dev_priv,

815 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),

816 pps_val);

817 if (crtc_state->dsc.dsc_split)

818 intel_de_write(dev_priv,

819 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),

820 pps_val);

821 }

822

823 /* Populate PICTURE_PARAMETER_SET_9 registers */

824 pps_val = 0;

825 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |

826 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);

827 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);

828 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

829 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,

830 pps_val);

831 /*

832 * If 2 VDSC instances are needed, configure PPS for second

833 * VDSC

834 */

835 if (crtc_state->dsc.dsc_split)

836 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,

837 pps_val);

838 } else {

839 intel_de_write(dev_priv,

840 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),

841 pps_val);

842 if (crtc_state->dsc.dsc_split)

843 intel_de_write(dev_priv,

844 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),

845 pps_val);

846 }

847

848 /* Populate PICTURE_PARAMETER_SET_10 registers */

849 pps_val = 0;

850 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |

851 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |

852 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |

853 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);

854 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);

855 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

856 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,

857 pps_val);

858 /*

859 * If 2 VDSC instances are needed, configure PPS for second

860 * VDSC

861 */

862 if (crtc_state->dsc.dsc_split)

863 intel_de_write(dev_priv,

864 DSCC_PICTURE_PARAMETER_SET_10, pps_val);

865 } else {

866 intel_de_write(dev_priv,

867 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),

868 pps_val);

869 if (crtc_state->dsc.dsc_split)

870 intel_de_write(dev_priv,

871 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),

872 pps_val);

873 }

874

875 /* Populate Picture parameter set 16 */

876 pps_val = 0;

877 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |

878 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /

879 vdsc_cfg->slice_width) |

880 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /

881 vdsc_cfg->slice_height);

882 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);

883 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

884 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,

885 pps_val);

886 /*

887 * If 2 VDSC instances are needed, configure PPS for second

888 * VDSC

889 */

890 if (crtc_state->dsc.dsc_split)

891 intel_de_write(dev_priv,

892 DSCC_PICTURE_PARAMETER_SET_16, pps_val);

893 } else {

894 intel_de_write(dev_priv,

895 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),

896 pps_val);

897 if (crtc_state->dsc.dsc_split)

898 intel_de_write(dev_priv,

899 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),

900 pps_val);

901 }

902

903 /* Populate the RC_BUF_THRESH registers */

904 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));

905 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {

906 rc_buf_thresh_dword[i / 4] |=

907 (u32)(vdsc_cfg->rc_buf_thresh[i] <<

908 BITS_PER_BYTE * (i % 4));

909 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,

910 rc_buf_thresh_dword[i / 4]);

911 }

912 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

913 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,

914 rc_buf_thresh_dword[0]);

915 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,

916 rc_buf_thresh_dword[1]);

917 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,

918 rc_buf_thresh_dword[2]);

919 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,

920 rc_buf_thresh_dword[3]);

921 if (crtc_state->dsc.dsc_split) {

922 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,

923 rc_buf_thresh_dword[0]);

924 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,

925 rc_buf_thresh_dword[1]);

926 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,

927 rc_buf_thresh_dword[2]);

928 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,

929 rc_buf_thresh_dword[3]);

930 }

931 } else {

932 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),

933 rc_buf_thresh_dword[0]);

934 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),

935 rc_buf_thresh_dword[1]);

936 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),

937 rc_buf_thresh_dword[2]);

938 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),

939 rc_buf_thresh_dword[3]);

940 if (crtc_state->dsc.dsc_split) {

941 intel_de_write(dev_priv,

942 ICL_DSC1_RC_BUF_THRESH_0(pipe),

943 rc_buf_thresh_dword[0]);

944 intel_de_write(dev_priv,

945 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),

946 rc_buf_thresh_dword[1]);

947 intel_de_write(dev_priv,

948 ICL_DSC1_RC_BUF_THRESH_1(pipe),

949 rc_buf_thresh_dword[2]);

950 intel_de_write(dev_priv,

951 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),

952 rc_buf_thresh_dword[3]);

953 }

954 }

955

956 /* Populate the RC_RANGE_PARAMETERS registers */

957 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));

958 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {

959 rc_range_params_dword[i / 2] |=

960 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<

961 RC_BPG_OFFSET_SHIFT) |

962 (vdsc_cfg->rc_range_params[i].range_max_qp <<

963 RC_MAX_QP_SHIFT) |

964 (vdsc_cfg->rc_range_params[i].range_min_qp <<

965 RC_MIN_QP_SHIFT)) << 16 * (i % 2));

966 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,

967 rc_range_params_dword[i / 2]);

968 }

969 if (!is_pipe_dsc(crtc, cpu_transcoder)) {

970 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,

971 rc_range_params_dword[0]);

972 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,

973 rc_range_params_dword[1]);

974 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,

975 rc_range_params_dword[2]);

976 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,

977 rc_range_params_dword[3]);

978 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,

979 rc_range_params_dword[4]);

980 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,

981 rc_range_params_dword[5]);

982 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,

983 rc_range_params_dword[6]);

984 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,

985 rc_range_params_dword[7]);

986 if (crtc_state->dsc.dsc_split) {

987 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,

988 rc_range_params_dword[0]);

989 intel_de_write(dev_priv,

990 DSCC_RC_RANGE_PARAMETERS_0_UDW,

991 rc_range_params_dword[1]);

992 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,

993 rc_range_params_dword[2]);

994 intel_de_write(dev_priv,

995 DSCC_RC_RANGE_PARAMETERS_1_UDW,

996 rc_range_params_dword[3]);

997 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,

998 rc_range_params_dword[4]);

999 intel_de_write(dev_priv,

1000 DSCC_RC_RANGE_PARAMETERS_2_UDW,

1001 rc_range_params_dword[5]);

1002 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,

1003 rc_range_params_dword[6]);

1004 intel_de_write(dev_priv,

1005 DSCC_RC_RANGE_PARAMETERS_3_UDW,

1006 rc_range_params_dword[7]);

1007 }

1008 } else {

1009 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),

1010 rc_range_params_dword[0]);

1011 intel_de_write(dev_priv,

1012 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),

1013 rc_range_params_dword[1]);

1014 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),

1015 rc_range_params_dword[2]);

1016 intel_de_write(dev_priv,

1017 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),

1018 rc_range_params_dword[3]);

1019 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),

1020 rc_range_params_dword[4]);

1021 intel_de_write(dev_priv,

1022 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),

1023 rc_range_params_dword[5]);

1024 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),

1025 rc_range_params_dword[6]);

1026 intel_de_write(dev_priv,

1027 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),

1028 rc_range_params_dword[7]);

1029 if (crtc_state->dsc.dsc_split) {

1030 intel_de_write(dev_priv,

1031 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),

1032 rc_range_params_dword[0]);

1033 intel_de_write(dev_priv,

1034 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),

1035 rc_range_params_dword[1]);

1036 intel_de_write(dev_priv,

1037 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),

1038 rc_range_params_dword[2]);

1039 intel_de_write(dev_priv,

1040 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),

1041 rc_range_params_dword[3]);

1042 intel_de_write(dev_priv,

1043 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),

1044 rc_range_params_dword[4]);

1045 intel_de_write(dev_priv,

1046 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),

1047 rc_range_params_dword[5]);

1048 intel_de_write(dev_priv,

1049 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),

1050 rc_range_params_dword[6]);

1051 intel_de_write(dev_priv,

1052 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),

1053 rc_range_params_dword[7]);

1054 }

1055 }

1056 }

1057

1058 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,

1059 const struct intel_crtc_state *crtc_state)

1060 {

1061 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

1062 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

1063 struct mipi_dsi_device *dsi;

1064 struct drm_dsc_picture_parameter_set pps;

1065 enum port port;

1066

1067 if (!crtc_state->dsc.compression_enable)

1068 return;

1069

1070 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);

1071

1072 for_each_dsi_port(port, intel_dsi->ports) {

1073 dsi = intel_dsi->dsi_hosts[port]->device;

1074

1075 mipi_dsi_picture_parameter_set(dsi, &pps);

1076 mipi_dsi_compression_mode(dsi, true);

1077 }

1078 }

1079

1080 void intel_dsc_dp_pps_write(struct intel_encoder *encoder,

1081 const struct intel_crtc_state *crtc_state)

1082 {

1083 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

1084 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

1085 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;

1086

1087 if (!crtc_state->dsc.compression_enable)

1088 return;

1089

1090 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */

1091 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);

1092

1093 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */

1094 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);

1095

1096 dig_port->write_infoframe(encoder, crtc_state,

1097 DP_SDP_PPS, &dp_dsc_pps_sdp,

1098 sizeof(dp_dsc_pps_sdp));

1099 }

1100

1101 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)

1102 {

1103 return is_pipe_dsc(crtc, cpu_transcoder) ?

1104 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;

1105 }

1106

1107 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)

1108 {

1109 return is_pipe_dsc(crtc, cpu_transcoder) ?

1110 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;

1111 }

1112

1113 static struct intel_crtc *

1114 _get_crtc_for_pipe(struct drm_i915_private *i915, enum pipe pipe)

1115 {

1116 if (!intel_pipe_valid(i915, pipe))

1117 return NULL;

1118

1119 return intel_get_crtc_for_pipe(i915, pipe);

1120 }

1121

1122 struct intel_crtc *

1123 intel_dsc_get_bigjoiner_secondary(const struct intel_crtc *primary_crtc)

1124 {

1125 return _get_crtc_for_pipe(to_i915(primary_crtc->base.dev), primary_crtc->pipe + 1);

1126 }

1127

1128 static struct intel_crtc *

1129 intel_dsc_get_bigjoiner_primary(const struct intel_crtc *secondary_crtc)

1130 {

1131 return _get_crtc_for_pipe(to_i915(secondary_crtc->base.dev), secondary_crtc->pipe - 1);

1132 }

1133

1134 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)

1135 {

1136 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

1137 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

1138 u32 dss_ctl1_val = 0;

1139

1140 if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {

1141 if (crtc_state->bigjoiner_slave)

1142 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;

1143 else

1144 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;

1145

1146 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);

1147 }

1148 }

1149

1150 void intel_dsc_enable(const struct intel_crtc_state *crtc_state)

1151 {

1152 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

1153 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

1154 u32 dss_ctl1_val = 0;

1155 u32 dss_ctl2_val = 0;

1156

1157 if (!crtc_state->dsc.compression_enable)

1158 return;

1159

1160 intel_dsc_pps_configure(crtc_state);

1161

1162 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;

1163 if (crtc_state->dsc.dsc_split) {

1164 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;

1165 dss_ctl1_val |= JOINER_ENABLE;

1166 }

1167 if (crtc_state->bigjoiner) {

1168 dss_ctl1_val |= BIG_JOINER_ENABLE;

1169 if (!crtc_state->bigjoiner_slave)

1170 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;

1171 }

1172 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);

1173 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);

1174 }

1175

1176 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)

1177 {

1178 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);

1179 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

1180

1181 /* Disable only if either of them is enabled */

1182 if (old_crtc_state->dsc.compression_enable ||

1183 old_crtc_state->bigjoiner) {

1184 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);

1185 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);

1186 }

1187 }

1188

1189 void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)

1190 {

1191 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

1192 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

1193 u32 dss_ctl1;

1194

1195 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder));

1196 if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {

1197 crtc_state->bigjoiner = true;

1198 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc);

1199 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc);

1200 } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {

1201 crtc_state->bigjoiner = true;

1202 crtc_state->bigjoiner_slave = true;

1203 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc);

1204 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc);

1205 }

1206 }

1207

1208 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)

1209 {

1210 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

1211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

1212 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

1213 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

1214 enum pipe pipe = crtc->pipe;

1215 enum intel_display_power_domain power_domain;

1216 intel_wakeref_t wakeref;

1217 u32 dss_ctl1, dss_ctl2, val;

1218

1219 if (!intel_dsc_source_support(crtc_state))

1220 return;

1221

1222 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder);

1223

1224 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);

1225 if (!wakeref)

1226 return;

1227

1228 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));

1229 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));

1230

1231 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;

1232 if (!crtc_state->dsc.compression_enable)

1233 goto out;

1234

1235 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&

1236 (dss_ctl1 & JOINER_ENABLE);

1237

1238 if (dss_ctl1 & BIG_JOINER_ENABLE) {

1239 crtc_state->bigjoiner = true;

1240

1241 if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) {

1242 crtc_state->bigjoiner_slave = true;

1243 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc);

1244 } else {

1245 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc);

1246 }

1247 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc);

1248 }

1249

1250 /* FIXME: add more state readout as needed */

1251

1252 /* PPS1 */

1253 if (!is_pipe_dsc(crtc, cpu_transcoder))

1254 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);

1255 else

1256 val = intel_de_read(dev_priv,

1257 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));

1258 vdsc_cfg->bits_per_pixel = val;

1259 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;

1260 out:

1261 intel_display_power_put(dev_priv, power_domain, wakeref);

1262 }