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[MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models
authorDuane Sand <duane.sand@imgtec.com>
Mon, 14 Jul 2014 22:30:14 +0000 (15:30 -0700)
committerElliott Hughes <enh@google.com>
Thu, 24 Jul 2014 04:04:20 +0000 (21:04 -0700)
commitc86950cb3f50ead0c9a9d0366b870d6c6e1b91c8
treeb21dc20111743fbbacc80bc8a06ca794dfef2333
parentbc74ecfaf5de47056fd8a48db65c0e5aef892f0c
[MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models

Save and restore floating point registers via 64-bit
load/stores when possible.  Use assembler's builtin macro
ops to generate pairs of 32-bit load/stores on Mips I cpus.

Some cpus or FR modes have only 16 even-numbered dp fp regs.
This is exposed by _MIPS_FPSET, defined by existing compilers.

(cherry picked from commit dd37251c473e1483faba0fd5aaf30e7a55582e8a)

Change-Id: Ibd43653701a363a77af85121d3cbd229d132a06a
libc/arch-mips/bionic/_setjmp.S
libc/arch-mips/bionic/setjmp.S
libc/arch-mips64/bionic/_setjmp.S
libc/arch-mips64/bionic/setjmp.S