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[DAG] Do MergeConsecutiveStores again before Instruction Selection
authorNirav Dave <niravd@google.com>
Mon, 27 Nov 2017 15:28:15 +0000 (15:28 +0000)
committerNirav Dave <niravd@google.com>
Mon, 27 Nov 2017 15:28:15 +0000 (15:28 +0000)
commitdbbb6c5fc3642987430866dffdf710df4f616ac7
treec747d6106fb07ea836450e9ebfdcdb8491307b83
parent0782e893a9946ee3012d3d1a5ad9eaf12ea07db1
[DAG] Do MergeConsecutiveStores again before Instruction Selection

Summary:

Now that store-merge is only generates type-safe stores, do a second
pass just before instruction selection to allow lowered intrinsics to
be merged as well.

Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319036 91177308-0d34-0410-b5e6-96231b3b80d8
13 files changed:
include/llvm/CodeGen/TargetLowering.h
lib/Target/AArch64/AArch64ISelLowering.cpp
test/CodeGen/AArch64/arm64-complex-ret.ll
test/CodeGen/AArch64/arm64-narrow-st-merge.ll
test/CodeGen/AArch64/arm64-variadic-aapcs.ll
test/CodeGen/AArch64/tailcall-explicit-sret.ll
test/CodeGen/AArch64/tailcall-implicit-sret.ll
test/CodeGen/AMDGPU/amdgpu.private-memory.ll
test/CodeGen/ARM/fp16-promote.ll
test/CodeGen/BPF/undef.ll
test/CodeGen/Mips/cconv/vector.ll
test/CodeGen/Mips/llvm-ir/extractelement.ll
test/CodeGen/SystemZ/fp-move-13.ll