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[AMDGPU] Fix DPP combiner
authorValery Pykhtin <Valery.Pykhtin@amd.com>
Wed, 9 Jan 2019 13:43:32 +0000 (13:43 +0000)
committerValery Pykhtin <Valery.Pykhtin@amd.com>
Wed, 9 Jan 2019 13:43:32 +0000 (13:43 +0000)
commite3e2923a39cbec3b3bc3a7d3f0e9a77a4115080e
treee5b6a0640116c26e051400e218f781ec8e3cf8fc
parentc547d68a5684f69cc3c59727e09a41bfaf1a97f2
[AMDGPU] Fix DPP combiner

Fixed issue with identity values and other cases, f32/f16 identity values to be added later. fma/mac instructions is disabled for now.
Test is fully reworked, added comments. Other fixes:

1. dpp move with uses and old reg initializer should be in the same BB.
2. bound_ctrl:0 is only considered when bank_mask and row_mask are fully enabled (0xF). Othervise the old register value is checked for identity.
3. Added add, subrev, and, or instructions to the old folding function.
4. Kill flag is cleared for the src0 (DPP register) as it may be copied into more than one user.

Differential revision: https://reviews.llvm.org/D55444

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350721 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/CodeGen/TargetInstrInfo.h
lib/Target/AMDGPU/GCNDPPCombine.cpp
lib/Target/AMDGPU/SIInstrInfo.cpp
lib/Target/AMDGPU/SIInstrInfo.h
test/CodeGen/AMDGPU/dpp_combine.ll [deleted file]
test/CodeGen/AMDGPU/dpp_combine.mir [new file with mode: 0644]
test/CodeGen/AMDGPU/dpp_combine_subregs.mir [deleted file]