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[RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes.
authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Fri, 25 May 2018 15:55:37 +0000 (15:55 +0000)
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Fri, 25 May 2018 15:55:37 +0000 (15:55 +0000)
commite68d92b3873c025b3d5adf2ad62fa73866d3a3e2
tree3e2fe60e841e33708b062bca5f7ede7a816b3c89
parentf1f35aaa79897871e64a763e6c0f827a11dcb8e3
[RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes.

This patch is the first of a sequence of three patches described by the LLVM-dev
RFC "MC support for variant scheduling classes".
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html

The goal of this patch is to introduce a new class of scheduling predicates for
SchedReadVariant and SchedWriteVariant.

An MCSchedPredicate can be used instead of a normal SchedPredicate to model
checks on the instruction (either a MachineInstr or a MCInst).
Internally, an MCSchedPredicate encapsulates an MCInstPredicate definition.
MCInstPredicate allows the definition of expressions with a well-known semantic,
that can be used to generate code for both MachineInstr and MCInst.

This is the first step toward teaching to tools like lllvm-mca how to resolve
variant scheduling classes.

Differential Revision: https://reviews.llvm.org/D46695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333282 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/Target/Target.td
include/llvm/Target/TargetInstrPredicate.td [new file with mode: 0644]
include/llvm/Target/TargetSchedule.td
utils/TableGen/CMakeLists.txt
utils/TableGen/InstrInfoEmitter.cpp
utils/TableGen/PredicateExpander.cpp [new file with mode: 0644]
utils/TableGen/PredicateExpander.h [new file with mode: 0644]
utils/TableGen/SubtargetEmitter.cpp